| Message ID | 20231212-x1e80100-clock-controllers-v1-0-0de1af44dcb3@linaro.org |
|---|---|
| Headers | show |
| Series | clk: qcom: Add TCSR, GPU, CAM and DISP clock controllers for X1E80100 | expand |
On Tue, 12 Dec 2023 at 00:46, Abel Vesa <abel.vesa@linaro.org> wrote: > > From: Rajendra Nayak <quic_rjendra@quicinc.com> > > Zonda ole pll has as extra PLL_OFF_CONFIG_CTL_U2 register, hence add > support for it. > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> The order of S-o-B trailers is incorrect. > --- > drivers/clk/qcom/clk-alpha-pll.c | 26 ++++++++++++++++++++++++++ > drivers/clk/qcom/clk-alpha-pll.h | 4 ++++ > 2 files changed, 30 insertions(+) > > diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c > index 05898d2a8b22..e1919b57fb65 100644 > --- a/drivers/clk/qcom/clk-alpha-pll.c > +++ b/drivers/clk/qcom/clk-alpha-pll.c > @@ -52,6 +52,7 @@ > #define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL]) > #define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U]) > #define PLL_CONFIG_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1]) > +#define PLL_CONFIG_CTL_U2(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U2]) > #define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL]) > #define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U]) > #define PLL_TEST_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1]) > @@ -228,6 +229,21 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { > [PLL_OFF_ALPHA_VAL] = 0x24, > [PLL_OFF_ALPHA_VAL_U] = 0x28, > }, > + [CLK_ALPHA_PLL_TYPE_ZONDA_OLE] = { > + [PLL_OFF_L_VAL] = 0x04, > + [PLL_OFF_ALPHA_VAL] = 0x08, > + [PLL_OFF_USER_CTL] = 0x0C, > + [PLL_OFF_USER_CTL_U] = 0x10, > + [PLL_OFF_CONFIG_CTL] = 0x14, > + [PLL_OFF_CONFIG_CTL_U] = 0x18, > + [PLL_OFF_CONFIG_CTL_U1] = 0x1C, > + [PLL_OFF_CONFIG_CTL_U2] = 0x20, > + [PLL_OFF_TEST_CTL] = 0x24, > + [PLL_OFF_TEST_CTL_U] = 0x28, > + [PLL_OFF_TEST_CTL_U1] = 0x2C, > + [PLL_OFF_OPMODE] = 0x30, > + [PLL_OFF_STATUS] = 0x3C, low-case hex please > + }, > }; > EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); > > @@ -2093,6 +2109,16 @@ const struct clk_ops clk_alpha_pll_zonda_ops = { > }; > EXPORT_SYMBOL_GPL(clk_alpha_pll_zonda_ops); > > +const struct clk_ops clk_alpha_pll_zonda_ole_ops = { > + .enable = clk_zonda_pll_enable, > + .disable = clk_zonda_pll_disable, > + .is_enabled = clk_trion_pll_is_enabled, > + .recalc_rate = clk_trion_pll_recalc_rate, > + .round_rate = clk_alpha_pll_round_rate, > + .set_rate = clk_zonda_pll_set_rate, > +}; > +EXPORT_SYMBOL(clk_alpha_pll_zonda_ole_ops); > + > void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, > const struct alpha_pll_config *config) > { > diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h > index a1a75bb12fe8..99a3db9de4a1 100644 > --- a/drivers/clk/qcom/clk-alpha-pll.h > +++ b/drivers/clk/qcom/clk-alpha-pll.h > @@ -21,6 +21,7 @@ enum { > CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION, > CLK_ALPHA_PLL_TYPE_AGERA, > CLK_ALPHA_PLL_TYPE_ZONDA, > + CLK_ALPHA_PLL_TYPE_ZONDA_OLE, > CLK_ALPHA_PLL_TYPE_LUCID_EVO, > CLK_ALPHA_PLL_TYPE_LUCID_OLE, > CLK_ALPHA_PLL_TYPE_RIVIAN_EVO, > @@ -42,6 +43,7 @@ enum { > PLL_OFF_CONFIG_CTL, > PLL_OFF_CONFIG_CTL_U, > PLL_OFF_CONFIG_CTL_U1, > + PLL_OFF_CONFIG_CTL_U2, > PLL_OFF_TEST_CTL, > PLL_OFF_TEST_CTL_U, > PLL_OFF_TEST_CTL_U1, > @@ -119,6 +121,7 @@ struct alpha_pll_config { > u32 config_ctl_val; > u32 config_ctl_hi_val; > u32 config_ctl_hi1_val; > + u32 config_ctl_hi2_val; > u32 user_ctl_val; > u32 user_ctl_hi_val; > u32 user_ctl_hi1_val; > @@ -173,6 +176,7 @@ extern const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops; > > extern const struct clk_ops clk_alpha_pll_zonda_ops; > #define clk_alpha_pll_postdiv_zonda_ops clk_alpha_pll_postdiv_fabia_ops > +extern const struct clk_ops clk_alpha_pll_zonda_ole_ops; > > extern const struct clk_ops clk_alpha_pll_lucid_evo_ops; > extern const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops; > > -- > 2.34.1 > >
On Tue, 12 Dec 2023 at 00:46, Abel Vesa <abel.vesa@linaro.org> wrote: > > From: Rajendra Nayak <quic_rjendra@quicinc.com> > > Add the dispcc clock driver for x1e80100. > > Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > --- > drivers/clk/qcom/Kconfig | 10 + > drivers/clk/qcom/Makefile | 1 + > drivers/clk/qcom/dispcc-x1e80100.c | 1699 ++++++++++++++++++++++++++++++++++++ > 3 files changed, 1710 insertions(+) Reviewed-by: Dmitry Baryshov <dmitry.baryshov@linaro.org>
On Tue, 12 Dec 2023 at 00:46, Abel Vesa <abel.vesa@linaro.org> wrote: > > From: Rajendra Nayak <quic_rjendra@quicinc.com> > > Add the camcc clock driver for x1e80100 > > Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > --- > drivers/clk/qcom/Kconfig | 8 + > drivers/clk/qcom/Makefile | 1 + > drivers/clk/qcom/camcc-x1e80100.c | 2489 +++++++++++++++++++++++++++++++++++++ > 3 files changed, 2498 insertions(+) > > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig > index 0633728c870c..4580edbd13ea 100644 > --- a/drivers/clk/qcom/Kconfig > +++ b/drivers/clk/qcom/Kconfig > @@ -20,6 +20,14 @@ menuconfig COMMON_CLK_QCOM > > if COMMON_CLK_QCOM > > +config CLK_X1E80100_CAMCC > + tristate "X1E80100 Camera Clock Controller" > + depends on ARM64 || COMPILE_TEST > + select CLK_X1E80100_GCC > + help > + Support for the camera clock controller on X1E80100 devices. > + Say Y if you want to support camera devices and camera functionality. > + > config CLK_X1E80100_DISPCC > tristate "X1E80100 Display Clock Controller" > depends on ARM64 || COMPILE_TEST > diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile > index 750b084553c6..1da65ca78e24 100644 > --- a/drivers/clk/qcom/Makefile > +++ b/drivers/clk/qcom/Makefile > @@ -21,6 +21,7 @@ clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o > obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o > obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o > obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o > +obj-$(CONFIG_CLK_X1E80100_CAMCC) += camcc-x1e80100.o > obj-$(CONFIG_CLK_X1E80100_DISPCC) += dispcc-x1e80100.o > obj-$(CONFIG_CLK_X1E80100_GCC) += gcc-x1e80100.o > obj-$(CONFIG_CLK_X1E80100_GPUCC) += gpucc-x1e80100.o > diff --git a/drivers/clk/qcom/camcc-x1e80100.c b/drivers/clk/qcom/camcc-x1e80100.c > new file mode 100644 > index 000000000000..50dc578692a1 > --- /dev/null > +++ b/drivers/clk/qcom/camcc-x1e80100.c > @@ -0,0 +1,2489 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#include <linux/clk-provider.h> > +#include <linux/mod_devicetable.h> > +#include <linux/module.h> > +#include <linux/platform_device.h> > +#include <linux/pm_runtime.h> > +#include <linux/regmap.h> > + > +#include <dt-bindings/clock/qcom,x1e80100-camcc.h> > + > +#include "clk-alpha-pll.h" > +#include "clk-branch.h" > +#include "clk-rcg.h" > +#include "clk-regmap.h" > +#include "common.h" > +#include "gdsc.h" > +#include "reset.h" > + > +enum { > + DT_BI_TCXO, > + DT_BI_TCXO_AO, > + DT_SLEEP_CLK, > +}; > + > +enum { > + P_BI_TCXO, > + P_CAM_CC_PLL0_OUT_EVEN, > + P_CAM_CC_PLL0_OUT_MAIN, > + P_CAM_CC_PLL0_OUT_ODD, > + P_CAM_CC_PLL1_OUT_EVEN, > + P_CAM_CC_PLL2_OUT_EVEN, > + P_CAM_CC_PLL2_OUT_MAIN, > + P_CAM_CC_PLL3_OUT_EVEN, > + P_CAM_CC_PLL4_OUT_EVEN, > + P_CAM_CC_PLL6_OUT_EVEN, > + P_CAM_CC_PLL8_OUT_EVEN, > + P_SLEEP_CLK, > +}; > + > +static const struct pll_vco lucid_ole_vco[] = { > + { 249600000, 2300000000, 0 }, > +}; > + > +static const struct pll_vco rivian_ole_vco[] = { > + { 777000000, 1285000000, 0 }, > +}; > + > +static const struct alpha_pll_config cam_cc_pll0_config = { > + .l = 0x3E, Lowercase hex, please. Other than that LGTM. > + .alpha = 0x8000, > + .config_ctl_val = 0x20485699, > + .config_ctl_hi_val = 0x00182261, > + .config_ctl_hi1_val = 0x82AA299C, > + .test_ctl_val = 0x00000000, > + .test_ctl_hi_val = 0x00000003, > + .test_ctl_hi1_val = 0x00009000, > + .test_ctl_hi2_val = 0x00000034, > + .user_ctl_val = 0x00008400, > + .user_ctl_hi_val = 0x00000005, > +};
This patchset adds all the missing clock controllers for Qualcomm X1E80100 platform. Another important change is the dropping of the dedicated schema of the SM8650 DISP CC as a preparatory work for documenting the DISP CC compatible for X1E801800. Initially, the TCSR clock controller was sent separately, but in order to avoid merge conflicts, all other clock controllers have been added. https://lore.kernel.org/all/20231122-x1e80100-clk-tcsrcc-v1-0-43078c6d6452@linaro.org/ Changes to TCSR clock controller since up-mentioned version: - called qcom_cc_probe instead of qcom_cc_really_probed, like Konrad suggested Signed-off-by: Abel Vesa <abel.vesa@linaro.org> --- Abel Vesa (3): dt-bindings: clock: Drop the SM8650 DISPCC dedicated schema dt-bindings: clock: qcom: Document the X1E80100 TCSR Clock Controller clk: qcom: Add TCSR clock driver for x1e80100 Rajendra Nayak (7): dt-bindings: clock: qcom: Document the X1E80100 Display Clock Controller dt-bindings: clock: qcom: Document the X1E80100 GPU Clock Controller dt-bindings: clock: qcom: Document the X1E80100 Camera Clock Controller clk: qcom: clk-alpha-pll: Add support for zonda ole pll configure clk: qcom: Add dispcc clock driver for x1e80100 clk: qcom: Add GPU clock driver for x1e80100 clk: qcom: Add camcc clock driver for x1e80100 .../bindings/clock/qcom,sm8450-camcc.yaml | 2 + .../bindings/clock/qcom,sm8450-gpucc.yaml | 2 + .../bindings/clock/qcom,sm8550-dispcc.yaml | 7 +- .../bindings/clock/qcom,sm8550-tcsr.yaml | 1 + .../bindings/clock/qcom,sm8650-dispcc.yaml | 106 - drivers/clk/qcom/Kconfig | 35 + drivers/clk/qcom/Makefile | 4 + drivers/clk/qcom/camcc-x1e80100.c | 2489 ++++++++++++++++++++ drivers/clk/qcom/clk-alpha-pll.c | 26 + drivers/clk/qcom/clk-alpha-pll.h | 4 + drivers/clk/qcom/dispcc-x1e80100.c | 1699 +++++++++++++ drivers/clk/qcom/gpucc-x1e80100.c | 659 ++++++ drivers/clk/qcom/tcsrcc-x1e80100.c | 285 +++ include/dt-bindings/clock/qcom,x1e80100-camcc.h | 135 ++ include/dt-bindings/clock/qcom,x1e80100-dispcc.h | 98 + include/dt-bindings/clock/qcom,x1e80100-gpucc.h | 41 + include/dt-bindings/clock/qcom,x1e80100-tcsr.h | 23 + include/dt-bindings/reset/qcom,x1e80100-gpucc.h | 19 + 18 files changed, 5528 insertions(+), 107 deletions(-) --- base-commit: 10b6aabadfd16f52a85603443a4778083f70882c change-id: 20231201-x1e80100-clock-controllers-ba42b0575f8a Best regards,