| Message ID | 20231208161249.1827174-1-gregory.clement@bootlin.com |
|---|---|
| Headers | show |
| Series | Add support for the Mobileye EyeQ5 SoC | expand |
On 12/8/23 7:12 PM, Gregory CLEMENT wrote: > Now that we support having the kernel in XPHYS and not only in KSEG0, > the case where ebase doesn't belong to KSEG0 is more likely to > occur. However, in this scenariowe encounter a significant and Scenario we? :-) > intimidating stack dump without any explanation. To address this, we > should eliminate the uninformative stack dump and replace it with a > warning that provides a clear explanation of the issue. > > Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> > --- > arch/mips/kernel/traps.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c > index 68f1dd54cde1c..ec0cebfd2ef7b 100644 > --- a/arch/mips/kernel/traps.c > +++ b/arch/mips/kernel/traps.c > @@ -2420,10 +2420,13 @@ void __init trap_init(void) > * EVA is special though as it allows segments to be rearranged > * and to become uncached during cache error handling. > */ > - if (!IS_ENABLED(CONFIG_EVA) && !WARN_ON(ebase_pa >= 0x20000000)) > + if (!IS_ENABLED(CONFIG_EVA) && ebase_pa < 0x20000000) > ebase = CKSEG0ADDR(ebase_pa); > else > ebase = (unsigned long)phys_to_virt(ebase_pa); > + if (ebase_pa >= 0x20000000) > + pr_warn("ebase(%pa) should better be in KSeg0", I think it's called KSEG0... [...] MBR, Sergey
On 12/8/23 7:12 PM, Gregory CLEMENT wrote: > From: Jiaxun Yang <jiaxun.yang@flygoat.com> > > NO_EXCEPT_FILL is used to indicate platform that does not > need to reserve ebase memory at start of kernel. > > This is true for all R2+ platform as they allocate ebase > memory on fly, and also true for any platform that does On the fly? > not load kernel at start of physical memory. > Using > Get rid this Kconfig symbol by use macro to detect conditions Using. > above. > > gc: use KSEG0 only for 32 bit configuration > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> [...] MBR, Sergey
On 12/8/23 7:12 PM, Gregory CLEMENT wrote: > From: Jiaxun Yang <jiaxun.yang@flygoat.com> > > Some BMIPS cpus has none standard start offset for vector interrupts. > > Handle those CPUs in vector size calculation and handler setup process. > > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> > --- > arch/mips/kernel/traps.c | 32 +++++++++++++++++++++++--------- > 1 file changed, 23 insertions(+), 9 deletions(-) > > diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c > index ea59d321f713e..651c9ec6265a9 100644 > --- a/arch/mips/kernel/traps.c > +++ b/arch/mips/kernel/traps.c > @@ -74,7 +74,6 @@ > > #include "access-helper.h" > > -#define MAX(a, b) ((a) >= (b) ? (a) : (b)) > > extern void check_wait(void); > extern asmlinkage void rollback_handle_int(void); > @@ -2005,6 +2004,7 @@ void __noreturn nmi_exception_handler(struct pt_regs *regs) > unsigned long ebase; > EXPORT_SYMBOL_GPL(ebase); > unsigned long exception_handlers[32]; > +static unsigned long vi_vecbase; > unsigned long vi_handlers[64]; > > void reserve_exception_space(phys_addr_t addr, unsigned long size) > @@ -2074,7 +2074,7 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) > handler = (unsigned long) addr; > vi_handlers[n] = handler; > > - b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); > + b = (unsigned char *)(vi_vecbase + n*VECTORSPACING); Add spaces around * for consistency please. [...] > @@ -2370,20 +2370,33 @@ void __init trap_init(void) > extern char except_vec3_generic; > extern char except_vec4; > extern char except_vec3_r4000; > - unsigned long i, vec_size; > + unsigned long i, vec_size, vi_vec_offset; > phys_addr_t ebase_pa; > > check_wait(); > > + if (cpu_has_veic || cpu_has_vint) { > + switch (current_cpu_type()) { > + case CPU_BMIPS3300: > + case CPU_BMIPS4380: > + vi_vec_offset = 0x400; > + break; > + case CPU_BMIPS5000: > + vi_vec_offset = 0x1000; > + break; > + default: > + vi_vec_offset = 0x200; > + break; > + } > + vec_size = vi_vec_offset + VECTORSPACING*64; Here as well... [...] MBR, Sergey
On 12/8/23 7:12 PM, Gregory CLEMENT wrote: > From: Jiaxun Yang <jiaxun.yang@flygoat.com> > > ebase may be in XKPHYS if memblock unable to allocate memory Is unable... > within KSEG0 physical range. > > To map ebase into uncached space we just convert it back to > physical address and then use platform's TO_UNCAC helper > to create mapping. > > Co-developed-by: Vladimir Kondratiev <vladimir.kondratiev@intel.com> > Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@intel.com> > Co-developed-by: Gregory CLEMENT <gregory.clement@bootlin.com> > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> > Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Hm, too many decelopers for such simple patch... :-) [...] MBR, Sergey
On 12/8/23 7:12 PM, Gregory CLEMENT wrote: > From: Jiaxun Yang <jiaxun.yang@flygoat.com> > > ebase may be in XKPHYS if memblock unable to allocate memory Is unable... > within KSEG0 physical range. > > To map ebase into uncached space we just convert it back to > physical address and then use platform's TO_UNCAC helper > to create mapping. > > Co-developed-by: Vladimir Kondratiev <vladimir.kondratiev@intel.com> > Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@intel.com> > Co-developed-by: Gregory CLEMENT <gregory.clement@bootlin.com> > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> > Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Hm, too many developers for such simple patch... :-) [...] MBR, Sergey
On 12/8/23 7:12 PM, Gregory CLEMENT wrote: > KSEGX_SIZE is defined to size of each KSEG segment. To the size? > TO_CAC and TO_UNCAC are defined for 32bits builds and point to KSEG 0 KSEG0. > and KSEG1. > TO_PHYS remains to be 64bits only as we want people to > use __pa to avoid mixup compat address space. Mixing up? > Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> > Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> [...] MBR, Sergey