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([2a01:e0a:999:a3a0:7db3:bdd9:4cab:2ee3]) by smtp.gmail.com with ESMTPSA id n30-20020a05600c501e00b00405442edc69sm15396853wmr.14.2023.11.07.02.55.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Nov 2023 02:55:59 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz Subject: [PATCH v3 00/20] riscv: report more ISA extensions through hwprobe Date: Tue, 7 Nov 2023 11:55:36 +0100 Message-ID: <20231107105556.517187-1-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 In order to be able to gather more information about the supported ISA extensions from userspace using the hwprobe syscall, add more ISA extensions report. This series adds the following ISA extensions parsing support: - Zfh[min] - Zvfh[min] - Zihintntl - Zbc - Zvbb - Zvbc - Zvkb - Zvkg - Zvkned - Zvknh[ab] - Zvksed - Zvksh - Zvkn - Zvknc - Zvkng - Zvks - Zvksc - Zvksg - Zvkt - Zfa - Zbkb - Zbkc - Zbkx - Zknd - Zkne - Zknh - Zkr - Zksed - Zksh - Zkt Some of these extensions are actually shorthands for other "sub" extensions. This series includes a patch from Conor/Evan that adds a way to specify such "bundled" extensions. When exposing these bundled extensions to userspace through hwprobe, only the "sub" extensions are exposed. In order to test it, one can use qemu and the small hwprobe utility provided[1]. Run qemu by specifying additional ISA extensions, for instance: $ qemu-system-riscv64 -cpu rv64,v=true,zk=true,zvksh=true,zvkned=true Then, run hwprobe: $ ./hwprobe Base system ISA: - IMA_FD - C - V Supported extensions: - Zba - Zbb - Zbs - Zbc - Zbkb - Zbkc - Zbkx - Zknd - Zkne - Zknh - Zkt - Zvkned - Zvksh - Zihintntl - Zfa Link: https://github.com/clementleger/hwprobe_dump [1] Acked-by: Conor Dooley --- Changes in V3: - Rebased on top of origin/master - Rename bundle_ext to subset_ext since it is used for superset extensions (Zvbb for instance). - Add an invalid id for pure lasso extension - Fix wrong type for check_isa ext, int -> unsigned int - Use bundled extension for ZVBB/ZVNHB - Split ZBC hwprobe support from scalar crypto patch - Fix typos (Evan) - Added a few Rb: from Evan - Change Zfh/Zfhmin to Zfh[min] to be more coherent with other commits - Reword comment about CHECK_ISA_EXT to be more clear Changes in V2: - Fix typo in first commit title (fatorize->factorize) - Add Zfa support - Fix missing uppercase for Zvkt naming in dt-bindings - Add Conor Acked-by on dt-bindings commits - Add scalar crypto support from Conor/Evan. - Use reporting of bunbled extensions for vector crypto Clément Léger (19): riscv: hwprobe: factorize hwprobe ISA extension reporting riscv: hwprobe: export missing Zbc ISA extension riscv: hwprobe: add support for scalar crypto ISA extensions dt-bindings: riscv: add scalar crypto ISA extensions description riscv: add ISA extension parsing for vector crypto riscv: hwprobe: export vector crypto ISA extensions dt-bindings: riscv: add vector crypto ISA extensions description riscv: add ISA extension parsing for Zfh/Zfh[min] riscv: hwprobe: export Zfh[min] ISA extensions dt-bindings: riscv: add Zfh[min] ISA extensions description riscv: add ISA extension parsing for Zihintntl riscv: hwprobe: export Zhintntl ISA extension dt-bindings: riscv: add Zihintntl ISA extension description riscv: add ISA extension parsing for Zvfh[min] riscv: hwprobe: export Zvfh[min] ISA extensions dt-bindings: riscv: add Zvfh[min] ISA extension description riscv: add ISA extension parsing for Zfa riscv: hwprobe: export Zfa ISA extension dt-bindings: riscv: add Zfa ISA extension description Evan Green (1): riscv: add ISA extension parsing for scalar crypto Documentation/arch/riscv/hwprobe.rst | 81 +++++++ .../devicetree/bindings/riscv/extensions.yaml | 210 ++++++++++++++++++ arch/riscv/include/asm/hwcap.h | 36 ++- arch/riscv/include/uapi/asm/hwprobe.h | 26 +++ arch/riscv/kernel/cpufeature.c | 189 ++++++++++++++-- arch/riscv/kernel/sys_riscv.c | 64 ++++-- 6 files changed, 566 insertions(+), 40 deletions(-)