Message ID | 20230912174928.528414-1-apatel@ventanamicro.com |
---|---|
Headers | show |
Series | Linux RISC-V AIA Support | expand |
Anup Patel wrote: > The RISC-V advanced interrupt architecture (AIA) specification > defines a new MSI controller called incoming message signalled > interrupt controller (IMSIC) which manages MSI on per-HART (or > per-CPU) basis. It also supports IPIs as software injected MSIs. > (For more details refer https://github.com/riscv/riscv-aia) > > Let us add an early irqchip driver for RISC-V IMSIC which sets > up the IMSIC state and provide IPIs. > > Signed-off-by: Anup Patel <apatel@ventanamicro.com> > --- > drivers/irqchip/Kconfig | 7 +- > drivers/irqchip/Makefile | 1 + > drivers/irqchip/irq-riscv-imsic-early.c | 258 ++++++++++++ > drivers/irqchip/irq-riscv-imsic-state.c | 523 ++++++++++++++++++++++++ > drivers/irqchip/irq-riscv-imsic-state.h | 66 +++ > include/linux/irqchip/riscv-imsic.h | 86 ++++ > 6 files changed, 940 insertions(+), 1 deletion(-) > create mode 100644 drivers/irqchip/irq-riscv-imsic-early.c > create mode 100644 drivers/irqchip/irq-riscv-imsic-state.c > create mode 100644 drivers/irqchip/irq-riscv-imsic-state.h > create mode 100644 include/linux/irqchip/riscv-imsic.h > > diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig > index f7149d0f3d45..ee99aacbefcc 100644 > --- a/drivers/irqchip/Kconfig > +++ b/drivers/irqchip/Kconfig > @@ -30,7 +30,6 @@ config ARM_GIC_V2M > > config GIC_NON_BANKED > bool > - Hi Anup, This change looks like a mistake to me. /Emil > config ARM_GIC_V3 > bool > select IRQ_DOMAIN_HIERARCHY > @@ -546,6 +545,12 @@ config SIFIVE_PLIC > select IRQ_DOMAIN_HIERARCHY > select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP > > +config RISCV_IMSIC > + bool > + depends on RISCV > + select IRQ_DOMAIN_HIERARCHY > + select GENERIC_MSI_IRQ > + > config EXYNOS_IRQ_COMBINER > bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST > depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST > diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile > index ffd945fe71aa..d714724387ce 100644 > --- a/drivers/irqchip/Makefile > +++ b/drivers/irqchip/Makefile > @@ -95,6 +95,7 @@ obj-$(CONFIG_QCOM_MPM) += irq-qcom-mpm.o > obj-$(CONFIG_CSKY_MPINTC) += irq-csky-mpintc.o > obj-$(CONFIG_CSKY_APB_INTC) += irq-csky-apb-intc.o > obj-$(CONFIG_RISCV_INTC) += irq-riscv-intc.o > +obj-$(CONFIG_RISCV_IMSIC) += irq-riscv-imsic-state.o irq-riscv-imsic-early.o > obj-$(CONFIG_SIFIVE_PLIC) += irq-sifive-plic.o > obj-$(CONFIG_IMX_IRQSTEER) += irq-imx-irqsteer.o > obj-$(CONFIG_IMX_INTMUX) += irq-imx-intmux.o > diff --git a/drivers/irqchip/irq-riscv-imsic-early.c b/drivers/irqchip/irq-riscv-imsic-early.c > new file mode 100644 > index 000000000000..1de89ce1ec2f > --- /dev/null > +++ b/drivers/irqchip/irq-riscv-imsic-early.c > @@ -0,0 +1,258 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2021 Western Digital Corporation or its affiliates. > + * Copyright (C) 2022 Ventana Micro Systems Inc. > + */ > + > +#define pr_fmt(fmt) "riscv-imsic: " fmt > +#include <linux/cpu.h> > +#include <linux/interrupt.h> > +#include <linux/io.h> > +#include <linux/irq.h> > +#include <linux/irqchip.h> > +#include <linux/irqchip/chained_irq.h> > +#include <linux/module.h> > +#include <linux/spinlock.h> > +#include <linux/smp.h> > + > +#include "irq-riscv-imsic-state.h" > + > +/* > + * The IMSIC driver uses 1 IPI for ID synchronization and > + * arch/riscv/kernel/smp.c require 6 IPIs so we fix the > + * total number of IPIs to 8. > + */ > +#define IMSIC_NR_IPI 8 > + > +static int imsic_parent_irq; > + > +#ifdef CONFIG_SMP > +static irqreturn_t imsic_ids_sync_handler(int irq, void *data) > +{ > + imsic_ids_local_sync(); > + return IRQ_HANDLED; > +} > + > +void imsic_ids_remote_sync(void) > +{ > + struct cpumask amask; > + > + /* > + * We simply inject ID synchronization IPI to all target CPUs > + * except current CPU. The ipi_send_mask() implementation of > + * IPI mux will inject ID synchronization IPI only for CPUs > + * that have enabled it so offline CPUs won't receive IPI. > + * An offline CPU will unconditionally synchronize IDs through > + * imsic_starting_cpu() when the CPU is brought up. > + */ > + cpumask_andnot(&amask, cpu_online_mask, cpumask_of(smp_processor_id())); > + __ipi_send_mask(imsic->ipi_lsync_desc, &amask); > +} > + > +static void imsic_ipi_send(unsigned int cpu) > +{ > + struct imsic_local_config *local = > + per_cpu_ptr(imsic->global.local, cpu); > + > + writel(imsic->ipi_id, local->msi_va); > +} > + > +static void imsic_ipi_starting_cpu(void) > +{ > + /* Enable IPIs for current CPU. */ > + __imsic_id_enable(imsic->ipi_id); > + > + /* Enable virtual IPI used for IMSIC ID synchronization */ > + enable_percpu_irq(imsic->ipi_virq, 0); > +} > + > +static void imsic_ipi_dying_cpu(void) > +{ > + /* > + * Disable virtual IPI used for IMSIC ID synchronization so > + * that we don't receive ID synchronization requests. > + */ > + disable_percpu_irq(imsic->ipi_virq); > +} > + > +static int __init imsic_ipi_domain_init(void) > +{ > + int virq; > + > + /* Allocate interrupt identity for IPIs */ > + virq = imsic_ids_alloc(get_count_order(1)); > + if (virq < 0) > + return virq; > + imsic->ipi_id = virq; > + > + /* Create IMSIC IPI multiplexing */ > + virq = ipi_mux_create(IMSIC_NR_IPI, imsic_ipi_send); > + if (virq <= 0) { > + imsic_ids_free(imsic->ipi_id, get_count_order(1)); > + return (virq < 0) ? virq : -ENOMEM; > + } > + imsic->ipi_virq = virq; > + > + /* First vIRQ is used for IMSIC ID synchronization */ > + virq = request_percpu_irq(imsic->ipi_virq, imsic_ids_sync_handler, > + "riscv-imsic-lsync", imsic->global.local); > + if (virq) { > + imsic_ids_free(imsic->ipi_id, get_count_order(1)); > + return virq; > + } > + irq_set_status_flags(imsic->ipi_virq, IRQ_HIDDEN); > + imsic->ipi_lsync_desc = irq_to_desc(imsic->ipi_virq); > + > + /* Set vIRQ range */ > + riscv_ipi_set_virq_range(imsic->ipi_virq + 1, IMSIC_NR_IPI - 1, true); > + > + /* Announce that IMSIC is providing IPIs */ > + pr_info("%pfwP: providing IPIs using interrupt %d\n", > + imsic->fwnode, imsic->ipi_id); > + > + return 0; > +} > +#else > +static void imsic_ipi_starting_cpu(void) > +{ > +} > + > +static void imsic_ipi_dying_cpu(void) > +{ > +} > + > +static int __init imsic_ipi_domain_init(void) > +{ > + /* Clear the IPI id because we are not using IPIs */ > + imsic->ipi_id = 0; > + return 0; > +} > +#endif > + > +/* > + * To handle an interrupt, we read the TOPEI CSR and write zero in one > + * instruction. If TOPEI CSR is non-zero then we translate TOPEI.ID to > + * Linux interrupt number and let Linux IRQ subsystem handle it. > + */ > +static void imsic_handle_irq(struct irq_desc *desc) > +{ > + struct irq_chip *chip = irq_desc_get_chip(desc); > + irq_hw_number_t hwirq; > + int err; > + > + chained_irq_enter(chip, desc); > + > + while ((hwirq = csr_swap(CSR_TOPEI, 0))) { > + hwirq = hwirq >> TOPEI_ID_SHIFT; > + > + if (hwirq == imsic->ipi_id) { > +#ifdef CONFIG_SMP > + ipi_mux_process(); > +#endif > + continue; > + } > + > + if (unlikely(!imsic->base_domain)) > + continue; > + > + err = generic_handle_domain_irq(imsic->base_domain, hwirq); > + if (unlikely(err)) > + pr_warn_ratelimited( > + "hwirq %lu mapping not found\n", hwirq); > + } > + > + chained_irq_exit(chip, desc); > +} > + > +static int imsic_starting_cpu(unsigned int cpu) > +{ > + /* Enable per-CPU parent interrupt */ > + enable_percpu_irq(imsic_parent_irq, > + irq_get_trigger_type(imsic_parent_irq)); > + > + /* Setup IPIs */ > + imsic_ipi_starting_cpu(); > + > + /* > + * Interrupts identities might have been enabled/disabled while > + * this CPU was not running so sync-up local enable/disable state. > + */ > + imsic_ids_local_sync(); > + > + /* Enable local interrupt delivery */ > + imsic_ids_local_delivery(true); > + > + return 0; > +} > + > +static int imsic_dying_cpu(unsigned int cpu) > +{ > + /* Cleanup IPIs */ > + imsic_ipi_dying_cpu(); > + > + return 0; > +} > + > +static int __init imsic_early_probe(struct fwnode_handle *fwnode) > +{ > + int rc; > + struct irq_domain *domain; > + > + /* Setup IMSIC state */ > + rc = imsic_setup_state(fwnode); > + if (rc) { > + pr_err("%pfwP: failed to setup state (error %d)\n", > + fwnode, rc); > + return rc; > + } > + > + /* Find parent domain and register chained handler */ > + domain = irq_find_matching_fwnode(riscv_get_intc_hwnode(), > + DOMAIN_BUS_ANY); > + if (!domain) { > + pr_err("%pfwP: Failed to find INTC domain\n", fwnode); > + return -ENOENT; > + } > + imsic_parent_irq = irq_create_mapping(domain, RV_IRQ_EXT); > + if (!imsic_parent_irq) { > + pr_err("%pfwP: Failed to create INTC mapping\n", fwnode); > + return -ENOENT; > + } > + irq_set_chained_handler(imsic_parent_irq, imsic_handle_irq); > + > + /* Initialize IPI domain */ > + rc = imsic_ipi_domain_init(); > + if (rc) { > + pr_err("%pfwP: Failed to initialize IPI domain\n", fwnode); > + return rc; > + } > + > + /* > + * Setup cpuhp state (must be done after setting imsic_parent_irq) > + * > + * Don't disable per-CPU IMSIC file when CPU goes offline > + * because this affects IPI and the masking/unmasking of > + * virtual IPIs is done via generic IPI-Mux > + */ > + cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, > + "irqchip/riscv/imsic:starting", > + imsic_starting_cpu, imsic_dying_cpu); > + > + return 0; > +} > + > +static int __init imsic_early_dt_init(struct device_node *node, > + struct device_node *parent) > +{ > + int rc; > + > + /* Do early setup of IMSIC state and IPIs */ > + rc = imsic_early_probe(&node->fwnode); > + if (rc) > + return rc; > + > + /* Ensure that OF platform device gets probed */ > + of_node_clear_flag(node, OF_POPULATED); > + return 0; > +} > +IRQCHIP_DECLARE(riscv_imsic, "riscv,imsics", imsic_early_dt_init); > diff --git a/drivers/irqchip/irq-riscv-imsic-state.c b/drivers/irqchip/irq-riscv-imsic-state.c > new file mode 100644 > index 000000000000..412b5b919dcc > --- /dev/null > +++ b/drivers/irqchip/irq-riscv-imsic-state.c > @@ -0,0 +1,523 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2021 Western Digital Corporation or its affiliates. > + * Copyright (C) 2022 Ventana Micro Systems Inc. > + */ > + > +#define pr_fmt(fmt) "riscv-imsic: " fmt > +#include <linux/bitmap.h> > +#include <linux/module.h> > +#include <linux/of_address.h> > +#include <linux/spinlock.h> > +#include <linux/smp.h> > +#include <asm/hwcap.h> > + > +#include "irq-riscv-imsic-state.h" > + > +#define IMSIC_DISABLE_EIDELIVERY 0 > +#define IMSIC_ENABLE_EIDELIVERY 1 > +#define IMSIC_DISABLE_EITHRESHOLD 1 > +#define IMSIC_ENABLE_EITHRESHOLD 0 > + > +#define imsic_csr_write(__c, __v) \ > +do { \ > + csr_write(CSR_ISELECT, __c); \ > + csr_write(CSR_IREG, __v); \ > +} while (0) > + > +#define imsic_csr_read(__c) \ > +({ \ > + unsigned long __v; \ > + csr_write(CSR_ISELECT, __c); \ > + __v = csr_read(CSR_IREG); \ > + __v; \ > +}) > + > +#define imsic_csr_set(__c, __v) \ > +do { \ > + csr_write(CSR_ISELECT, __c); \ > + csr_set(CSR_IREG, __v); \ > +} while (0) > + > +#define imsic_csr_clear(__c, __v) \ > +do { \ > + csr_write(CSR_ISELECT, __c); \ > + csr_clear(CSR_IREG, __v); \ > +} while (0) > + > +struct imsic_priv *imsic; > + > +const struct imsic_global_config *imsic_get_global_config(void) > +{ > + return (imsic) ? &imsic->global : NULL; > +} > +EXPORT_SYMBOL_GPL(imsic_get_global_config); > + > +void __imsic_eix_update(unsigned long base_id, > + unsigned long num_id, bool pend, bool val) > +{ > + unsigned long i, isel, ireg; > + unsigned long id = base_id, last_id = base_id + num_id; > + > + while (id < last_id) { > + isel = id / BITS_PER_LONG; > + isel *= BITS_PER_LONG / IMSIC_EIPx_BITS; > + isel += (pend) ? IMSIC_EIP0 : IMSIC_EIE0; > + > + ireg = 0; > + for (i = id & (__riscv_xlen - 1); > + (id < last_id) && (i < __riscv_xlen); i++) { > + ireg |= BIT(i); > + id++; > + } > + > + /* > + * The IMSIC EIEx and EIPx registers are indirectly > + * accessed via using ISELECT and IREG CSRs so we > + * need to access these CSRs without getting preempted. > + * > + * All existing users of this function call this > + * function with local IRQs disabled so we don't > + * need to do anything special here. > + */ > + if (val) > + imsic_csr_set(isel, ireg); > + else > + imsic_csr_clear(isel, ireg); > + } > +} > + > +void imsic_id_set_target(unsigned int id, unsigned int target_cpu) > +{ > + unsigned long flags; > + > + raw_spin_lock_irqsave(&imsic->ids_lock, flags); > + imsic->ids_target_cpu[id] = target_cpu; > + raw_spin_unlock_irqrestore(&imsic->ids_lock, flags); > +} > + > +unsigned int imsic_id_get_target(unsigned int id) > +{ > + unsigned int ret; > + unsigned long flags; > + > + raw_spin_lock_irqsave(&imsic->ids_lock, flags); > + ret = imsic->ids_target_cpu[id]; > + raw_spin_unlock_irqrestore(&imsic->ids_lock, flags); > + > + return ret; > +} > + > +void imsic_ids_local_sync(void) > +{ > + int i; > + unsigned long flags; > + > + raw_spin_lock_irqsave(&imsic->ids_lock, flags); > + for (i = 1; i <= imsic->global.nr_ids; i++) { > + if (imsic->ipi_id == i) > + continue; > + > + if (test_bit(i, imsic->ids_enabled_bimap)) > + __imsic_id_enable(i); > + else > + __imsic_id_disable(i); > + } > + raw_spin_unlock_irqrestore(&imsic->ids_lock, flags); > +} > + > +void imsic_ids_local_delivery(bool enable) > +{ > + if (enable) { > + imsic_csr_write(IMSIC_EITHRESHOLD, IMSIC_ENABLE_EITHRESHOLD); > + imsic_csr_write(IMSIC_EIDELIVERY, IMSIC_ENABLE_EIDELIVERY); > + } else { > + imsic_csr_write(IMSIC_EIDELIVERY, IMSIC_DISABLE_EIDELIVERY); > + imsic_csr_write(IMSIC_EITHRESHOLD, IMSIC_DISABLE_EITHRESHOLD); > + } > +} > + > +int imsic_ids_alloc(unsigned int order) > +{ > + int ret; > + unsigned long flags; > + > + raw_spin_lock_irqsave(&imsic->ids_lock, flags); > + ret = bitmap_find_free_region(imsic->ids_used_bimap, > + imsic->global.nr_ids + 1, order); > + raw_spin_unlock_irqrestore(&imsic->ids_lock, flags); > + > + return ret; > +} > + > +void imsic_ids_free(unsigned int base_id, unsigned int order) > +{ > + unsigned long flags; > + > + raw_spin_lock_irqsave(&imsic->ids_lock, flags); > + bitmap_release_region(imsic->ids_used_bimap, base_id, order); > + raw_spin_unlock_irqrestore(&imsic->ids_lock, flags); > +} > + > +static int __init imsic_ids_init(void) > +{ > + int i; > + struct imsic_global_config *global = &imsic->global; > + > + raw_spin_lock_init(&imsic->ids_lock); > + > + /* Allocate used bitmap */ > + imsic->ids_used_bimap = bitmap_zalloc(global->nr_ids + 1, GFP_KERNEL); > + if (!imsic->ids_used_bimap) > + return -ENOMEM; > + > + /* Allocate enabled bitmap */ > + imsic->ids_enabled_bimap = bitmap_zalloc(global->nr_ids + 1, > + GFP_KERNEL); > + if (!imsic->ids_enabled_bimap) { > + kfree(imsic->ids_used_bimap); > + return -ENOMEM; > + } > + > + /* Allocate target CPU array */ > + imsic->ids_target_cpu = kcalloc(global->nr_ids + 1, > + sizeof(unsigned int), GFP_KERNEL); > + if (!imsic->ids_target_cpu) { > + bitmap_free(imsic->ids_enabled_bimap); > + bitmap_free(imsic->ids_used_bimap); > + return -ENOMEM; > + } > + for (i = 0; i <= global->nr_ids; i++) > + imsic->ids_target_cpu[i] = UINT_MAX; > + > + /* Reserve ID#0 because it is special and never implemented */ > + bitmap_set(imsic->ids_used_bimap, 0, 1); > + > + return 0; > +} > + > +static void __init imsic_ids_cleanup(void) > +{ > + kfree(imsic->ids_target_cpu); > + bitmap_free(imsic->ids_enabled_bimap); > + bitmap_free(imsic->ids_used_bimap); > +} > + > +static int __init imsic_get_parent_hartid(struct fwnode_handle *fwnode, > + u32 index, unsigned long *hartid) > +{ > + int rc; > + struct fwnode_reference_args parent; > + > + rc = fwnode_property_get_reference_args(fwnode, > + "interrupts-extended", "#interrupt-cells", > + 0, index, &parent); > + if (rc) > + return rc; > + > + /* > + * Skip interrupts other than external interrupts for > + * current privilege level. > + */ > + if (parent.args[0] != RV_IRQ_EXT) > + return -EINVAL; > + > + return riscv_get_intc_hartid(parent.fwnode, hartid); > +} > + > +static int __init imsic_get_mmio_resource(struct fwnode_handle *fwnode, > + u32 index, struct resource *res) > +{ > + /* > + * Currently, only OF fwnode is support so extend this function > + * for other types of fwnode for ACPI support. > + */ > + if (!is_of_node(fwnode)) > + return -EINVAL; > + return of_address_to_resource(to_of_node(fwnode), index, res); > +} > + > +int __init imsic_setup_state(struct fwnode_handle *fwnode) > +{ > + int rc, cpu; > + phys_addr_t base_addr; > + void __iomem **mmios_va = NULL; > + struct resource res, *mmios = NULL; > + struct imsic_local_config *local; > + struct imsic_global_config *global; > + unsigned long reloff, hartid; > + u32 i, j, index, nr_parent_irqs, nr_handlers = 0, num_mmios = 0; > + > + /* > + * Only one IMSIC instance allowed in a platform for clean > + * implementation of SMP IRQ affinity and per-CPU IPIs. > + * > + * This means on a multi-socket (or multi-die) platform we > + * will have multiple MMIO regions for one IMSIC instance. > + */ > + if (imsic) { > + pr_err("%pfwP: already initialized hence ignoring\n", > + fwnode); > + return -EALREADY; > + } > + > + if (!riscv_isa_extension_available(NULL, SxAIA)) { > + pr_err("%pfwP: AIA support not available\n", fwnode); > + return -ENODEV; > + } > + > + imsic = kzalloc(sizeof(*imsic), GFP_KERNEL); > + if (!imsic) > + return -ENOMEM; > + imsic->fwnode = fwnode; > + global = &imsic->global; > + > + global->local = alloc_percpu(typeof(*(global->local))); > + if (!global->local) { > + rc = -ENOMEM; > + goto out_free_priv; > + } > + > + /* Find number of parent interrupts */ > + nr_parent_irqs = 0; > + while (!imsic_get_parent_hartid(fwnode, nr_parent_irqs, &hartid)) > + nr_parent_irqs++; > + if (!nr_parent_irqs) { > + pr_err("%pfwP: no parent irqs available\n", fwnode); > + rc = -EINVAL; > + goto out_free_local; > + } > + > + /* Find number of guest index bits in MSI address */ > + rc = fwnode_property_read_u32_array(fwnode, "riscv,guest-index-bits", > + &global->guest_index_bits, 1); > + if (rc) > + global->guest_index_bits = 0; > + i = BITS_PER_LONG - IMSIC_MMIO_PAGE_SHIFT; > + if (i < global->guest_index_bits) { > + pr_err("%pfwP: guest index bits too big\n", fwnode); > + rc = -EINVAL; > + goto out_free_local; > + } > + > + /* Find number of HART index bits */ > + rc = fwnode_property_read_u32_array(fwnode, "riscv,hart-index-bits", > + &global->hart_index_bits, 1); > + if (rc) { > + /* Assume default value */ > + global->hart_index_bits = __fls(nr_parent_irqs); > + if (BIT(global->hart_index_bits) < nr_parent_irqs) > + global->hart_index_bits++; > + } > + i = BITS_PER_LONG - IMSIC_MMIO_PAGE_SHIFT - global->guest_index_bits; > + if (i < global->hart_index_bits) { > + pr_err("%pfwP: HART index bits too big\n", fwnode); > + rc = -EINVAL; > + goto out_free_local; > + } > + > + /* Find number of group index bits */ > + rc = fwnode_property_read_u32_array(fwnode, "riscv,group-index-bits", > + &global->group_index_bits, 1); > + if (rc) > + global->group_index_bits = 0; > + i = BITS_PER_LONG - IMSIC_MMIO_PAGE_SHIFT - > + global->guest_index_bits - global->hart_index_bits; > + if (i < global->group_index_bits) { > + pr_err("%pfwP: group index bits too big\n", fwnode); > + rc = -EINVAL; > + goto out_free_local; > + } > + > + /* > + * Find first bit position of group index. > + * If not specified assumed the default APLIC-IMSIC configuration. > + */ > + rc = fwnode_property_read_u32_array(fwnode, "riscv,group-index-shift", > + &global->group_index_shift, 1); > + if (rc) > + global->group_index_shift = IMSIC_MMIO_PAGE_SHIFT * 2; > + i = global->group_index_bits + global->group_index_shift - 1; > + if (i >= BITS_PER_LONG) { > + pr_err("%pfwP: group index shift too big\n", fwnode); > + rc = -EINVAL; > + goto out_free_local; > + } > + > + /* Find number of interrupt identities */ > + rc = fwnode_property_read_u32_array(fwnode, "riscv,num-ids", > + &global->nr_ids, 1); > + if (rc) { > + pr_err("%pfwP: number of interrupt identities not found\n", > + fwnode); > + goto out_free_local; > + } > + if ((global->nr_ids < IMSIC_MIN_ID) || > + (global->nr_ids >= IMSIC_MAX_ID) || > + ((global->nr_ids & IMSIC_MIN_ID) != IMSIC_MIN_ID)) { > + pr_err("%pfwP: invalid number of interrupt identities\n", > + fwnode); > + rc = -EINVAL; > + goto out_free_local; > + } > + > + /* Find number of guest interrupt identities */ > + if (fwnode_property_read_u32_array(fwnode, "riscv,num-guest-ids", > + &global->nr_guest_ids, 1)) > + global->nr_guest_ids = global->nr_ids; > + if ((global->nr_guest_ids < IMSIC_MIN_ID) || > + (global->nr_guest_ids >= IMSIC_MAX_ID) || > + ((global->nr_guest_ids & IMSIC_MIN_ID) != IMSIC_MIN_ID)) { > + pr_err("%pfwP: invalid number of guest interrupt identities\n", > + fwnode); > + rc = -EINVAL; > + goto out_free_local; > + } > + > + /* Compute base address */ > + rc = imsic_get_mmio_resource(fwnode, 0, &res); > + if (rc) { > + pr_err("%pfwP: first MMIO resource not found\n", fwnode); > + rc = -EINVAL; > + goto out_free_local; > + } > + global->base_addr = res.start; > + global->base_addr &= ~(BIT(global->guest_index_bits + > + global->hart_index_bits + > + IMSIC_MMIO_PAGE_SHIFT) - 1); > + global->base_addr &= ~((BIT(global->group_index_bits) - 1) << > + global->group_index_shift); > + > + /* Find number of MMIO register sets */ > + while (!imsic_get_mmio_resource(fwnode, num_mmios, &res)) > + num_mmios++; > + > + /* Allocate MMIO resource array */ > + mmios = kcalloc(num_mmios, sizeof(*mmios), GFP_KERNEL); > + if (!mmios) { > + rc = -ENOMEM; > + goto out_free_local; > + } > + > + /* Allocate MMIO virtual address array */ > + mmios_va = kcalloc(num_mmios, sizeof(*mmios_va), GFP_KERNEL); > + if (!mmios_va) { > + rc = -ENOMEM; > + goto out_iounmap; > + } > + > + /* Parse and map MMIO register sets */ > + for (i = 0; i < num_mmios; i++) { > + rc = imsic_get_mmio_resource(fwnode, i, &mmios[i]); > + if (rc) { > + pr_err("%pfwP: unable to parse MMIO regset %d\n", > + fwnode, i); > + goto out_iounmap; > + } > + > + base_addr = mmios[i].start; > + base_addr &= ~(BIT(global->guest_index_bits + > + global->hart_index_bits + > + IMSIC_MMIO_PAGE_SHIFT) - 1); > + base_addr &= ~((BIT(global->group_index_bits) - 1) << > + global->group_index_shift); > + if (base_addr != global->base_addr) { > + rc = -EINVAL; > + pr_err("%pfwP: address mismatch for regset %d\n", > + fwnode, i); > + goto out_iounmap; > + } > + > + mmios_va[i] = ioremap(mmios[i].start, resource_size(&mmios[i])); > + if (!mmios_va[i]) { > + rc = -EIO; > + pr_err("%pfwP: unable to map MMIO regset %d\n", > + fwnode, i); > + goto out_iounmap; > + } > + } > + > + /* Initialize interrupt identity management */ > + rc = imsic_ids_init(); > + if (rc) { > + pr_err("%pfwP: failed to initialize interrupt management\n", > + fwnode); > + goto out_iounmap; > + } > + > + /* Configure handlers for target CPUs */ > + for (i = 0; i < nr_parent_irqs; i++) { > + rc = imsic_get_parent_hartid(fwnode, i, &hartid); > + if (rc) { > + pr_warn("%pfwP: hart ID for parent irq%d not found\n", > + fwnode, i); > + continue; > + } > + > + cpu = riscv_hartid_to_cpuid(hartid); > + if (cpu < 0) { > + pr_warn("%pfwP: invalid cpuid for parent irq%d\n", > + fwnode, i); > + continue; > + } > + > + /* Find MMIO location of MSI page */ > + index = num_mmios; > + reloff = i * BIT(global->guest_index_bits) * > + IMSIC_MMIO_PAGE_SZ; > + for (j = 0; num_mmios; j++) { > + if (reloff < resource_size(&mmios[j])) { > + index = j; > + break; > + } > + > + /* > + * MMIO region size may not be aligned to > + * BIT(global->guest_index_bits) * IMSIC_MMIO_PAGE_SZ > + * if holes are present. > + */ > + reloff -= ALIGN(resource_size(&mmios[j]), > + BIT(global->guest_index_bits) * IMSIC_MMIO_PAGE_SZ); > + } > + if (index >= num_mmios) { > + pr_warn("%pfwP: MMIO not found for parent irq%d\n", > + fwnode, i); > + continue; > + } > + > + local = per_cpu_ptr(global->local, cpu); > + local->msi_pa = mmios[index].start + reloff; > + local->msi_va = mmios_va[index] + reloff; > + > + nr_handlers++; > + } > + > + /* If no CPU handlers found then can't take interrupts */ > + if (!nr_handlers) { > + pr_err("%pfwP: No CPU handlers found\n", fwnode); > + rc = -ENODEV; > + goto out_ids_cleanup; > + } > + > + /* We don't need MMIO arrays anymore so let's free-up */ > + kfree(mmios_va); > + kfree(mmios); > + > + return 0; > + > +out_ids_cleanup: > + imsic_ids_cleanup(); > +out_iounmap: > + for (i = 0; i < num_mmios; i++) { > + if (mmios_va[i]) > + iounmap(mmios_va[i]); > + } > + kfree(mmios_va); > + kfree(mmios); > +out_free_local: > + free_percpu(imsic->global.local); > +out_free_priv: > + kfree(imsic); > + imsic = NULL; > + return rc; > +} > diff --git a/drivers/irqchip/irq-riscv-imsic-state.h b/drivers/irqchip/irq-riscv-imsic-state.h > new file mode 100644 > index 000000000000..3170018949a8 > --- /dev/null > +++ b/drivers/irqchip/irq-riscv-imsic-state.h > @@ -0,0 +1,66 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (C) 2021 Western Digital Corporation or its affiliates. > + * Copyright (C) 2022 Ventana Micro Systems Inc. > + */ > + > +#ifndef _IRQ_RISCV_IMSIC_STATE_H > +#define _IRQ_RISCV_IMSIC_STATE_H > + > +#include <linux/irqchip/riscv-imsic.h> > +#include <linux/irqdomain.h> > +#include <linux/fwnode.h> > + > +struct imsic_priv { > + /* Device details */ > + struct fwnode_handle *fwnode; > + > + /* Global configuration common for all HARTs */ > + struct imsic_global_config global; > + > + /* Global state of interrupt identities */ > + raw_spinlock_t ids_lock; > + unsigned long *ids_used_bimap; > + unsigned long *ids_enabled_bimap; > + unsigned int *ids_target_cpu; > + > + /* IPI interrupt identity and synchronization */ > + u32 ipi_id; > + int ipi_virq; > + struct irq_desc *ipi_lsync_desc; > + > + /* IRQ domains (created by platform driver) */ > + struct irq_domain *base_domain; > + struct irq_domain *plat_domain; > +}; > + > +extern struct imsic_priv *imsic; > + > +void __imsic_eix_update(unsigned long base_id, > + unsigned long num_id, bool pend, bool val); > + > +#define __imsic_id_enable(__id) \ > + __imsic_eix_update((__id), 1, false, true) > +#define __imsic_id_disable(__id) \ > + __imsic_eix_update((__id), 1, false, false) > + > +void imsic_id_set_target(unsigned int id, unsigned int target_cpu); > +unsigned int imsic_id_get_target(unsigned int id); > + > +void imsic_ids_local_sync(void); > +void imsic_ids_local_delivery(bool enable); > + > +#ifdef CONFIG_SMP > +void imsic_ids_remote_sync(void); > +#else > +static inline void imsic_ids_remote_sync(void) > +{ > +} > +#endif > + > +int imsic_ids_alloc(unsigned int order); > +void imsic_ids_free(unsigned int base_id, unsigned int order); > + > +int imsic_setup_state(struct fwnode_handle *fwnode); > + > +#endif > diff --git a/include/linux/irqchip/riscv-imsic.h b/include/linux/irqchip/riscv-imsic.h > new file mode 100644 > index 000000000000..1f6fc9a57218 > --- /dev/null > +++ b/include/linux/irqchip/riscv-imsic.h > @@ -0,0 +1,86 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (C) 2021 Western Digital Corporation or its affiliates. > + * Copyright (C) 2022 Ventana Micro Systems Inc. > + */ > +#ifndef __LINUX_IRQCHIP_RISCV_IMSIC_H > +#define __LINUX_IRQCHIP_RISCV_IMSIC_H > + > +#include <linux/types.h> > +#include <asm/csr.h> > + > +#define IMSIC_MMIO_PAGE_SHIFT 12 > +#define IMSIC_MMIO_PAGE_SZ (1UL << IMSIC_MMIO_PAGE_SHIFT) > +#define IMSIC_MMIO_PAGE_LE 0x00 > +#define IMSIC_MMIO_PAGE_BE 0x04 > + > +#define IMSIC_MIN_ID 63 > +#define IMSIC_MAX_ID 2048 > + > +#define IMSIC_EIDELIVERY 0x70 > + > +#define IMSIC_EITHRESHOLD 0x72 > + > +#define IMSIC_EIP0 0x80 > +#define IMSIC_EIP63 0xbf > +#define IMSIC_EIPx_BITS 32 > + > +#define IMSIC_EIE0 0xc0 > +#define IMSIC_EIE63 0xff > +#define IMSIC_EIEx_BITS 32 > + > +#define IMSIC_FIRST IMSIC_EIDELIVERY > +#define IMSIC_LAST IMSIC_EIE63 > + > +#define IMSIC_MMIO_SETIPNUM_LE 0x00 > +#define IMSIC_MMIO_SETIPNUM_BE 0x04 > + > +struct imsic_local_config { > + phys_addr_t msi_pa; > + void __iomem *msi_va; > +}; > + > +struct imsic_global_config { > + /* > + * MSI Target Address Scheme > + * > + * XLEN-1 12 0 > + * | | | > + * ------------------------------------------------------------- > + * |xxxxxx|Group Index|xxxxxxxxxxx|HART Index|Guest Index| 0 | > + * ------------------------------------------------------------- > + */ > + > + /* Bits representing Guest index, HART index, and Group index */ > + u32 guest_index_bits; > + u32 hart_index_bits; > + u32 group_index_bits; > + u32 group_index_shift; > + > + /* Global base address matching all target MSI addresses */ > + phys_addr_t base_addr; > + > + /* Number of interrupt identities */ > + u32 nr_ids; > + > + /* Number of guest interrupt identities */ > + u32 nr_guest_ids; > + > + /* Per-CPU IMSIC addresses */ > + struct imsic_local_config __percpu *local; > +}; > + > +#ifdef CONFIG_RISCV_IMSIC > + > +extern const struct imsic_global_config *imsic_get_global_config(void); > + > +#else > + > +static inline const struct imsic_global_config *imsic_get_global_config(void) > +{ > + return NULL; > +} > + > +#endif > + > +#endif > -- > 2.34.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
On Wed, Sep 13, 2023 at 4:03 PM Emil Renner Berthing <emil.renner.berthing@canonical.com> wrote: > > Anup Patel wrote: > > The RISC-V advanced interrupt architecture (AIA) specification > > defines a new MSI controller called incoming message signalled > > interrupt controller (IMSIC) which manages MSI on per-HART (or > > per-CPU) basis. It also supports IPIs as software injected MSIs. > > (For more details refer https://github.com/riscv/riscv-aia) > > > > Let us add an early irqchip driver for RISC-V IMSIC which sets > > up the IMSIC state and provide IPIs. > > > > Signed-off-by: Anup Patel <apatel@ventanamicro.com> > > --- > > drivers/irqchip/Kconfig | 7 +- > > drivers/irqchip/Makefile | 1 + > > drivers/irqchip/irq-riscv-imsic-early.c | 258 ++++++++++++ > > drivers/irqchip/irq-riscv-imsic-state.c | 523 ++++++++++++++++++++++++ > > drivers/irqchip/irq-riscv-imsic-state.h | 66 +++ > > include/linux/irqchip/riscv-imsic.h | 86 ++++ > > 6 files changed, 940 insertions(+), 1 deletion(-) > > create mode 100644 drivers/irqchip/irq-riscv-imsic-early.c > > create mode 100644 drivers/irqchip/irq-riscv-imsic-state.c > > create mode 100644 drivers/irqchip/irq-riscv-imsic-state.h > > create mode 100644 include/linux/irqchip/riscv-imsic.h > > > > diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig > > index f7149d0f3d45..ee99aacbefcc 100644 > > --- a/drivers/irqchip/Kconfig > > +++ b/drivers/irqchip/Kconfig > > @@ -30,7 +30,6 @@ config ARM_GIC_V2M > > > > config GIC_NON_BANKED > > bool > > - > > Hi Anup, > > This change looks like a mistake to me. Ahh, yes. This change creeped in accidentally. I will remove this change in the next revision. Regards, Anup > > /Emil > > > config ARM_GIC_V3 > > bool > > select IRQ_DOMAIN_HIERARCHY > > @@ -546,6 +545,12 @@ config SIFIVE_PLIC > > select IRQ_DOMAIN_HIERARCHY > > select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP > > > > +config RISCV_IMSIC > > + bool > > + depends on RISCV > > + select IRQ_DOMAIN_HIERARCHY > > + select GENERIC_MSI_IRQ > > + > > config EXYNOS_IRQ_COMBINER > > bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST > > depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST > > diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile > > index ffd945fe71aa..d714724387ce 100644 > > --- a/drivers/irqchip/Makefile > > +++ b/drivers/irqchip/Makefile > > @@ -95,6 +95,7 @@ obj-$(CONFIG_QCOM_MPM) += irq-qcom-mpm.o > > obj-$(CONFIG_CSKY_MPINTC) += irq-csky-mpintc.o > > obj-$(CONFIG_CSKY_APB_INTC) += irq-csky-apb-intc.o > > obj-$(CONFIG_RISCV_INTC) += irq-riscv-intc.o > > +obj-$(CONFIG_RISCV_IMSIC) += irq-riscv-imsic-state.o irq-riscv-imsic-early.o > > obj-$(CONFIG_SIFIVE_PLIC) += irq-sifive-plic.o > > obj-$(CONFIG_IMX_IRQSTEER) += irq-imx-irqsteer.o > > obj-$(CONFIG_IMX_INTMUX) += irq-imx-intmux.o > > diff --git a/drivers/irqchip/irq-riscv-imsic-early.c b/drivers/irqchip/irq-riscv-imsic-early.c > > new file mode 100644 > > index 000000000000..1de89ce1ec2f > > --- /dev/null > > +++ b/drivers/irqchip/irq-riscv-imsic-early.c > > @@ -0,0 +1,258 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Copyright (C) 2021 Western Digital Corporation or its affiliates. > > + * Copyright (C) 2022 Ventana Micro Systems Inc. > > + */ > > + > > +#define pr_fmt(fmt) "riscv-imsic: " fmt > > +#include <linux/cpu.h> > > +#include <linux/interrupt.h> > > +#include <linux/io.h> > > +#include <linux/irq.h> > > +#include <linux/irqchip.h> > > +#include <linux/irqchip/chained_irq.h> > > +#include <linux/module.h> > > +#include <linux/spinlock.h> > > +#include <linux/smp.h> > > + > > +#include "irq-riscv-imsic-state.h" > > + > > +/* > > + * The IMSIC driver uses 1 IPI for ID synchronization and > > + * arch/riscv/kernel/smp.c require 6 IPIs so we fix the > > + * total number of IPIs to 8. > > + */ > > +#define IMSIC_NR_IPI 8 > > + > > +static int imsic_parent_irq; > > + > > +#ifdef CONFIG_SMP > > +static irqreturn_t imsic_ids_sync_handler(int irq, void *data) > > +{ > > + imsic_ids_local_sync(); > > + return IRQ_HANDLED; > > +} > > + > > +void imsic_ids_remote_sync(void) > > +{ > > + struct cpumask amask; > > + > > + /* > > + * We simply inject ID synchronization IPI to all target CPUs > > + * except current CPU. The ipi_send_mask() implementation of > > + * IPI mux will inject ID synchronization IPI only for CPUs > > + * that have enabled it so offline CPUs won't receive IPI. > > + * An offline CPU will unconditionally synchronize IDs through > > + * imsic_starting_cpu() when the CPU is brought up. > > + */ > > + cpumask_andnot(&amask, cpu_online_mask, cpumask_of(smp_processor_id())); > > + __ipi_send_mask(imsic->ipi_lsync_desc, &amask); > > +} > > + > > +static void imsic_ipi_send(unsigned int cpu) > > +{ > > + struct imsic_local_config *local = > > + per_cpu_ptr(imsic->global.local, cpu); > > + > > + writel(imsic->ipi_id, local->msi_va); > > +} > > + > > +static void imsic_ipi_starting_cpu(void) > > +{ > > + /* Enable IPIs for current CPU. */ > > + __imsic_id_enable(imsic->ipi_id); > > + > > + /* Enable virtual IPI used for IMSIC ID synchronization */ > > + enable_percpu_irq(imsic->ipi_virq, 0); > > +} > > + > > +static void imsic_ipi_dying_cpu(void) > > +{ > > + /* > > + * Disable virtual IPI used for IMSIC ID synchronization so > > + * that we don't receive ID synchronization requests. > > + */ > > + disable_percpu_irq(imsic->ipi_virq); > > +} > > + > > +static int __init imsic_ipi_domain_init(void) > > +{ > > + int virq; > > + > > + /* Allocate interrupt identity for IPIs */ > > + virq = imsic_ids_alloc(get_count_order(1)); > > + if (virq < 0) > > + return virq; > > + imsic->ipi_id = virq; > > + > > + /* Create IMSIC IPI multiplexing */ > > + virq = ipi_mux_create(IMSIC_NR_IPI, imsic_ipi_send); > > + if (virq <= 0) { > > + imsic_ids_free(imsic->ipi_id, get_count_order(1)); > > + return (virq < 0) ? virq : -ENOMEM; > > + } > > + imsic->ipi_virq = virq; > > + > > + /* First vIRQ is used for IMSIC ID synchronization */ > > + virq = request_percpu_irq(imsic->ipi_virq, imsic_ids_sync_handler, > > + "riscv-imsic-lsync", imsic->global.local); > > + if (virq) { > > + imsic_ids_free(imsic->ipi_id, get_count_order(1)); > > + return virq; > > + } > > + irq_set_status_flags(imsic->ipi_virq, IRQ_HIDDEN); > > + imsic->ipi_lsync_desc = irq_to_desc(imsic->ipi_virq); > > + > > + /* Set vIRQ range */ > > + riscv_ipi_set_virq_range(imsic->ipi_virq + 1, IMSIC_NR_IPI - 1, true); > > + > > + /* Announce that IMSIC is providing IPIs */ > > + pr_info("%pfwP: providing IPIs using interrupt %d\n", > > + imsic->fwnode, imsic->ipi_id); > > + > > + return 0; > > +} > > +#else > > +static void imsic_ipi_starting_cpu(void) > > +{ > > +} > > + > > +static void imsic_ipi_dying_cpu(void) > > +{ > > +} > > + > > +static int __init imsic_ipi_domain_init(void) > > +{ > > + /* Clear the IPI id because we are not using IPIs */ > > + imsic->ipi_id = 0; > > + return 0; > > +} > > +#endif > > + > > +/* > > + * To handle an interrupt, we read the TOPEI CSR and write zero in one > > + * instruction. If TOPEI CSR is non-zero then we translate TOPEI.ID to > > + * Linux interrupt number and let Linux IRQ subsystem handle it. > > + */ > > +static void imsic_handle_irq(struct irq_desc *desc) > > +{ > > + struct irq_chip *chip = irq_desc_get_chip(desc); > > + irq_hw_number_t hwirq; > > + int err; > > + > > + chained_irq_enter(chip, desc); > > + > > + while ((hwirq = csr_swap(CSR_TOPEI, 0))) { > > + hwirq = hwirq >> TOPEI_ID_SHIFT; > > + > > + if (hwirq == imsic->ipi_id) { > > +#ifdef CONFIG_SMP > > + ipi_mux_process(); > > +#endif > > + continue; > > + } > > + > > + if (unlikely(!imsic->base_domain)) > > + continue; > > + > > + err = generic_handle_domain_irq(imsic->base_domain, hwirq); > > + if (unlikely(err)) > > + pr_warn_ratelimited( > > + "hwirq %lu mapping not found\n", hwirq); > > + } > > + > > + chained_irq_exit(chip, desc); > > +} > > + > > +static int imsic_starting_cpu(unsigned int cpu) > > +{ > > + /* Enable per-CPU parent interrupt */ > > + enable_percpu_irq(imsic_parent_irq, > > + irq_get_trigger_type(imsic_parent_irq)); > > + > > + /* Setup IPIs */ > > + imsic_ipi_starting_cpu(); > > + > > + /* > > + * Interrupts identities might have been enabled/disabled while > > + * this CPU was not running so sync-up local enable/disable state. > > + */ > > + imsic_ids_local_sync(); > > + > > + /* Enable local interrupt delivery */ > > + imsic_ids_local_delivery(true); > > + > > + return 0; > > +} > > + > > +static int imsic_dying_cpu(unsigned int cpu) > > +{ > > + /* Cleanup IPIs */ > > + imsic_ipi_dying_cpu(); > > + > > + return 0; > > +} > > + > > +static int __init imsic_early_probe(struct fwnode_handle *fwnode) > > +{ > > + int rc; > > + struct irq_domain *domain; > > + > > + /* Setup IMSIC state */ > > + rc = imsic_setup_state(fwnode); > > + if (rc) { > > + pr_err("%pfwP: failed to setup state (error %d)\n", > > + fwnode, rc); > > + return rc; > > + } > > + > > + /* Find parent domain and register chained handler */ > > + domain = irq_find_matching_fwnode(riscv_get_intc_hwnode(), > > + DOMAIN_BUS_ANY); > > + if (!domain) { > > + pr_err("%pfwP: Failed to find INTC domain\n", fwnode); > > + return -ENOENT; > > + } > > + imsic_parent_irq = irq_create_mapping(domain, RV_IRQ_EXT); > > + if (!imsic_parent_irq) { > > + pr_err("%pfwP: Failed to create INTC mapping\n", fwnode); > > + return -ENOENT; > > + } > > + irq_set_chained_handler(imsic_parent_irq, imsic_handle_irq); > > + > > + /* Initialize IPI domain */ > > + rc = imsic_ipi_domain_init(); > > + if (rc) { > > + pr_err("%pfwP: Failed to initialize IPI domain\n", fwnode); > > + return rc; > > + } > > + > > + /* > > + * Setup cpuhp state (must be done after setting imsic_parent_irq) > > + * > > + * Don't disable per-CPU IMSIC file when CPU goes offline > > + * because this affects IPI and the masking/unmasking of > > + * virtual IPIs is done via generic IPI-Mux > > + */ > > + cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, > > + "irqchip/riscv/imsic:starting", > > + imsic_starting_cpu, imsic_dying_cpu); > > + > > + return 0; > > +} > > + > > +static int __init imsic_early_dt_init(struct device_node *node, > > + struct device_node *parent) > > +{ > > + int rc; > > + > > + /* Do early setup of IMSIC state and IPIs */ > > + rc = imsic_early_probe(&node->fwnode); > > + if (rc) > > + return rc; > > + > > + /* Ensure that OF platform device gets probed */ > > + of_node_clear_flag(node, OF_POPULATED); > > + return 0; > > +} > > +IRQCHIP_DECLARE(riscv_imsic, "riscv,imsics", imsic_early_dt_init); > > diff --git a/drivers/irqchip/irq-riscv-imsic-state.c b/drivers/irqchip/irq-riscv-imsic-state.c > > new file mode 100644 > > index 000000000000..412b5b919dcc > > --- /dev/null > > +++ b/drivers/irqchip/irq-riscv-imsic-state.c > > @@ -0,0 +1,523 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Copyright (C) 2021 Western Digital Corporation or its affiliates. > > + * Copyright (C) 2022 Ventana Micro Systems Inc. > > + */ > > + > > +#define pr_fmt(fmt) "riscv-imsic: " fmt > > +#include <linux/bitmap.h> > > +#include <linux/module.h> > > +#include <linux/of_address.h> > > +#include <linux/spinlock.h> > > +#include <linux/smp.h> > > +#include <asm/hwcap.h> > > + > > +#include "irq-riscv-imsic-state.h" > > + > > +#define IMSIC_DISABLE_EIDELIVERY 0 > > +#define IMSIC_ENABLE_EIDELIVERY 1 > > +#define IMSIC_DISABLE_EITHRESHOLD 1 > > +#define IMSIC_ENABLE_EITHRESHOLD 0 > > + > > +#define imsic_csr_write(__c, __v) \ > > +do { \ > > + csr_write(CSR_ISELECT, __c); \ > > + csr_write(CSR_IREG, __v); \ > > +} while (0) > > + > > +#define imsic_csr_read(__c) \ > > +({ \ > > + unsigned long __v; \ > > + csr_write(CSR_ISELECT, __c); \ > > + __v = csr_read(CSR_IREG); \ > > + __v; \ > > +}) > > + > > +#define imsic_csr_set(__c, __v) \ > > +do { \ > > + csr_write(CSR_ISELECT, __c); \ > > + csr_set(CSR_IREG, __v); \ > > +} while (0) > > + > > +#define imsic_csr_clear(__c, __v) \ > > +do { \ > > + csr_write(CSR_ISELECT, __c); \ > > + csr_clear(CSR_IREG, __v); \ > > +} while (0) > > + > > +struct imsic_priv *imsic; > > + > > +const struct imsic_global_config *imsic_get_global_config(void) > > +{ > > + return (imsic) ? &imsic->global : NULL; > > +} > > +EXPORT_SYMBOL_GPL(imsic_get_global_config); > > + > > +void __imsic_eix_update(unsigned long base_id, > > + unsigned long num_id, bool pend, bool val) > > +{ > > + unsigned long i, isel, ireg; > > + unsigned long id = base_id, last_id = base_id + num_id; > > + > > + while (id < last_id) { > > + isel = id / BITS_PER_LONG; > > + isel *= BITS_PER_LONG / IMSIC_EIPx_BITS; > > + isel += (pend) ? IMSIC_EIP0 : IMSIC_EIE0; > > + > > + ireg = 0; > > + for (i = id & (__riscv_xlen - 1); > > + (id < last_id) && (i < __riscv_xlen); i++) { > > + ireg |= BIT(i); > > + id++; > > + } > > + > > + /* > > + * The IMSIC EIEx and EIPx registers are indirectly > > + * accessed via using ISELECT and IREG CSRs so we > > + * need to access these CSRs without getting preempted. > > + * > > + * All existing users of this function call this > > + * function with local IRQs disabled so we don't > > + * need to do anything special here. > > + */ > > + if (val) > > + imsic_csr_set(isel, ireg); > > + else > > + imsic_csr_clear(isel, ireg); > > + } > > +} > > + > > +void imsic_id_set_target(unsigned int id, unsigned int target_cpu) > > +{ > > + unsigned long flags; > > + > > + raw_spin_lock_irqsave(&imsic->ids_lock, flags); > > + imsic->ids_target_cpu[id] = target_cpu; > > + raw_spin_unlock_irqrestore(&imsic->ids_lock, flags); > > +} > > + > > +unsigned int imsic_id_get_target(unsigned int id) > > +{ > > + unsigned int ret; > > + unsigned long flags; > > + > > + raw_spin_lock_irqsave(&imsic->ids_lock, flags); > > + ret = imsic->ids_target_cpu[id]; > > + raw_spin_unlock_irqrestore(&imsic->ids_lock, flags); > > + > > + return ret; > > +} > > + > > +void imsic_ids_local_sync(void) > > +{ > > + int i; > > + unsigned long flags; > > + > > + raw_spin_lock_irqsave(&imsic->ids_lock, flags); > > + for (i = 1; i <= imsic->global.nr_ids; i++) { > > + if (imsic->ipi_id == i) > > + continue; > > + > > + if (test_bit(i, imsic->ids_enabled_bimap)) > > + __imsic_id_enable(i); > > + else > > + __imsic_id_disable(i); > > + } > > + raw_spin_unlock_irqrestore(&imsic->ids_lock, flags); > > +} > > + > > +void imsic_ids_local_delivery(bool enable) > > +{ > > + if (enable) { > > + imsic_csr_write(IMSIC_EITHRESHOLD, IMSIC_ENABLE_EITHRESHOLD); > > + imsic_csr_write(IMSIC_EIDELIVERY, IMSIC_ENABLE_EIDELIVERY); > > + } else { > > + imsic_csr_write(IMSIC_EIDELIVERY, IMSIC_DISABLE_EIDELIVERY); > > + imsic_csr_write(IMSIC_EITHRESHOLD, IMSIC_DISABLE_EITHRESHOLD); > > + } > > +} > > + > > +int imsic_ids_alloc(unsigned int order) > > +{ > > + int ret; > > + unsigned long flags; > > + > > + raw_spin_lock_irqsave(&imsic->ids_lock, flags); > > + ret = bitmap_find_free_region(imsic->ids_used_bimap, > > + imsic->global.nr_ids + 1, order); > > + raw_spin_unlock_irqrestore(&imsic->ids_lock, flags); > > + > > + return ret; > > +} > > + > > +void imsic_ids_free(unsigned int base_id, unsigned int order) > > +{ > > + unsigned long flags; > > + > > + raw_spin_lock_irqsave(&imsic->ids_lock, flags); > > + bitmap_release_region(imsic->ids_used_bimap, base_id, order); > > + raw_spin_unlock_irqrestore(&imsic->ids_lock, flags); > > +} > > + > > +static int __init imsic_ids_init(void) > > +{ > > + int i; > > + struct imsic_global_config *global = &imsic->global; > > + > > + raw_spin_lock_init(&imsic->ids_lock); > > + > > + /* Allocate used bitmap */ > > + imsic->ids_used_bimap = bitmap_zalloc(global->nr_ids + 1, GFP_KERNEL); > > + if (!imsic->ids_used_bimap) > > + return -ENOMEM; > > + > > + /* Allocate enabled bitmap */ > > + imsic->ids_enabled_bimap = bitmap_zalloc(global->nr_ids + 1, > > + GFP_KERNEL); > > + if (!imsic->ids_enabled_bimap) { > > + kfree(imsic->ids_used_bimap); > > + return -ENOMEM; > > + } > > + > > + /* Allocate target CPU array */ > > + imsic->ids_target_cpu = kcalloc(global->nr_ids + 1, > > + sizeof(unsigned int), GFP_KERNEL); > > + if (!imsic->ids_target_cpu) { > > + bitmap_free(imsic->ids_enabled_bimap); > > + bitmap_free(imsic->ids_used_bimap); > > + return -ENOMEM; > > + } > > + for (i = 0; i <= global->nr_ids; i++) > > + imsic->ids_target_cpu[i] = UINT_MAX; > > + > > + /* Reserve ID#0 because it is special and never implemented */ > > + bitmap_set(imsic->ids_used_bimap, 0, 1); > > + > > + return 0; > > +} > > + > > +static void __init imsic_ids_cleanup(void) > > +{ > > + kfree(imsic->ids_target_cpu); > > + bitmap_free(imsic->ids_enabled_bimap); > > + bitmap_free(imsic->ids_used_bimap); > > +} > > + > > +static int __init imsic_get_parent_hartid(struct fwnode_handle *fwnode, > > + u32 index, unsigned long *hartid) > > +{ > > + int rc; > > + struct fwnode_reference_args parent; > > + > > + rc = fwnode_property_get_reference_args(fwnode, > > + "interrupts-extended", "#interrupt-cells", > > + 0, index, &parent); > > + if (rc) > > + return rc; > > + > > + /* > > + * Skip interrupts other than external interrupts for > > + * current privilege level. > > + */ > > + if (parent.args[0] != RV_IRQ_EXT) > > + return -EINVAL; > > + > > + return riscv_get_intc_hartid(parent.fwnode, hartid); > > +} > > + > > +static int __init imsic_get_mmio_resource(struct fwnode_handle *fwnode, > > + u32 index, struct resource *res) > > +{ > > + /* > > + * Currently, only OF fwnode is support so extend this function > > + * for other types of fwnode for ACPI support. > > + */ > > + if (!is_of_node(fwnode)) > > + return -EINVAL; > > + return of_address_to_resource(to_of_node(fwnode), index, res); > > +} > > + > > +int __init imsic_setup_state(struct fwnode_handle *fwnode) > > +{ > > + int rc, cpu; > > + phys_addr_t base_addr; > > + void __iomem **mmios_va = NULL; > > + struct resource res, *mmios = NULL; > > + struct imsic_local_config *local; > > + struct imsic_global_config *global; > > + unsigned long reloff, hartid; > > + u32 i, j, index, nr_parent_irqs, nr_handlers = 0, num_mmios = 0; > > + > > + /* > > + * Only one IMSIC instance allowed in a platform for clean > > + * implementation of SMP IRQ affinity and per-CPU IPIs. > > + * > > + * This means on a multi-socket (or multi-die) platform we > > + * will have multiple MMIO regions for one IMSIC instance. > > + */ > > + if (imsic) { > > + pr_err("%pfwP: already initialized hence ignoring\n", > > + fwnode); > > + return -EALREADY; > > + } > > + > > + if (!riscv_isa_extension_available(NULL, SxAIA)) { > > + pr_err("%pfwP: AIA support not available\n", fwnode); > > + return -ENODEV; > > + } > > + > > + imsic = kzalloc(sizeof(*imsic), GFP_KERNEL); > > + if (!imsic) > > + return -ENOMEM; > > + imsic->fwnode = fwnode; > > + global = &imsic->global; > > + > > + global->local = alloc_percpu(typeof(*(global->local))); > > + if (!global->local) { > > + rc = -ENOMEM; > > + goto out_free_priv; > > + } > > + > > + /* Find number of parent interrupts */ > > + nr_parent_irqs = 0; > > + while (!imsic_get_parent_hartid(fwnode, nr_parent_irqs, &hartid)) > > + nr_parent_irqs++; > > + if (!nr_parent_irqs) { > > + pr_err("%pfwP: no parent irqs available\n", fwnode); > > + rc = -EINVAL; > > + goto out_free_local; > > + } > > + > > + /* Find number of guest index bits in MSI address */ > > + rc = fwnode_property_read_u32_array(fwnode, "riscv,guest-index-bits", > > + &global->guest_index_bits, 1); > > + if (rc) > > + global->guest_index_bits = 0; > > + i = BITS_PER_LONG - IMSIC_MMIO_PAGE_SHIFT; > > + if (i < global->guest_index_bits) { > > + pr_err("%pfwP: guest index bits too big\n", fwnode); > > + rc = -EINVAL; > > + goto out_free_local; > > + } > > + > > + /* Find number of HART index bits */ > > + rc = fwnode_property_read_u32_array(fwnode, "riscv,hart-index-bits", > > + &global->hart_index_bits, 1); > > + if (rc) { > > + /* Assume default value */ > > + global->hart_index_bits = __fls(nr_parent_irqs); > > + if (BIT(global->hart_index_bits) < nr_parent_irqs) > > + global->hart_index_bits++; > > + } > > + i = BITS_PER_LONG - IMSIC_MMIO_PAGE_SHIFT - global->guest_index_bits; > > + if (i < global->hart_index_bits) { > > + pr_err("%pfwP: HART index bits too big\n", fwnode); > > + rc = -EINVAL; > > + goto out_free_local; > > + } > > + > > + /* Find number of group index bits */ > > + rc = fwnode_property_read_u32_array(fwnode, "riscv,group-index-bits", > > + &global->group_index_bits, 1); > > + if (rc) > > + global->group_index_bits = 0; > > + i = BITS_PER_LONG - IMSIC_MMIO_PAGE_SHIFT - > > + global->guest_index_bits - global->hart_index_bits; > > + if (i < global->group_index_bits) { > > + pr_err("%pfwP: group index bits too big\n", fwnode); > > + rc = -EINVAL; > > + goto out_free_local; > > + } > > + > > + /* > > + * Find first bit position of group index. > > + * If not specified assumed the default APLIC-IMSIC configuration. > > + */ > > + rc = fwnode_property_read_u32_array(fwnode, "riscv,group-index-shift", > > + &global->group_index_shift, 1); > > + if (rc) > > + global->group_index_shift = IMSIC_MMIO_PAGE_SHIFT * 2; > > + i = global->group_index_bits + global->group_index_shift - 1; > > + if (i >= BITS_PER_LONG) { > > + pr_err("%pfwP: group index shift too big\n", fwnode); > > + rc = -EINVAL; > > + goto out_free_local; > > + } > > + > > + /* Find number of interrupt identities */ > > + rc = fwnode_property_read_u32_array(fwnode, "riscv,num-ids", > > + &global->nr_ids, 1); > > + if (rc) { > > + pr_err("%pfwP: number of interrupt identities not found\n", > > + fwnode); > > + goto out_free_local; > > + } > > + if ((global->nr_ids < IMSIC_MIN_ID) || > > + (global->nr_ids >= IMSIC_MAX_ID) || > > + ((global->nr_ids & IMSIC_MIN_ID) != IMSIC_MIN_ID)) { > > + pr_err("%pfwP: invalid number of interrupt identities\n", > > + fwnode); > > + rc = -EINVAL; > > + goto out_free_local; > > + } > > + > > + /* Find number of guest interrupt identities */ > > + if (fwnode_property_read_u32_array(fwnode, "riscv,num-guest-ids", > > + &global->nr_guest_ids, 1)) > > + global->nr_guest_ids = global->nr_ids; > > + if ((global->nr_guest_ids < IMSIC_MIN_ID) || > > + (global->nr_guest_ids >= IMSIC_MAX_ID) || > > + ((global->nr_guest_ids & IMSIC_MIN_ID) != IMSIC_MIN_ID)) { > > + pr_err("%pfwP: invalid number of guest interrupt identities\n", > > + fwnode); > > + rc = -EINVAL; > > + goto out_free_local; > > + } > > + > > + /* Compute base address */ > > + rc = imsic_get_mmio_resource(fwnode, 0, &res); > > + if (rc) { > > + pr_err("%pfwP: first MMIO resource not found\n", fwnode); > > + rc = -EINVAL; > > + goto out_free_local; > > + } > > + global->base_addr = res.start; > > + global->base_addr &= ~(BIT(global->guest_index_bits + > > + global->hart_index_bits + > > + IMSIC_MMIO_PAGE_SHIFT) - 1); > > + global->base_addr &= ~((BIT(global->group_index_bits) - 1) << > > + global->group_index_shift); > > + > > + /* Find number of MMIO register sets */ > > + while (!imsic_get_mmio_resource(fwnode, num_mmios, &res)) > > + num_mmios++; > > + > > + /* Allocate MMIO resource array */ > > + mmios = kcalloc(num_mmios, sizeof(*mmios), GFP_KERNEL); > > + if (!mmios) { > > + rc = -ENOMEM; > > + goto out_free_local; > > + } > > + > > + /* Allocate MMIO virtual address array */ > > + mmios_va = kcalloc(num_mmios, sizeof(*mmios_va), GFP_KERNEL); > > + if (!mmios_va) { > > + rc = -ENOMEM; > > + goto out_iounmap; > > + } > > + > > + /* Parse and map MMIO register sets */ > > + for (i = 0; i < num_mmios; i++) { > > + rc = imsic_get_mmio_resource(fwnode, i, &mmios[i]); > > + if (rc) { > > + pr_err("%pfwP: unable to parse MMIO regset %d\n", > > + fwnode, i); > > + goto out_iounmap; > > + } > > + > > + base_addr = mmios[i].start; > > + base_addr &= ~(BIT(global->guest_index_bits + > > + global->hart_index_bits + > > + IMSIC_MMIO_PAGE_SHIFT) - 1); > > + base_addr &= ~((BIT(global->group_index_bits) - 1) << > > + global->group_index_shift); > > + if (base_addr != global->base_addr) { > > + rc = -EINVAL; > > + pr_err("%pfwP: address mismatch for regset %d\n", > > + fwnode, i); > > + goto out_iounmap; > > + } > > + > > + mmios_va[i] = ioremap(mmios[i].start, resource_size(&mmios[i])); > > + if (!mmios_va[i]) { > > + rc = -EIO; > > + pr_err("%pfwP: unable to map MMIO regset %d\n", > > + fwnode, i); > > + goto out_iounmap; > > + } > > + } > > + > > + /* Initialize interrupt identity management */ > > + rc = imsic_ids_init(); > > + if (rc) { > > + pr_err("%pfwP: failed to initialize interrupt management\n", > > + fwnode); > > + goto out_iounmap; > > + } > > + > > + /* Configure handlers for target CPUs */ > > + for (i = 0; i < nr_parent_irqs; i++) { > > + rc = imsic_get_parent_hartid(fwnode, i, &hartid); > > + if (rc) { > > + pr_warn("%pfwP: hart ID for parent irq%d not found\n", > > + fwnode, i); > > + continue; > > + } > > + > > + cpu = riscv_hartid_to_cpuid(hartid); > > + if (cpu < 0) { > > + pr_warn("%pfwP: invalid cpuid for parent irq%d\n", > > + fwnode, i); > > + continue; > > + } > > + > > + /* Find MMIO location of MSI page */ > > + index = num_mmios; > > + reloff = i * BIT(global->guest_index_bits) * > > + IMSIC_MMIO_PAGE_SZ; > > + for (j = 0; num_mmios; j++) { > > + if (reloff < resource_size(&mmios[j])) { > > + index = j; > > + break; > > + } > > + > > + /* > > + * MMIO region size may not be aligned to > > + * BIT(global->guest_index_bits) * IMSIC_MMIO_PAGE_SZ > > + * if holes are present. > > + */ > > + reloff -= ALIGN(resource_size(&mmios[j]), > > + BIT(global->guest_index_bits) * IMSIC_MMIO_PAGE_SZ); > > + } > > + if (index >= num_mmios) { > > + pr_warn("%pfwP: MMIO not found for parent irq%d\n", > > + fwnode, i); > > + continue; > > + } > > + > > + local = per_cpu_ptr(global->local, cpu); > > + local->msi_pa = mmios[index].start + reloff; > > + local->msi_va = mmios_va[index] + reloff; > > + > > + nr_handlers++; > > + } > > + > > + /* If no CPU handlers found then can't take interrupts */ > > + if (!nr_handlers) { > > + pr_err("%pfwP: No CPU handlers found\n", fwnode); > > + rc = -ENODEV; > > + goto out_ids_cleanup; > > + } > > + > > + /* We don't need MMIO arrays anymore so let's free-up */ > > + kfree(mmios_va); > > + kfree(mmios); > > + > > + return 0; > > + > > +out_ids_cleanup: > > + imsic_ids_cleanup(); > > +out_iounmap: > > + for (i = 0; i < num_mmios; i++) { > > + if (mmios_va[i]) > > + iounmap(mmios_va[i]); > > + } > > + kfree(mmios_va); > > + kfree(mmios); > > +out_free_local: > > + free_percpu(imsic->global.local); > > +out_free_priv: > > + kfree(imsic); > > + imsic = NULL; > > + return rc; > > +} > > diff --git a/drivers/irqchip/irq-riscv-imsic-state.h b/drivers/irqchip/irq-riscv-imsic-state.h > > new file mode 100644 > > index 000000000000..3170018949a8 > > --- /dev/null > > +++ b/drivers/irqchip/irq-riscv-imsic-state.h > > @@ -0,0 +1,66 @@ > > +/* SPDX-License-Identifier: GPL-2.0-only */ > > +/* > > + * Copyright (C) 2021 Western Digital Corporation or its affiliates. > > + * Copyright (C) 2022 Ventana Micro Systems Inc. > > + */ > > + > > +#ifndef _IRQ_RISCV_IMSIC_STATE_H > > +#define _IRQ_RISCV_IMSIC_STATE_H > > + > > +#include <linux/irqchip/riscv-imsic.h> > > +#include <linux/irqdomain.h> > > +#include <linux/fwnode.h> > > + > > +struct imsic_priv { > > + /* Device details */ > > + struct fwnode_handle *fwnode; > > + > > + /* Global configuration common for all HARTs */ > > + struct imsic_global_config global; > > + > > + /* Global state of interrupt identities */ > > + raw_spinlock_t ids_lock; > > + unsigned long *ids_used_bimap; > > + unsigned long *ids_enabled_bimap; > > + unsigned int *ids_target_cpu; > > + > > + /* IPI interrupt identity and synchronization */ > > + u32 ipi_id; > > + int ipi_virq; > > + struct irq_desc *ipi_lsync_desc; > > + > > + /* IRQ domains (created by platform driver) */ > > + struct irq_domain *base_domain; > > + struct irq_domain *plat_domain; > > +}; > > + > > +extern struct imsic_priv *imsic; > > + > > +void __imsic_eix_update(unsigned long base_id, > > + unsigned long num_id, bool pend, bool val); > > + > > +#define __imsic_id_enable(__id) \ > > + __imsic_eix_update((__id), 1, false, true) > > +#define __imsic_id_disable(__id) \ > > + __imsic_eix_update((__id), 1, false, false) > > + > > +void imsic_id_set_target(unsigned int id, unsigned int target_cpu); > > +unsigned int imsic_id_get_target(unsigned int id); > > + > > +void imsic_ids_local_sync(void); > > +void imsic_ids_local_delivery(bool enable); > > + > > +#ifdef CONFIG_SMP > > +void imsic_ids_remote_sync(void); > > +#else > > +static inline void imsic_ids_remote_sync(void) > > +{ > > +} > > +#endif > > + > > +int imsic_ids_alloc(unsigned int order); > > +void imsic_ids_free(unsigned int base_id, unsigned int order); > > + > > +int imsic_setup_state(struct fwnode_handle *fwnode); > > + > > +#endif > > diff --git a/include/linux/irqchip/riscv-imsic.h b/include/linux/irqchip/riscv-imsic.h > > new file mode 100644 > > index 000000000000..1f6fc9a57218 > > --- /dev/null > > +++ b/include/linux/irqchip/riscv-imsic.h > > @@ -0,0 +1,86 @@ > > +/* SPDX-License-Identifier: GPL-2.0-only */ > > +/* > > + * Copyright (C) 2021 Western Digital Corporation or its affiliates. > > + * Copyright (C) 2022 Ventana Micro Systems Inc. > > + */ > > +#ifndef __LINUX_IRQCHIP_RISCV_IMSIC_H > > +#define __LINUX_IRQCHIP_RISCV_IMSIC_H > > + > > +#include <linux/types.h> > > +#include <asm/csr.h> > > + > > +#define IMSIC_MMIO_PAGE_SHIFT 12 > > +#define IMSIC_MMIO_PAGE_SZ (1UL << IMSIC_MMIO_PAGE_SHIFT) > > +#define IMSIC_MMIO_PAGE_LE 0x00 > > +#define IMSIC_MMIO_PAGE_BE 0x04 > > + > > +#define IMSIC_MIN_ID 63 > > +#define IMSIC_MAX_ID 2048 > > + > > +#define IMSIC_EIDELIVERY 0x70 > > + > > +#define IMSIC_EITHRESHOLD 0x72 > > + > > +#define IMSIC_EIP0 0x80 > > +#define IMSIC_EIP63 0xbf > > +#define IMSIC_EIPx_BITS 32 > > + > > +#define IMSIC_EIE0 0xc0 > > +#define IMSIC_EIE63 0xff > > +#define IMSIC_EIEx_BITS 32 > > + > > +#define IMSIC_FIRST IMSIC_EIDELIVERY > > +#define IMSIC_LAST IMSIC_EIE63 > > + > > +#define IMSIC_MMIO_SETIPNUM_LE 0x00 > > +#define IMSIC_MMIO_SETIPNUM_BE 0x04 > > + > > +struct imsic_local_config { > > + phys_addr_t msi_pa; > > + void __iomem *msi_va; > > +}; > > + > > +struct imsic_global_config { > > + /* > > + * MSI Target Address Scheme > > + * > > + * XLEN-1 12 0 > > + * | | | > > + * ------------------------------------------------------------- > > + * |xxxxxx|Group Index|xxxxxxxxxxx|HART Index|Guest Index| 0 | > > + * ------------------------------------------------------------- > > + */ > > + > > + /* Bits representing Guest index, HART index, and Group index */ > > + u32 guest_index_bits; > > + u32 hart_index_bits; > > + u32 group_index_bits; > > + u32 group_index_shift; > > + > > + /* Global base address matching all target MSI addresses */ > > + phys_addr_t base_addr; > > + > > + /* Number of interrupt identities */ > > + u32 nr_ids; > > + > > + /* Number of guest interrupt identities */ > > + u32 nr_guest_ids; > > + > > + /* Per-CPU IMSIC addresses */ > > + struct imsic_local_config __percpu *local; > > +}; > > + > > +#ifdef CONFIG_RISCV_IMSIC > > + > > +extern const struct imsic_global_config *imsic_get_global_config(void); > > + > > +#else > > + > > +static inline const struct imsic_global_config *imsic_get_global_config(void) > > +{ > > + return NULL; > > +} > > + > > +#endif > > + > > +#endif > > -- > > 2.34.1 > > > > > > _______________________________________________ > > linux-riscv mailing list > > linux-riscv@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-riscv
On Tue, Sep 12, 2023 at 10:50 AM Anup Patel <apatel@ventanamicro.com> wrote: > > The riscv_of_processor_hartid() used by riscv_of_parent_hartid() fails > for HARTs disabled in the DT. This results in the following warning > thrown by the RISC-V INTC driver for the E-core on SiFive boards: > > [ 0.000000] riscv-intc: unable to find hart id for /cpus/cpu@0/interrupt-controller > > The riscv_of_parent_hartid() is only expected to read the hartid from > the DT so we should directly call of_get_cpu_hwid() instead of calling > riscv_of_processor_hartid(). > > Fixes: ad635e723e17 ("riscv: cpu: Add 64bit hartid support on RV64") > Signed-off-by: Anup Patel <apatel@ventanamicro.com> > --- > arch/riscv/kernel/cpu.c | 11 ++++++----- > 1 file changed, 6 insertions(+), 5 deletions(-) > > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > index c17dacb1141c..157ace8b262c 100644 > --- a/arch/riscv/kernel/cpu.c > +++ b/arch/riscv/kernel/cpu.c > @@ -125,13 +125,14 @@ int __init riscv_early_of_processor_hartid(struct device_node *node, unsigned lo > */ > int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid) > { > - int rc; > - > for (; node; node = node->parent) { > if (of_device_is_compatible(node, "riscv")) { > - rc = riscv_of_processor_hartid(node, hartid); > - if (!rc) > - return 0; > + *hartid = (unsigned long)of_get_cpu_hwid(node, 0); > + if (*hartid == ~0UL) { > + pr_warn("Found CPU without hart ID\n"); > + return -ENODEV; > + } > + return 0; > } > } > > -- > 2.34.1 > LGTM. Reviewed-by: Atish Patra <atishp@rivosinc.com>
On Tue, Sep 12, 2023 at 10:50 AM Anup Patel <apatel@ventanamicro.com> wrote: > > We add a common riscv_get_intc_hartid() which help device drivers to > get hartid of the HART associated with a INTC (i.e. local interrupt > controller) fwnode. This new function is more generic compared to > the existing riscv_of_parent_hartid() function hence we also replace > use of riscv_of_parent_hartid() with riscv_get_intc_hartid(). > > Signed-off-by: Anup Patel <apatel@ventanamicro.com> > --- > arch/riscv/include/asm/processor.h | 4 +++- > arch/riscv/kernel/cpu.c | 13 ++++++++++++- > drivers/irqchip/irq-riscv-intc.c | 2 +- > drivers/irqchip/irq-sifive-plic.c | 3 ++- > 4 files changed, 18 insertions(+), 4 deletions(-) > > diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h > index 3e23e1786d05..3ce64b3bea4e 100644 > --- a/arch/riscv/include/asm/processor.h > +++ b/arch/riscv/include/asm/processor.h > @@ -119,7 +119,9 @@ static inline void wait_for_interrupt(void) > struct device_node; > int riscv_of_processor_hartid(struct device_node *node, unsigned long *hartid); > int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *hartid); > -int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid); > + > +struct fwnode_handle; > +int riscv_get_intc_hartid(struct fwnode_handle *node, unsigned long *hartid); > > extern void riscv_fill_hwcap(void); > extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src); > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > index 157ace8b262c..ee583eac3c5b 100644 > --- a/arch/riscv/kernel/cpu.c > +++ b/arch/riscv/kernel/cpu.c > @@ -123,7 +123,8 @@ int __init riscv_early_of_processor_hartid(struct device_node *node, unsigned lo > * To achieve this, we walk up the DT tree until we find an active > * RISC-V core (HART) node and extract the cpuid from it. > */ > -int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid) > +static int riscv_of_parent_hartid(struct device_node *node, > + unsigned long *hartid) > { > for (; node; node = node->parent) { > if (of_device_is_compatible(node, "riscv")) { > @@ -139,6 +140,16 @@ int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid) > return -1; > } > > +/* Find hart ID of the INTC fwnode. */ > +int riscv_get_intc_hartid(struct fwnode_handle *node, unsigned long *hartid) > +{ > + /* Extend this function ACPI in the future. */ > + if (!is_of_node(node)) > + return -ENODEV; > + > + return riscv_of_parent_hartid(to_of_node(node), hartid); > +} > + > DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); > > unsigned long riscv_cached_mvendorid(unsigned int cpu_id) > diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c > index 4adeee1bc391..65f4a2afb381 100644 > --- a/drivers/irqchip/irq-riscv-intc.c > +++ b/drivers/irqchip/irq-riscv-intc.c > @@ -143,7 +143,7 @@ static int __init riscv_intc_init(struct device_node *node, > int rc; > unsigned long hartid; > > - rc = riscv_of_parent_hartid(node, &hartid); > + rc = riscv_get_intc_hartid(of_fwnode_handle(node), &hartid); > if (rc < 0) { > pr_warn("unable to find hart id for %pOF\n", node); > return 0; > diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c > index e1484905b7bd..56b0544b1f27 100644 > --- a/drivers/irqchip/irq-sifive-plic.c > +++ b/drivers/irqchip/irq-sifive-plic.c > @@ -477,7 +477,8 @@ static int __init __plic_init(struct device_node *node, > continue; > } > > - error = riscv_of_parent_hartid(parent.np, &hartid); > + error = riscv_get_intc_hartid(of_fwnode_handle(parent.np), > + &hartid); > if (error < 0) { > pr_warn("failed to parse hart ID for context %d.\n", i); > continue; > -- > 2.34.1 > Reviewed-by: Atish Patra <atishp@rivosinc.com>
Hi Anup, On Tue, Sep 12, 2023 at 11:19:14PM +0530, Anup Patel wrote: > We add a common riscv_get_intc_hartid() which help device drivers to > get hartid of the HART associated with a INTC (i.e. local interrupt > controller) fwnode. This new function is more generic compared to > the existing riscv_of_parent_hartid() function hence we also replace > use of riscv_of_parent_hartid() with riscv_get_intc_hartid(). > > Signed-off-by: Anup Patel <apatel@ventanamicro.com> > --- > arch/riscv/include/asm/processor.h | 4 +++- > arch/riscv/kernel/cpu.c | 13 ++++++++++++- > drivers/irqchip/irq-riscv-intc.c | 2 +- > drivers/irqchip/irq-sifive-plic.c | 3 ++- > 4 files changed, 18 insertions(+), 4 deletions(-) > > diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h > index 3e23e1786d05..3ce64b3bea4e 100644 > --- a/arch/riscv/include/asm/processor.h > +++ b/arch/riscv/include/asm/processor.h > @@ -119,7 +119,9 @@ static inline void wait_for_interrupt(void) > struct device_node; > int riscv_of_processor_hartid(struct device_node *node, unsigned long *hartid); > int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *hartid); > -int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid); > + > +struct fwnode_handle; > +int riscv_get_intc_hartid(struct fwnode_handle *node, unsigned long *hartid); > > extern void riscv_fill_hwcap(void); > extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src); > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > index 157ace8b262c..ee583eac3c5b 100644 > --- a/arch/riscv/kernel/cpu.c > +++ b/arch/riscv/kernel/cpu.c > @@ -123,7 +123,8 @@ int __init riscv_early_of_processor_hartid(struct device_node *node, unsigned lo > * To achieve this, we walk up the DT tree until we find an active > * RISC-V core (HART) node and extract the cpuid from it. > */ > -int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid) > +static int riscv_of_parent_hartid(struct device_node *node, > + unsigned long *hartid) > { > for (; node; node = node->parent) { > if (of_device_is_compatible(node, "riscv")) { > @@ -139,6 +140,16 @@ int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid) > return -1; > } > > +/* Find hart ID of the INTC fwnode. */ > +int riscv_get_intc_hartid(struct fwnode_handle *node, unsigned long *hartid) > +{ > + /* Extend this function ACPI in the future. */ As per Marc's feedback, we can't use swnode for ACPI irchips. So, there is no need to create this wrapper function and this patch can be dropped. Thanks, Sunil > + if (!is_of_node(node)) > + return -ENODEV; > + > + return riscv_of_parent_hartid(to_of_node(node), hartid); > +} > + > DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); > > unsigned long riscv_cached_mvendorid(unsigned int cpu_id) > diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c > index 4adeee1bc391..65f4a2afb381 100644 > --- a/drivers/irqchip/irq-riscv-intc.c > +++ b/drivers/irqchip/irq-riscv-intc.c > @@ -143,7 +143,7 @@ static int __init riscv_intc_init(struct device_node *node, > int rc; > unsigned long hartid; > > - rc = riscv_of_parent_hartid(node, &hartid); > + rc = riscv_get_intc_hartid(of_fwnode_handle(node), &hartid); > if (rc < 0) { > pr_warn("unable to find hart id for %pOF\n", node); > return 0; > diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c > index e1484905b7bd..56b0544b1f27 100644 > --- a/drivers/irqchip/irq-sifive-plic.c > +++ b/drivers/irqchip/irq-sifive-plic.c > @@ -477,7 +477,8 @@ static int __init __plic_init(struct device_node *node, > continue; > } > > - error = riscv_of_parent_hartid(parent.np, &hartid); > + error = riscv_get_intc_hartid(of_fwnode_handle(parent.np), > + &hartid); > if (error < 0) { > pr_warn("failed to parse hart ID for context %d.\n", i); > continue; > -- > 2.34.1 >
Hi Anup, On Tue, Sep 12, 2023 at 11:19:21PM +0530, Anup Patel wrote: > The RISC-V advanced interrupt architecture (AIA) specification > defines a new MSI controller called incoming message signalled > interrupt controller (IMSIC) which manages MSI on per-HART (or > per-CPU) basis. It also supports IPIs as software injected MSIs. > (For more details refer https://github.com/riscv/riscv-aia) > > Let us add an early irqchip driver for RISC-V IMSIC which sets > up the IMSIC state and provide IPIs. > > Signed-off-by: Anup Patel <apatel@ventanamicro.com> > --- > drivers/irqchip/Kconfig | 7 +- > drivers/irqchip/Makefile | 1 + > drivers/irqchip/irq-riscv-imsic-early.c | 258 ++++++++++++ > drivers/irqchip/irq-riscv-imsic-state.c | 523 ++++++++++++++++++++++++ > drivers/irqchip/irq-riscv-imsic-state.h | 66 +++ > include/linux/irqchip/riscv-imsic.h | 86 ++++ > 6 files changed, 940 insertions(+), 1 deletion(-) > create mode 100644 drivers/irqchip/irq-riscv-imsic-early.c > create mode 100644 drivers/irqchip/irq-riscv-imsic-state.c > create mode 100644 drivers/irqchip/irq-riscv-imsic-state.h > create mode 100644 include/linux/irqchip/riscv-imsic.h > > diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig > index f7149d0f3d45..ee99aacbefcc 100644 > --- a/drivers/irqchip/Kconfig > +++ b/drivers/irqchip/Kconfig > @@ -30,7 +30,6 @@ config ARM_GIC_V2M > > config GIC_NON_BANKED > bool > - > config ARM_GIC_V3 > bool > select IRQ_DOMAIN_HIERARCHY > @@ -546,6 +545,12 @@ config SIFIVE_PLIC > select IRQ_DOMAIN_HIERARCHY > select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP > > +config RISCV_IMSIC > + bool > + depends on RISCV > + select IRQ_DOMAIN_HIERARCHY > + select GENERIC_MSI_IRQ > + > config EXYNOS_IRQ_COMBINER > bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST > depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST > diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile > index ffd945fe71aa..d714724387ce 100644 > --- a/drivers/irqchip/Makefile > +++ b/drivers/irqchip/Makefile > @@ -95,6 +95,7 @@ obj-$(CONFIG_QCOM_MPM) += irq-qcom-mpm.o > obj-$(CONFIG_CSKY_MPINTC) += irq-csky-mpintc.o > obj-$(CONFIG_CSKY_APB_INTC) += irq-csky-apb-intc.o > obj-$(CONFIG_RISCV_INTC) += irq-riscv-intc.o > +obj-$(CONFIG_RISCV_IMSIC) += irq-riscv-imsic-state.o irq-riscv-imsic-early.o > obj-$(CONFIG_SIFIVE_PLIC) += irq-sifive-plic.o > obj-$(CONFIG_IMX_IRQSTEER) += irq-imx-irqsteer.o > obj-$(CONFIG_IMX_INTMUX) += irq-imx-intmux.o > diff --git a/drivers/irqchip/irq-riscv-imsic-early.c b/drivers/irqchip/irq-riscv-imsic-early.c > new file mode 100644 > index 000000000000..1de89ce1ec2f > --- /dev/null > +++ b/drivers/irqchip/irq-riscv-imsic-early.c > @@ -0,0 +1,258 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2021 Western Digital Corporation or its affiliates. > + * Copyright (C) 2022 Ventana Micro Systems Inc. > + */ > + > +#define pr_fmt(fmt) "riscv-imsic: " fmt > +#include <linux/cpu.h> > +#include <linux/interrupt.h> > +#include <linux/io.h> > +#include <linux/irq.h> > +#include <linux/irqchip.h> > +#include <linux/irqchip/chained_irq.h> > +#include <linux/module.h> > +#include <linux/spinlock.h> > +#include <linux/smp.h> > + > +#include "irq-riscv-imsic-state.h" > + > +/* > + * The IMSIC driver uses 1 IPI for ID synchronization and > + * arch/riscv/kernel/smp.c require 6 IPIs so we fix the > + * total number of IPIs to 8. > + */ > +#define IMSIC_NR_IPI 8 > + > +static int imsic_parent_irq; > + > +#ifdef CONFIG_SMP > +static irqreturn_t imsic_ids_sync_handler(int irq, void *data) > +{ > + imsic_ids_local_sync(); > + return IRQ_HANDLED; > +} > + > +void imsic_ids_remote_sync(void) > +{ > + struct cpumask amask; > + > + /* > + * We simply inject ID synchronization IPI to all target CPUs > + * except current CPU. The ipi_send_mask() implementation of > + * IPI mux will inject ID synchronization IPI only for CPUs > + * that have enabled it so offline CPUs won't receive IPI. > + * An offline CPU will unconditionally synchronize IDs through > + * imsic_starting_cpu() when the CPU is brought up. > + */ > + cpumask_andnot(&amask, cpu_online_mask, cpumask_of(smp_processor_id())); > + __ipi_send_mask(imsic->ipi_lsync_desc, &amask); > +} > + > +static void imsic_ipi_send(unsigned int cpu) > +{ > + struct imsic_local_config *local = > + per_cpu_ptr(imsic->global.local, cpu); > + > + writel(imsic->ipi_id, local->msi_va); > +} > + > +static void imsic_ipi_starting_cpu(void) > +{ > + /* Enable IPIs for current CPU. */ > + __imsic_id_enable(imsic->ipi_id); > + > + /* Enable virtual IPI used for IMSIC ID synchronization */ > + enable_percpu_irq(imsic->ipi_virq, 0); > +} > + > +static void imsic_ipi_dying_cpu(void) > +{ > + /* > + * Disable virtual IPI used for IMSIC ID synchronization so > + * that we don't receive ID synchronization requests. > + */ > + disable_percpu_irq(imsic->ipi_virq); > +} > + > +static int __init imsic_ipi_domain_init(void) > +{ > + int virq; > + > + /* Allocate interrupt identity for IPIs */ > + virq = imsic_ids_alloc(get_count_order(1)); > + if (virq < 0) > + return virq; > + imsic->ipi_id = virq; > + > + /* Create IMSIC IPI multiplexing */ > + virq = ipi_mux_create(IMSIC_NR_IPI, imsic_ipi_send); > + if (virq <= 0) { > + imsic_ids_free(imsic->ipi_id, get_count_order(1)); > + return (virq < 0) ? virq : -ENOMEM; > + } > + imsic->ipi_virq = virq; > + > + /* First vIRQ is used for IMSIC ID synchronization */ > + virq = request_percpu_irq(imsic->ipi_virq, imsic_ids_sync_handler, > + "riscv-imsic-lsync", imsic->global.local); > + if (virq) { > + imsic_ids_free(imsic->ipi_id, get_count_order(1)); > + return virq; > + } > + irq_set_status_flags(imsic->ipi_virq, IRQ_HIDDEN); > + imsic->ipi_lsync_desc = irq_to_desc(imsic->ipi_virq); > + > + /* Set vIRQ range */ > + riscv_ipi_set_virq_range(imsic->ipi_virq + 1, IMSIC_NR_IPI - 1, true); > + > + /* Announce that IMSIC is providing IPIs */ > + pr_info("%pfwP: providing IPIs using interrupt %d\n", > + imsic->fwnode, imsic->ipi_id); > + > + return 0; > +} > +#else > +static void imsic_ipi_starting_cpu(void) > +{ > +} > + > +static void imsic_ipi_dying_cpu(void) > +{ > +} > + > +static int __init imsic_ipi_domain_init(void) > +{ > + /* Clear the IPI id because we are not using IPIs */ > + imsic->ipi_id = 0; > + return 0; > +} > +#endif > + > +/* > + * To handle an interrupt, we read the TOPEI CSR and write zero in one > + * instruction. If TOPEI CSR is non-zero then we translate TOPEI.ID to > + * Linux interrupt number and let Linux IRQ subsystem handle it. > + */ > +static void imsic_handle_irq(struct irq_desc *desc) > +{ > + struct irq_chip *chip = irq_desc_get_chip(desc); > + irq_hw_number_t hwirq; > + int err; > + > + chained_irq_enter(chip, desc); > + > + while ((hwirq = csr_swap(CSR_TOPEI, 0))) { > + hwirq = hwirq >> TOPEI_ID_SHIFT; > + > + if (hwirq == imsic->ipi_id) { > +#ifdef CONFIG_SMP > + ipi_mux_process(); > +#endif > + continue; > + } > + > + if (unlikely(!imsic->base_domain)) > + continue; > + > + err = generic_handle_domain_irq(imsic->base_domain, hwirq); > + if (unlikely(err)) > + pr_warn_ratelimited( > + "hwirq %lu mapping not found\n", hwirq); > + } > + > + chained_irq_exit(chip, desc); > +} > + > +static int imsic_starting_cpu(unsigned int cpu) > +{ > + /* Enable per-CPU parent interrupt */ > + enable_percpu_irq(imsic_parent_irq, > + irq_get_trigger_type(imsic_parent_irq)); > + > + /* Setup IPIs */ > + imsic_ipi_starting_cpu(); > + > + /* > + * Interrupts identities might have been enabled/disabled while > + * this CPU was not running so sync-up local enable/disable state. > + */ > + imsic_ids_local_sync(); > + > + /* Enable local interrupt delivery */ > + imsic_ids_local_delivery(true); > + > + return 0; > +} > + > +static int imsic_dying_cpu(unsigned int cpu) > +{ > + /* Cleanup IPIs */ > + imsic_ipi_dying_cpu(); > + > + return 0; > +} > + > +static int __init imsic_early_probe(struct fwnode_handle *fwnode) Can this imsic_early_probe() take an additional pointer as parameter? This parameter can be NULL for DT and we can use to pass the MADT structure in case of ACPI since fwnode in ACPI will not have any properties. The parameter needs to be passed to imsic_setup_state() also. > +{ > + int rc; > + struct irq_domain *domain; > + > + /* Setup IMSIC state */ > + rc = imsic_setup_state(fwnode); > + if (rc) { > + pr_err("%pfwP: failed to setup state (error %d)\n", > + fwnode, rc); > + return rc; > + } > + > + /* Find parent domain and register chained handler */ > + domain = irq_find_matching_fwnode(riscv_get_intc_hwnode(), > + DOMAIN_BUS_ANY); > + if (!domain) { > + pr_err("%pfwP: Failed to find INTC domain\n", fwnode); > + return -ENOENT; > + } > + imsic_parent_irq = irq_create_mapping(domain, RV_IRQ_EXT); > + if (!imsic_parent_irq) { > + pr_err("%pfwP: Failed to create INTC mapping\n", fwnode); > + return -ENOENT; > + } > + irq_set_chained_handler(imsic_parent_irq, imsic_handle_irq); > + > + /* Initialize IPI domain */ > + rc = imsic_ipi_domain_init(); > + if (rc) { > + pr_err("%pfwP: Failed to initialize IPI domain\n", fwnode); > + return rc; > + } > + > + /* > + * Setup cpuhp state (must be done after setting imsic_parent_irq) > + * > + * Don't disable per-CPU IMSIC file when CPU goes offline > + * because this affects IPI and the masking/unmasking of > + * virtual IPIs is done via generic IPI-Mux > + */ > + cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, > + "irqchip/riscv/imsic:starting", > + imsic_starting_cpu, imsic_dying_cpu); > + > + return 0; > +} > + > +static int __init imsic_early_dt_init(struct device_node *node, > + struct device_node *parent) > +{ > + int rc; > + > + /* Do early setup of IMSIC state and IPIs */ > + rc = imsic_early_probe(&node->fwnode); > + if (rc) > + return rc; > + > + /* Ensure that OF platform device gets probed */ > + of_node_clear_flag(node, OF_POPULATED); > + return 0; > +} > +IRQCHIP_DECLARE(riscv_imsic, "riscv,imsics", imsic_early_dt_init); > diff --git a/drivers/irqchip/irq-riscv-imsic-state.c b/drivers/irqchip/irq-riscv-imsic-state.c > new file mode 100644 > index 000000000000..412b5b919dcc > --- /dev/null > +++ b/drivers/irqchip/irq-riscv-imsic-state.c > @@ -0,0 +1,523 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2021 Western Digital Corporation or its affiliates. > + * Copyright (C) 2022 Ventana Micro Systems Inc. > + */ > + > +#define pr_fmt(fmt) "riscv-imsic: " fmt > +#include <linux/bitmap.h> > +#include <linux/module.h> > +#include <linux/of_address.h> > +#include <linux/spinlock.h> > +#include <linux/smp.h> > +#include <asm/hwcap.h> > + > +#include "irq-riscv-imsic-state.h" > + > +#define IMSIC_DISABLE_EIDELIVERY 0 > +#define IMSIC_ENABLE_EIDELIVERY 1 > +#define IMSIC_DISABLE_EITHRESHOLD 1 > +#define IMSIC_ENABLE_EITHRESHOLD 0 > + > +#define imsic_csr_write(__c, __v) \ > +do { \ > + csr_write(CSR_ISELECT, __c); \ > + csr_write(CSR_IREG, __v); \ > +} while (0) > + > +#define imsic_csr_read(__c) \ > +({ \ > + unsigned long __v; \ > + csr_write(CSR_ISELECT, __c); \ > + __v = csr_read(CSR_IREG); \ > + __v; \ > +}) > + > +#define imsic_csr_set(__c, __v) \ > +do { \ > + csr_write(CSR_ISELECT, __c); \ > + csr_set(CSR_IREG, __v); \ > +} while (0) > + > +#define imsic_csr_clear(__c, __v) \ > +do { \ > + csr_write(CSR_ISELECT, __c); \ > + csr_clear(CSR_IREG, __v); \ > +} while (0) > + > +struct imsic_priv *imsic; > + > +const struct imsic_global_config *imsic_get_global_config(void) > +{ > + return (imsic) ? &imsic->global : NULL; > +} > +EXPORT_SYMBOL_GPL(imsic_get_global_config); > + > +void __imsic_eix_update(unsigned long base_id, > + unsigned long num_id, bool pend, bool val) > +{ > + unsigned long i, isel, ireg; > + unsigned long id = base_id, last_id = base_id + num_id; > + > + while (id < last_id) { > + isel = id / BITS_PER_LONG; > + isel *= BITS_PER_LONG / IMSIC_EIPx_BITS; > + isel += (pend) ? IMSIC_EIP0 : IMSIC_EIE0; > + > + ireg = 0; > + for (i = id & (__riscv_xlen - 1); > + (id < last_id) && (i < __riscv_xlen); i++) { > + ireg |= BIT(i); > + id++; > + } > + > + /* > + * The IMSIC EIEx and EIPx registers are indirectly > + * accessed via using ISELECT and IREG CSRs so we > + * need to access these CSRs without getting preempted. > + * > + * All existing users of this function call this > + * function with local IRQs disabled so we don't > + * need to do anything special here. > + */ > + if (val) > + imsic_csr_set(isel, ireg); > + else > + imsic_csr_clear(isel, ireg); > + } > +} > + > +void imsic_id_set_target(unsigned int id, unsigned int target_cpu) > +{ > + unsigned long flags; > + > + raw_spin_lock_irqsave(&imsic->ids_lock, flags); > + imsic->ids_target_cpu[id] = target_cpu; > + raw_spin_unlock_irqrestore(&imsic->ids_lock, flags); > +} > + > +unsigned int imsic_id_get_target(unsigned int id) > +{ > + unsigned int ret; > + unsigned long flags; > + > + raw_spin_lock_irqsave(&imsic->ids_lock, flags); > + ret = imsic->ids_target_cpu[id]; > + raw_spin_unlock_irqrestore(&imsic->ids_lock, flags); > + > + return ret; > +} > + > +void imsic_ids_local_sync(void) > +{ > + int i; > + unsigned long flags; > + > + raw_spin_lock_irqsave(&imsic->ids_lock, flags); > + for (i = 1; i <= imsic->global.nr_ids; i++) { > + if (imsic->ipi_id == i) > + continue; > + > + if (test_bit(i, imsic->ids_enabled_bimap)) > + __imsic_id_enable(i); > + else > + __imsic_id_disable(i); > + } > + raw_spin_unlock_irqrestore(&imsic->ids_lock, flags); > +} > + > +void imsic_ids_local_delivery(bool enable) > +{ > + if (enable) { > + imsic_csr_write(IMSIC_EITHRESHOLD, IMSIC_ENABLE_EITHRESHOLD); > + imsic_csr_write(IMSIC_EIDELIVERY, IMSIC_ENABLE_EIDELIVERY); > + } else { > + imsic_csr_write(IMSIC_EIDELIVERY, IMSIC_DISABLE_EIDELIVERY); > + imsic_csr_write(IMSIC_EITHRESHOLD, IMSIC_DISABLE_EITHRESHOLD); > + } > +} > + > +int imsic_ids_alloc(unsigned int order) > +{ > + int ret; > + unsigned long flags; > + > + raw_spin_lock_irqsave(&imsic->ids_lock, flags); > + ret = bitmap_find_free_region(imsic->ids_used_bimap, > + imsic->global.nr_ids + 1, order); > + raw_spin_unlock_irqrestore(&imsic->ids_lock, flags); > + > + return ret; > +} > + > +void imsic_ids_free(unsigned int base_id, unsigned int order) > +{ > + unsigned long flags; > + > + raw_spin_lock_irqsave(&imsic->ids_lock, flags); > + bitmap_release_region(imsic->ids_used_bimap, base_id, order); > + raw_spin_unlock_irqrestore(&imsic->ids_lock, flags); > +} > + > +static int __init imsic_ids_init(void) > +{ > + int i; > + struct imsic_global_config *global = &imsic->global; > + > + raw_spin_lock_init(&imsic->ids_lock); > + > + /* Allocate used bitmap */ > + imsic->ids_used_bimap = bitmap_zalloc(global->nr_ids + 1, GFP_KERNEL); > + if (!imsic->ids_used_bimap) > + return -ENOMEM; > + > + /* Allocate enabled bitmap */ > + imsic->ids_enabled_bimap = bitmap_zalloc(global->nr_ids + 1, > + GFP_KERNEL); > + if (!imsic->ids_enabled_bimap) { > + kfree(imsic->ids_used_bimap); > + return -ENOMEM; > + } > + > + /* Allocate target CPU array */ > + imsic->ids_target_cpu = kcalloc(global->nr_ids + 1, > + sizeof(unsigned int), GFP_KERNEL); > + if (!imsic->ids_target_cpu) { > + bitmap_free(imsic->ids_enabled_bimap); > + bitmap_free(imsic->ids_used_bimap); > + return -ENOMEM; > + } > + for (i = 0; i <= global->nr_ids; i++) > + imsic->ids_target_cpu[i] = UINT_MAX; > + > + /* Reserve ID#0 because it is special and never implemented */ > + bitmap_set(imsic->ids_used_bimap, 0, 1); > + > + return 0; > +} > + > +static void __init imsic_ids_cleanup(void) > +{ > + kfree(imsic->ids_target_cpu); > + bitmap_free(imsic->ids_enabled_bimap); > + bitmap_free(imsic->ids_used_bimap); > +} > + > +static int __init imsic_get_parent_hartid(struct fwnode_handle *fwnode, > + u32 index, unsigned long *hartid) > +{ > + int rc; > + struct fwnode_reference_args parent; > + > + rc = fwnode_property_get_reference_args(fwnode, > + "interrupts-extended", "#interrupt-cells", > + 0, index, &parent); > + if (rc) > + return rc; > + > + /* > + * Skip interrupts other than external interrupts for > + * current privilege level. > + */ > + if (parent.args[0] != RV_IRQ_EXT) > + return -EINVAL; > + > + return riscv_get_intc_hartid(parent.fwnode, hartid); > +} > + > +static int __init imsic_get_mmio_resource(struct fwnode_handle *fwnode, > + u32 index, struct resource *res) > +{ > + /* > + * Currently, only OF fwnode is support so extend this function > + * for other types of fwnode for ACPI support. > + */ > + if (!is_of_node(fwnode)) > + return -EINVAL; > + return of_address_to_resource(to_of_node(fwnode), index, res); > +} > + > +int __init imsic_setup_state(struct fwnode_handle *fwnode) > +{ > + int rc, cpu; > + phys_addr_t base_addr; > + void __iomem **mmios_va = NULL; > + struct resource res, *mmios = NULL; > + struct imsic_local_config *local; > + struct imsic_global_config *global; > + unsigned long reloff, hartid; > + u32 i, j, index, nr_parent_irqs, nr_handlers = 0, num_mmios = 0; > + > + /* > + * Only one IMSIC instance allowed in a platform for clean > + * implementation of SMP IRQ affinity and per-CPU IPIs. > + * > + * This means on a multi-socket (or multi-die) platform we > + * will have multiple MMIO regions for one IMSIC instance. > + */ > + if (imsic) { > + pr_err("%pfwP: already initialized hence ignoring\n", > + fwnode); > + return -EALREADY; > + } > + > + if (!riscv_isa_extension_available(NULL, SxAIA)) { > + pr_err("%pfwP: AIA support not available\n", fwnode); > + return -ENODEV; > + } > + > + imsic = kzalloc(sizeof(*imsic), GFP_KERNEL); > + if (!imsic) > + return -ENOMEM; > + imsic->fwnode = fwnode; > + global = &imsic->global; > + > + global->local = alloc_percpu(typeof(*(global->local))); > + if (!global->local) { > + rc = -ENOMEM; > + goto out_free_priv; > + } > + > + /* Find number of parent interrupts */ > + nr_parent_irqs = 0; > + while (!imsic_get_parent_hartid(fwnode, nr_parent_irqs, &hartid)) > + nr_parent_irqs++; > + if (!nr_parent_irqs) { > + pr_err("%pfwP: no parent irqs available\n", fwnode); > + rc = -EINVAL; > + goto out_free_local; > + } > + > + /* Find number of guest index bits in MSI address */ > + rc = fwnode_property_read_u32_array(fwnode, "riscv,guest-index-bits", > + &global->guest_index_bits, 1); > + if (rc) > + global->guest_index_bits = 0; > + i = BITS_PER_LONG - IMSIC_MMIO_PAGE_SHIFT; > + if (i < global->guest_index_bits) { > + pr_err("%pfwP: guest index bits too big\n", fwnode); > + rc = -EINVAL; > + goto out_free_local; > + } > + > + /* Find number of HART index bits */ > + rc = fwnode_property_read_u32_array(fwnode, "riscv,hart-index-bits", > + &global->hart_index_bits, 1); > + if (rc) { > + /* Assume default value */ > + global->hart_index_bits = __fls(nr_parent_irqs); > + if (BIT(global->hart_index_bits) < nr_parent_irqs) > + global->hart_index_bits++; > + } > + i = BITS_PER_LONG - IMSIC_MMIO_PAGE_SHIFT - global->guest_index_bits; > + if (i < global->hart_index_bits) { > + pr_err("%pfwP: HART index bits too big\n", fwnode); > + rc = -EINVAL; > + goto out_free_local; > + } > + > + /* Find number of group index bits */ > + rc = fwnode_property_read_u32_array(fwnode, "riscv,group-index-bits", > + &global->group_index_bits, 1); > + if (rc) > + global->group_index_bits = 0; > + i = BITS_PER_LONG - IMSIC_MMIO_PAGE_SHIFT - > + global->guest_index_bits - global->hart_index_bits; > + if (i < global->group_index_bits) { > + pr_err("%pfwP: group index bits too big\n", fwnode); > + rc = -EINVAL; > + goto out_free_local; > + } > + > + /* > + * Find first bit position of group index. > + * If not specified assumed the default APLIC-IMSIC configuration. > + */ > + rc = fwnode_property_read_u32_array(fwnode, "riscv,group-index-shift", > + &global->group_index_shift, 1); > + if (rc) > + global->group_index_shift = IMSIC_MMIO_PAGE_SHIFT * 2; > + i = global->group_index_bits + global->group_index_shift - 1; > + if (i >= BITS_PER_LONG) { > + pr_err("%pfwP: group index shift too big\n", fwnode); > + rc = -EINVAL; > + goto out_free_local; > + } > + > + /* Find number of interrupt identities */ > + rc = fwnode_property_read_u32_array(fwnode, "riscv,num-ids", > + &global->nr_ids, 1); > + if (rc) { > + pr_err("%pfwP: number of interrupt identities not found\n", > + fwnode); > + goto out_free_local; > + } > + if ((global->nr_ids < IMSIC_MIN_ID) || > + (global->nr_ids >= IMSIC_MAX_ID) || > + ((global->nr_ids & IMSIC_MIN_ID) != IMSIC_MIN_ID)) { > + pr_err("%pfwP: invalid number of interrupt identities\n", > + fwnode); > + rc = -EINVAL; > + goto out_free_local; > + } > + > + /* Find number of guest interrupt identities */ > + if (fwnode_property_read_u32_array(fwnode, "riscv,num-guest-ids", > + &global->nr_guest_ids, 1)) > + global->nr_guest_ids = global->nr_ids; > + if ((global->nr_guest_ids < IMSIC_MIN_ID) || > + (global->nr_guest_ids >= IMSIC_MAX_ID) || > + ((global->nr_guest_ids & IMSIC_MIN_ID) != IMSIC_MIN_ID)) { > + pr_err("%pfwP: invalid number of guest interrupt identities\n", > + fwnode); > + rc = -EINVAL; > + goto out_free_local; > + } > + Could you create a separate function for DT to fill up this imsic_global structure? In case of ACPI, we can not get this data from the fwnode and hence need to have separate function to fill up this structure. Thanks! Sunil > + /* Compute base address */ > + rc = imsic_get_mmio_resource(fwnode, 0, &res); > + if (rc) { > + pr_err("%pfwP: first MMIO resource not found\n", fwnode); > + rc = -EINVAL; > + goto out_free_local; > + } > + global->base_addr = res.start; > + global->base_addr &= ~(BIT(global->guest_index_bits + > + global->hart_index_bits + > + IMSIC_MMIO_PAGE_SHIFT) - 1); > + global->base_addr &= ~((BIT(global->group_index_bits) - 1) << > + global->group_index_shift); > + > + /* Find number of MMIO register sets */ > + while (!imsic_get_mmio_resource(fwnode, num_mmios, &res)) > + num_mmios++; > + > + /* Allocate MMIO resource array */ > + mmios = kcalloc(num_mmios, sizeof(*mmios), GFP_KERNEL); > + if (!mmios) { > + rc = -ENOMEM; > + goto out_free_local; > + } > + > + /* Allocate MMIO virtual address array */ > + mmios_va = kcalloc(num_mmios, sizeof(*mmios_va), GFP_KERNEL); > + if (!mmios_va) { > + rc = -ENOMEM; > + goto out_iounmap; > + } > + > + /* Parse and map MMIO register sets */ > + for (i = 0; i < num_mmios; i++) { > + rc = imsic_get_mmio_resource(fwnode, i, &mmios[i]); > + if (rc) { > + pr_err("%pfwP: unable to parse MMIO regset %d\n", > + fwnode, i); > + goto out_iounmap; > + } > + > + base_addr = mmios[i].start; > + base_addr &= ~(BIT(global->guest_index_bits + > + global->hart_index_bits + > + IMSIC_MMIO_PAGE_SHIFT) - 1); > + base_addr &= ~((BIT(global->group_index_bits) - 1) << > + global->group_index_shift); > + if (base_addr != global->base_addr) { > + rc = -EINVAL; > + pr_err("%pfwP: address mismatch for regset %d\n", > + fwnode, i); > + goto out_iounmap; > + } > + > + mmios_va[i] = ioremap(mmios[i].start, resource_size(&mmios[i])); > + if (!mmios_va[i]) { > + rc = -EIO; > + pr_err("%pfwP: unable to map MMIO regset %d\n", > + fwnode, i); > + goto out_iounmap; > + } > + } > + > + /* Initialize interrupt identity management */ > + rc = imsic_ids_init(); > + if (rc) { > + pr_err("%pfwP: failed to initialize interrupt management\n", > + fwnode); > + goto out_iounmap; > + } > + > + /* Configure handlers for target CPUs */ > + for (i = 0; i < nr_parent_irqs; i++) { > + rc = imsic_get_parent_hartid(fwnode, i, &hartid); > + if (rc) { > + pr_warn("%pfwP: hart ID for parent irq%d not found\n", > + fwnode, i); > + continue; > + } > + > + cpu = riscv_hartid_to_cpuid(hartid); > + if (cpu < 0) { > + pr_warn("%pfwP: invalid cpuid for parent irq%d\n", > + fwnode, i); > + continue; > + } > + > + /* Find MMIO location of MSI page */ > + index = num_mmios; > + reloff = i * BIT(global->guest_index_bits) * > + IMSIC_MMIO_PAGE_SZ; > + for (j = 0; num_mmios; j++) { > + if (reloff < resource_size(&mmios[j])) { > + index = j; > + break; > + } > + > + /* > + * MMIO region size may not be aligned to > + * BIT(global->guest_index_bits) * IMSIC_MMIO_PAGE_SZ > + * if holes are present. > + */ > + reloff -= ALIGN(resource_size(&mmios[j]), > + BIT(global->guest_index_bits) * IMSIC_MMIO_PAGE_SZ); > + } > + if (index >= num_mmios) { > + pr_warn("%pfwP: MMIO not found for parent irq%d\n", > + fwnode, i); > + continue; > + } > + > + local = per_cpu_ptr(global->local, cpu); > + local->msi_pa = mmios[index].start + reloff; > + local->msi_va = mmios_va[index] + reloff; > + > + nr_handlers++; > + } > + > + /* If no CPU handlers found then can't take interrupts */ > + if (!nr_handlers) { > + pr_err("%pfwP: No CPU handlers found\n", fwnode); > + rc = -ENODEV; > + goto out_ids_cleanup; > + } > + > + /* We don't need MMIO arrays anymore so let's free-up */ > + kfree(mmios_va); > + kfree(mmios); > + > + return 0; > + > +out_ids_cleanup: > + imsic_ids_cleanup(); > +out_iounmap: > + for (i = 0; i < num_mmios; i++) { > + if (mmios_va[i]) > + iounmap(mmios_va[i]); > + } > + kfree(mmios_va); > + kfree(mmios); > +out_free_local: > + free_percpu(imsic->global.local); > +out_free_priv: > + kfree(imsic); > + imsic = NULL; > + return rc; > +} > diff --git a/drivers/irqchip/irq-riscv-imsic-state.h b/drivers/irqchip/irq-riscv-imsic-state.h > new file mode 100644 > index 000000000000..3170018949a8 > --- /dev/null > +++ b/drivers/irqchip/irq-riscv-imsic-state.h > @@ -0,0 +1,66 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (C) 2021 Western Digital Corporation or its affiliates. > + * Copyright (C) 2022 Ventana Micro Systems Inc. > + */ > + > +#ifndef _IRQ_RISCV_IMSIC_STATE_H > +#define _IRQ_RISCV_IMSIC_STATE_H > + > +#include <linux/irqchip/riscv-imsic.h> > +#include <linux/irqdomain.h> > +#include <linux/fwnode.h> > + > +struct imsic_priv { > + /* Device details */ > + struct fwnode_handle *fwnode; > + > + /* Global configuration common for all HARTs */ > + struct imsic_global_config global; > + > + /* Global state of interrupt identities */ > + raw_spinlock_t ids_lock; > + unsigned long *ids_used_bimap; > + unsigned long *ids_enabled_bimap; > + unsigned int *ids_target_cpu; > + > + /* IPI interrupt identity and synchronization */ > + u32 ipi_id; > + int ipi_virq; > + struct irq_desc *ipi_lsync_desc; > + > + /* IRQ domains (created by platform driver) */ > + struct irq_domain *base_domain; > + struct irq_domain *plat_domain; > +}; > + > +extern struct imsic_priv *imsic; > + > +void __imsic_eix_update(unsigned long base_id, > + unsigned long num_id, bool pend, bool val); > + > +#define __imsic_id_enable(__id) \ > + __imsic_eix_update((__id), 1, false, true) > +#define __imsic_id_disable(__id) \ > + __imsic_eix_update((__id), 1, false, false) > + > +void imsic_id_set_target(unsigned int id, unsigned int target_cpu); > +unsigned int imsic_id_get_target(unsigned int id); > + > +void imsic_ids_local_sync(void); > +void imsic_ids_local_delivery(bool enable); > + > +#ifdef CONFIG_SMP > +void imsic_ids_remote_sync(void); > +#else > +static inline void imsic_ids_remote_sync(void) > +{ > +} > +#endif > + > +int imsic_ids_alloc(unsigned int order); > +void imsic_ids_free(unsigned int base_id, unsigned int order); > + > +int imsic_setup_state(struct fwnode_handle *fwnode); > + > +#endif > diff --git a/include/linux/irqchip/riscv-imsic.h b/include/linux/irqchip/riscv-imsic.h > new file mode 100644 > index 000000000000..1f6fc9a57218 > --- /dev/null > +++ b/include/linux/irqchip/riscv-imsic.h > @@ -0,0 +1,86 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (C) 2021 Western Digital Corporation or its affiliates. > + * Copyright (C) 2022 Ventana Micro Systems Inc. > + */ > +#ifndef __LINUX_IRQCHIP_RISCV_IMSIC_H > +#define __LINUX_IRQCHIP_RISCV_IMSIC_H > + > +#include <linux/types.h> > +#include <asm/csr.h> > + > +#define IMSIC_MMIO_PAGE_SHIFT 12 > +#define IMSIC_MMIO_PAGE_SZ (1UL << IMSIC_MMIO_PAGE_SHIFT) > +#define IMSIC_MMIO_PAGE_LE 0x00 > +#define IMSIC_MMIO_PAGE_BE 0x04 > + > +#define IMSIC_MIN_ID 63 > +#define IMSIC_MAX_ID 2048 > + > +#define IMSIC_EIDELIVERY 0x70 > + > +#define IMSIC_EITHRESHOLD 0x72 > + > +#define IMSIC_EIP0 0x80 > +#define IMSIC_EIP63 0xbf > +#define IMSIC_EIPx_BITS 32 > + > +#define IMSIC_EIE0 0xc0 > +#define IMSIC_EIE63 0xff > +#define IMSIC_EIEx_BITS 32 > + > +#define IMSIC_FIRST IMSIC_EIDELIVERY > +#define IMSIC_LAST IMSIC_EIE63 > + > +#define IMSIC_MMIO_SETIPNUM_LE 0x00 > +#define IMSIC_MMIO_SETIPNUM_BE 0x04 > + > +struct imsic_local_config { > + phys_addr_t msi_pa; > + void __iomem *msi_va; > +}; > + > +struct imsic_global_config { > + /* > + * MSI Target Address Scheme > + * > + * XLEN-1 12 0 > + * | | | > + * ------------------------------------------------------------- > + * |xxxxxx|Group Index|xxxxxxxxxxx|HART Index|Guest Index| 0 | > + * ------------------------------------------------------------- > + */ > + > + /* Bits representing Guest index, HART index, and Group index */ > + u32 guest_index_bits; > + u32 hart_index_bits; > + u32 group_index_bits; > + u32 group_index_shift; > + > + /* Global base address matching all target MSI addresses */ > + phys_addr_t base_addr; > + > + /* Number of interrupt identities */ > + u32 nr_ids; > + > + /* Number of guest interrupt identities */ > + u32 nr_guest_ids; > + > + /* Per-CPU IMSIC addresses */ > + struct imsic_local_config __percpu *local; > +}; > + > +#ifdef CONFIG_RISCV_IMSIC > + > +extern const struct imsic_global_config *imsic_get_global_config(void); > + > +#else > + > +static inline const struct imsic_global_config *imsic_get_global_config(void) > +{ > + return NULL; > +} > + > +#endif > + > +#endif > -- > 2.34.1 >
Hi Anup, On Tue, Sep 12, 2023 at 11:19:25PM +0530, Anup Patel wrote: > The RISC-V advanced interrupt architecture (AIA) specification defines > advanced platform-level interrupt controller (APLIC) which has two modes > of operation: 1) Direct mode and 2) MSI mode. > (For more details, refer https://github.com/riscv/riscv-aia) > > In APLIC direct-mode, wired interrupts are forwared to CPUs (or HARTs) > as a local external interrupt. > > We add a platform irqchip driver for the RISC-V APLIC direct-mode to > support RISC-V platforms having only wired interrupts. > > Signed-off-by: Anup Patel <apatel@ventanamicro.com> > --- > drivers/irqchip/Kconfig | 5 + > drivers/irqchip/Makefile | 1 + > drivers/irqchip/irq-riscv-aplic-direct.c | 326 +++++++++++++++++++++++ > drivers/irqchip/irq-riscv-aplic-main.c | 240 +++++++++++++++++ > drivers/irqchip/irq-riscv-aplic-main.h | 45 ++++ > include/linux/irqchip/riscv-aplic.h | 119 +++++++++ > 6 files changed, 736 insertions(+) > create mode 100644 drivers/irqchip/irq-riscv-aplic-direct.c > create mode 100644 drivers/irqchip/irq-riscv-aplic-main.c > create mode 100644 drivers/irqchip/irq-riscv-aplic-main.h > create mode 100644 include/linux/irqchip/riscv-aplic.h > > diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig > index a6aad78076a0..44c455084d09 100644 > --- a/drivers/irqchip/Kconfig > +++ b/drivers/irqchip/Kconfig > @@ -545,6 +545,11 @@ config SIFIVE_PLIC > select IRQ_DOMAIN_HIERARCHY > select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP > > +config RISCV_APLIC > + bool > + depends on RISCV > + select IRQ_DOMAIN_HIERARCHY > + > config RISCV_IMSIC > bool > depends on RISCV > diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile > index abca445a3229..7f8289790ed8 100644 > --- a/drivers/irqchip/Makefile > +++ b/drivers/irqchip/Makefile > @@ -95,6 +95,7 @@ obj-$(CONFIG_QCOM_MPM) += irq-qcom-mpm.o > obj-$(CONFIG_CSKY_MPINTC) += irq-csky-mpintc.o > obj-$(CONFIG_CSKY_APB_INTC) += irq-csky-apb-intc.o > obj-$(CONFIG_RISCV_INTC) += irq-riscv-intc.o > +obj-$(CONFIG_RISCV_APLIC) += irq-riscv-aplic-main.o irq-riscv-aplic-direct.o > obj-$(CONFIG_RISCV_IMSIC) += irq-riscv-imsic-state.o irq-riscv-imsic-early.o irq-riscv-imsic-platform.o > obj-$(CONFIG_SIFIVE_PLIC) += irq-sifive-plic.o > obj-$(CONFIG_IMX_IRQSTEER) += irq-imx-irqsteer.o > diff --git a/drivers/irqchip/irq-riscv-aplic-direct.c b/drivers/irqchip/irq-riscv-aplic-direct.c > new file mode 100644 > index 000000000000..e36d655a1490 > --- /dev/null > +++ b/drivers/irqchip/irq-riscv-aplic-direct.c > @@ -0,0 +1,326 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2021 Western Digital Corporation or its affiliates. > + * Copyright (C) 2022 Ventana Micro Systems Inc. > + */ > + > +#include <linux/bitops.h> > +#include <linux/cpu.h> > +#include <linux/interrupt.h> > +#include <linux/irqchip.h> > +#include <linux/irqchip/chained_irq.h> > +#include <linux/irqchip/riscv-aplic.h> > +#include <linux/module.h> > +#include <linux/of_address.h> > +#include <linux/printk.h> > +#include <linux/smp.h> > + > +#include "irq-riscv-aplic-main.h" > + > +#define APLIC_DISABLE_IDELIVERY 0 > +#define APLIC_ENABLE_IDELIVERY 1 > +#define APLIC_DISABLE_ITHRESHOLD 1 > +#define APLIC_ENABLE_ITHRESHOLD 0 > + > +struct aplic_direct { > + struct aplic_priv priv; > + struct irq_domain *irqdomain; > + struct cpumask lmask; > +}; > + > +struct aplic_idc { > + unsigned int hart_index; > + void __iomem *regs; > + struct aplic_direct *direct; > +}; > + > +static unsigned int aplic_direct_parent_irq; > +static DEFINE_PER_CPU(struct aplic_idc, aplic_idcs); > + > +static void aplic_direct_irq_eoi(struct irq_data *d) > +{ > + /* > + * The fasteoi_handler requires irq_eoi() callback hence > + * provide a dummy handler. > + */ > +} > + > +#ifdef CONFIG_SMP > +static int aplic_direct_set_affinity(struct irq_data *d, > + const struct cpumask *mask_val, bool force) > +{ > + struct aplic_priv *priv = irq_data_get_irq_chip_data(d); > + struct aplic_direct *direct = > + container_of(priv, struct aplic_direct, priv); > + struct aplic_idc *idc; > + unsigned int cpu, val; > + struct cpumask amask; > + void __iomem *target; > + > + cpumask_and(&amask, &direct->lmask, mask_val); > + > + if (force) > + cpu = cpumask_first(&amask); > + else > + cpu = cpumask_any_and(&amask, cpu_online_mask); > + > + if (cpu >= nr_cpu_ids) > + return -EINVAL; > + > + idc = per_cpu_ptr(&aplic_idcs, cpu); > + target = priv->regs + APLIC_TARGET_BASE; > + target += (d->hwirq - 1) * sizeof(u32); > + val = idc->hart_index & APLIC_TARGET_HART_IDX_MASK; > + val <<= APLIC_TARGET_HART_IDX_SHIFT; > + val |= APLIC_DEFAULT_PRIORITY; > + writel(val, target); > + > + irq_data_update_effective_affinity(d, cpumask_of(cpu)); > + > + return IRQ_SET_MASK_OK_DONE; > +} > +#endif > + > +static struct irq_chip aplic_direct_chip = { > + .name = "APLIC-DIRECT", > + .irq_mask = aplic_irq_mask, > + .irq_unmask = aplic_irq_unmask, > + .irq_set_type = aplic_irq_set_type, > + .irq_eoi = aplic_direct_irq_eoi, > +#ifdef CONFIG_SMP > + .irq_set_affinity = aplic_direct_set_affinity, > +#endif > + .flags = IRQCHIP_SET_TYPE_MASKED | > + IRQCHIP_SKIP_SET_WAKE | > + IRQCHIP_MASK_ON_SUSPEND, > +}; > + > +static int aplic_direct_irqdomain_translate(struct irq_domain *d, > + struct irq_fwspec *fwspec, > + unsigned long *hwirq, > + unsigned int *type) > +{ > + struct aplic_priv *priv = d->host_data; > + > + return aplic_irqdomain_translate(fwspec, priv->gsi_base, > + hwirq, type); > +} > + > +static int aplic_direct_irqdomain_alloc(struct irq_domain *domain, > + unsigned int virq, unsigned int nr_irqs, > + void *arg) > +{ > + int i, ret; > + unsigned int type; > + irq_hw_number_t hwirq; > + struct irq_fwspec *fwspec = arg; > + struct aplic_priv *priv = domain->host_data; > + struct aplic_direct *direct = > + container_of(priv, struct aplic_direct, priv); > + > + ret = aplic_irqdomain_translate(fwspec, priv->gsi_base, > + &hwirq, &type); > + if (ret) > + return ret; > + > + for (i = 0; i < nr_irqs; i++) { > + irq_domain_set_info(domain, virq + i, hwirq + i, > + &aplic_direct_chip, priv, > + handle_fasteoi_irq, NULL, NULL); > + irq_set_affinity(virq + i, &direct->lmask); > + /* See the reason described in aplic_msi_irqdomain_alloc() */ > + irq_set_status_flags(virq + i, IRQ_DISABLE_UNLAZY); > + } > + > + return 0; > +} > + > +static const struct irq_domain_ops aplic_direct_irqdomain_ops = { > + .translate = aplic_direct_irqdomain_translate, > + .alloc = aplic_direct_irqdomain_alloc, > + .free = irq_domain_free_irqs_top, > +}; > + > +/* > + * To handle an APLIC direct interrupts, we just read the CLAIMI register > + * which will return highest priority pending interrupt and clear the > + * pending bit of the interrupt. This process is repeated until CLAIMI > + * register return zero value. > + */ > +static void aplic_direct_handle_irq(struct irq_desc *desc) > +{ > + struct aplic_idc *idc = this_cpu_ptr(&aplic_idcs); > + struct irq_chip *chip = irq_desc_get_chip(desc); > + struct irq_domain *irqdomain = idc->direct->irqdomain; > + irq_hw_number_t hw_irq; > + int irq; > + > + chained_irq_enter(chip, desc); > + > + while ((hw_irq = readl(idc->regs + APLIC_IDC_CLAIMI))) { > + hw_irq = hw_irq >> APLIC_IDC_TOPI_ID_SHIFT; > + irq = irq_find_mapping(irqdomain, hw_irq); > + > + if (unlikely(irq <= 0)) > + dev_warn_ratelimited(idc->direct->priv.dev, > + "hw_irq %lu mapping not found\n", > + hw_irq); > + else > + generic_handle_irq(irq); > + } > + > + chained_irq_exit(chip, desc); > +} > + > +static void aplic_idc_set_delivery(struct aplic_idc *idc, bool en) > +{ > + u32 de = (en) ? APLIC_ENABLE_IDELIVERY : APLIC_DISABLE_IDELIVERY; > + u32 th = (en) ? APLIC_ENABLE_ITHRESHOLD : APLIC_DISABLE_ITHRESHOLD; > + > + /* Priority must be less than threshold for interrupt triggering */ > + writel(th, idc->regs + APLIC_IDC_ITHRESHOLD); > + > + /* Delivery must be set to 1 for interrupt triggering */ > + writel(de, idc->regs + APLIC_IDC_IDELIVERY); > +} > + > +static int aplic_direct_dying_cpu(unsigned int cpu) > +{ > + if (aplic_direct_parent_irq) > + disable_percpu_irq(aplic_direct_parent_irq); > + > + return 0; > +} > + > +static int aplic_direct_starting_cpu(unsigned int cpu) > +{ > + if (aplic_direct_parent_irq) > + enable_percpu_irq(aplic_direct_parent_irq, > + irq_get_trigger_type(aplic_direct_parent_irq)); > + > + return 0; > +} > + > +int aplic_direct_setup(struct device *dev, void __iomem *regs) > +{ > + int i, j, rc, cpu, setup_count = 0; > + struct fwnode_reference_args parent; > + struct aplic_direct *direct; > + struct aplic_priv *priv; > + struct irq_domain *domain; > + unsigned long hartid; > + struct aplic_idc *idc; > + u32 val; > + > + direct = kzalloc(sizeof(*direct), GFP_KERNEL); > + if (!direct) > + return -ENOMEM; > + priv = &direct->priv; > + > + rc = aplic_setup_priv(priv, dev, regs); > + if (rc) { > + dev_err(dev, "failed to create APLIC context\n"); > + kfree(direct); > + return rc; > + } > + > + /* Setup per-CPU IDC and target CPU mask */ > + for (i = 0; i < priv->nr_idcs; i++) { > + rc = fwnode_property_get_reference_args(dev->fwnode, > + "interrupts-extended", "#interrupt-cells", > + 0, i, &parent); > + if (rc) { > + dev_warn(dev, "parent irq for IDC%d not found\n", i); > + continue; > + } > + > + /* > + * Skip interrupts other than external interrupts for > + * current privilege level. > + */ > + if (parent.args[0] != RV_IRQ_EXT) > + continue; > + > + rc = riscv_get_intc_hartid(parent.fwnode, &hartid); > + if (rc) { > + dev_warn(dev, "invalid hartid for IDC%d\n", i); > + continue; > + } > + > + cpu = riscv_hartid_to_cpuid(hartid); > + if (cpu < 0) { > + dev_warn(dev, "invalid cpuid for IDC%d\n", i); > + continue; > + } > + > + cpumask_set_cpu(cpu, &direct->lmask); > + > + idc = per_cpu_ptr(&aplic_idcs, cpu); > + idc->hart_index = i; > + idc->regs = priv->regs + APLIC_IDC_BASE + i * APLIC_IDC_SIZE; > + idc->direct = direct; > + > + aplic_idc_set_delivery(idc, true); > + > + /* > + * Boot cpu might not have APLIC hart_index = 0 so check > + * and update target registers of all interrupts. > + */ > + if (cpu == smp_processor_id() && idc->hart_index) { > + val = idc->hart_index & APLIC_TARGET_HART_IDX_MASK; > + val <<= APLIC_TARGET_HART_IDX_SHIFT; > + val |= APLIC_DEFAULT_PRIORITY; > + for (j = 1; j <= priv->nr_irqs; j++) > + writel(val, priv->regs + APLIC_TARGET_BASE + > + (j - 1) * sizeof(u32)); > + } > + > + setup_count++; > + } > + > + /* Find parent domain and register chained handler */ > + domain = irq_find_matching_fwnode(riscv_get_intc_hwnode(), > + DOMAIN_BUS_ANY); > + if (!aplic_direct_parent_irq && domain) { > + aplic_direct_parent_irq = irq_create_mapping(domain, RV_IRQ_EXT); > + if (aplic_direct_parent_irq) { > + irq_set_chained_handler(aplic_direct_parent_irq, > + aplic_direct_handle_irq); > + > + /* > + * Setup CPUHP notifier to enable parent > + * interrupt on all CPUs > + */ > + cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, > + "irqchip/riscv/aplic:starting", > + aplic_direct_starting_cpu, > + aplic_direct_dying_cpu); > + } > + } > + > + /* Fail if we were not able to setup IDC for any CPU */ > + if (!setup_count) { > + kfree(direct); > + return -ENODEV; > + } > + > + /* Setup global config and interrupt delivery */ > + aplic_init_hw_global(priv, false); > + > + /* Create irq domain instance for the APLIC */ > + direct->irqdomain = irq_domain_create_linear(dev->fwnode, > + priv->nr_irqs + 1, > + &aplic_direct_irqdomain_ops, > + priv); > + if (!direct->irqdomain) { > + dev_err(dev, "failed to create direct irq domain\n"); > + kfree(direct); > + return -ENOMEM; > + } > + > + /* Advertise the interrupt controller */ > + dev_info(dev, "%d interrupts directly connected to %d CPUs\n", > + priv->nr_irqs, priv->nr_idcs); > + > + return 0; > +} > diff --git a/drivers/irqchip/irq-riscv-aplic-main.c b/drivers/irqchip/irq-riscv-aplic-main.c > new file mode 100644 > index 000000000000..d62a096774c4 > --- /dev/null > +++ b/drivers/irqchip/irq-riscv-aplic-main.c > @@ -0,0 +1,240 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2021 Western Digital Corporation or its affiliates. > + * Copyright (C) 2022 Ventana Micro Systems Inc. > + */ > + > +#include <linux/printk.h> > +#include <linux/module.h> > +#include <linux/platform_device.h> > +#include <linux/irqchip/riscv-aplic.h> > + > +#include "irq-riscv-aplic-main.h" > + > +void aplic_irq_unmask(struct irq_data *d) > +{ > + struct aplic_priv *priv = irq_data_get_irq_chip_data(d); > + > + writel(d->hwirq, priv->regs + APLIC_SETIENUM); > +} > + > +void aplic_irq_mask(struct irq_data *d) > +{ > + struct aplic_priv *priv = irq_data_get_irq_chip_data(d); > + > + writel(d->hwirq, priv->regs + APLIC_CLRIENUM); > +} > + > +int aplic_irq_set_type(struct irq_data *d, unsigned int type) > +{ > + u32 val = 0; > + void __iomem *sourcecfg; > + struct aplic_priv *priv = irq_data_get_irq_chip_data(d); > + > + switch (type) { > + case IRQ_TYPE_NONE: > + val = APLIC_SOURCECFG_SM_INACTIVE; > + break; > + case IRQ_TYPE_LEVEL_LOW: > + val = APLIC_SOURCECFG_SM_LEVEL_LOW; > + break; > + case IRQ_TYPE_LEVEL_HIGH: > + val = APLIC_SOURCECFG_SM_LEVEL_HIGH; > + break; > + case IRQ_TYPE_EDGE_FALLING: > + val = APLIC_SOURCECFG_SM_EDGE_FALL; > + break; > + case IRQ_TYPE_EDGE_RISING: > + val = APLIC_SOURCECFG_SM_EDGE_RISE; > + break; > + default: > + return -EINVAL; > + } > + > + sourcecfg = priv->regs + APLIC_SOURCECFG_BASE; > + sourcecfg += (d->hwirq - 1) * sizeof(u32); > + writel(val, sourcecfg); > + > + return 0; > +} > + > +int aplic_irqdomain_translate(struct irq_fwspec *fwspec, u32 gsi_base, > + unsigned long *hwirq, unsigned int *type) > +{ > + if (WARN_ON(fwspec->param_count < 2)) > + return -EINVAL; > + if (WARN_ON(!fwspec->param[0])) > + return -EINVAL; > + > + /* For DT, gsi_base is always zero. */ > + *hwirq = fwspec->param[0] - gsi_base; > + *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; > + > + WARN_ON(*type == IRQ_TYPE_NONE); > + > + return 0; > +} > + > +void aplic_init_hw_global(struct aplic_priv *priv, bool msi_mode) > +{ > + u32 val; > +#ifdef CONFIG_RISCV_M_MODE > + u32 valH; > + > + if (msi_mode) { > + val = priv->msicfg.base_ppn; > + valH = ((u64)priv->msicfg.base_ppn >> 32) & > + APLIC_xMSICFGADDRH_BAPPN_MASK; > + valH |= (priv->msicfg.lhxw & APLIC_xMSICFGADDRH_LHXW_MASK) > + << APLIC_xMSICFGADDRH_LHXW_SHIFT; > + valH |= (priv->msicfg.hhxw & APLIC_xMSICFGADDRH_HHXW_MASK) > + << APLIC_xMSICFGADDRH_HHXW_SHIFT; > + valH |= (priv->msicfg.lhxs & APLIC_xMSICFGADDRH_LHXS_MASK) > + << APLIC_xMSICFGADDRH_LHXS_SHIFT; > + valH |= (priv->msicfg.hhxs & APLIC_xMSICFGADDRH_HHXS_MASK) > + << APLIC_xMSICFGADDRH_HHXS_SHIFT; > + writel(val, priv->regs + APLIC_xMSICFGADDR); > + writel(valH, priv->regs + APLIC_xMSICFGADDRH); > + } > +#endif > + > + /* Setup APLIC domaincfg register */ > + val = readl(priv->regs + APLIC_DOMAINCFG); > + val |= APLIC_DOMAINCFG_IE; > + if (msi_mode) > + val |= APLIC_DOMAINCFG_DM; > + writel(val, priv->regs + APLIC_DOMAINCFG); > + if (readl(priv->regs + APLIC_DOMAINCFG) != val) > + dev_warn(priv->dev, "unable to write 0x%x in domaincfg\n", > + val); > +} > + > +static void aplic_init_hw_irqs(struct aplic_priv *priv) > +{ > + int i; > + > + /* Disable all interrupts */ > + for (i = 0; i <= priv->nr_irqs; i += 32) > + writel(-1U, priv->regs + APLIC_CLRIE_BASE + > + (i / 32) * sizeof(u32)); > + > + /* Set interrupt type and default priority for all interrupts */ > + for (i = 1; i <= priv->nr_irqs; i++) { > + writel(0, priv->regs + APLIC_SOURCECFG_BASE + > + (i - 1) * sizeof(u32)); > + writel(APLIC_DEFAULT_PRIORITY, > + priv->regs + APLIC_TARGET_BASE + > + (i - 1) * sizeof(u32)); > + } > + > + /* Clear APLIC domaincfg */ > + writel(0, priv->regs + APLIC_DOMAINCFG); > +} > + > +int aplic_setup_priv(struct aplic_priv *priv, struct device *dev, > + void __iomem *regs) > +{ > + struct fwnode_reference_args parent; > + int rc; > + > + /* Save device pointer and register base */ > + priv->dev = dev; > + priv->regs = regs; > + > + /* > + * Find out GSI base number > + * > + * Note: DT does not define "riscv,gsi-base" property so GSI > + * base is always zero for DT. > + */ > + rc = fwnode_property_read_u32_array(dev->fwnode, "riscv,gsi-base", > + &priv->gsi_base, 1); For DT, you can just initialize this to 0 without reading the property. > + if (rc) > + priv->gsi_base = 0; > + > + /* Find out number of interrupt sources */ > + rc = fwnode_property_read_u32_array(dev->fwnode, "riscv,num-sources", > + &priv->nr_irqs, 1); > + if (rc) { > + dev_err(dev, "failed to get number of interrupt sources\n"); > + return rc; > + } > + > + /* Setup initial state APLIC interrupts */ > + aplic_init_hw_irqs(priv); > + > + /* > + * Find out number of IDCs based on parent interrupts > + * > + * If "msi-parent" property is present then we ignore the > + * APLIC IDCs which forces the APLIC driver to use MSI mode. > + */ > + if (!fwnode_property_present(dev->fwnode, "msi-parent")) { > + while (!fwnode_property_get_reference_args(dev->fwnode, > + "interrupts-extended", "#interrupt-cells", > + 0, priv->nr_idcs, &parent)) > + priv->nr_idcs++; > + } > + Can this finding nr_idcs be done after aplic_init_hw_irqs() above? > + return 0; > +} > + > +static int aplic_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct resource *res; > + void __iomem *regs; > + int rc; > + > + /* Map the MMIO registers */ > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + if (!res) { > + dev_err(dev, "failed to get MMIO resource\n"); > + return -EINVAL; > + } > + regs = devm_ioremap(&pdev->dev, res->start, resource_size(res)); > + if (!regs) { > + dev_err(dev, "failed map MMIO registers\n"); > + return -ENOMEM; > + } > + > + /* > + * If msi-parent property is present then setup APLIC MSI mode > + * otherwise setup APLIC direct mode. > + */ > + if (fwnode_property_present(dev->fwnode, "msi-parent")) Can this check be based on nr_idcs instead of checking for msi-parent again? Thanks! Sunil > + rc = -ENODEV; > + else > + rc = aplic_direct_setup(dev, regs); > + if (rc) { > + dev_err(dev, "failed setup APLIC in %s mode\n", > + fwnode_property_present(dev->fwnode, "msi-parent") ? > + "MSI" : "direct"); > + return rc; > + } > + > + return 0; > +} > + > +static const struct of_device_id aplic_match[] = { > + { .compatible = "riscv,aplic" }, > + {} > +}; > + > +static struct platform_driver aplic_driver = { > + .driver = { > + .name = "riscv-aplic", > + .of_match_table = aplic_match, > + }, > + .probe = aplic_probe, > +}; > + > +static int __init aplic_init(void) > +{ > + /* > + * Register APLIC driver as early as possible so that APLIC > + * platform device is probed as soon as it is created. > + */ > + return platform_driver_register(&aplic_driver); > +} > +core_initcall(aplic_init); > diff --git a/drivers/irqchip/irq-riscv-aplic-main.h b/drivers/irqchip/irq-riscv-aplic-main.h > new file mode 100644 > index 000000000000..474a04229334 > --- /dev/null > +++ b/drivers/irqchip/irq-riscv-aplic-main.h > @@ -0,0 +1,45 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (C) 2021 Western Digital Corporation or its affiliates. > + * Copyright (C) 2022 Ventana Micro Systems Inc. > + */ > + > +#ifndef _IRQ_RISCV_APLIC_MAIN_H > +#define _IRQ_RISCV_APLIC_MAIN_H > + > +#include <linux/device.h> > +#include <linux/io.h> > +#include <linux/irq.h> > +#include <linux/irqdomain.h> > +#include <linux/fwnode.h> > + > +#define APLIC_DEFAULT_PRIORITY 1 > + > +struct aplic_msicfg { > + phys_addr_t base_ppn; > + u32 hhxs; > + u32 hhxw; > + u32 lhxs; > + u32 lhxw; > +}; > + > +struct aplic_priv { > + struct device *dev; > + u32 gsi_base; > + u32 nr_irqs; > + u32 nr_idcs; > + void __iomem *regs; > + struct aplic_msicfg msicfg; > +}; > + > +void aplic_irq_unmask(struct irq_data *d); > +void aplic_irq_mask(struct irq_data *d); > +int aplic_irq_set_type(struct irq_data *d, unsigned int type); > +int aplic_irqdomain_translate(struct irq_fwspec *fwspec, u32 gsi_base, > + unsigned long *hwirq, unsigned int *type); > +void aplic_init_hw_global(struct aplic_priv *priv, bool msi_mode); > +int aplic_setup_priv(struct aplic_priv *priv, struct device *dev, > + void __iomem *regs); > +int aplic_direct_setup(struct device *dev, void __iomem *regs); > + > +#endif > diff --git a/include/linux/irqchip/riscv-aplic.h b/include/linux/irqchip/riscv-aplic.h > new file mode 100644 > index 000000000000..97e198ea0109 > --- /dev/null > +++ b/include/linux/irqchip/riscv-aplic.h > @@ -0,0 +1,119 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (C) 2021 Western Digital Corporation or its affiliates. > + * Copyright (C) 2022 Ventana Micro Systems Inc. > + */ > +#ifndef __LINUX_IRQCHIP_RISCV_APLIC_H > +#define __LINUX_IRQCHIP_RISCV_APLIC_H > + > +#include <linux/bitops.h> > + > +#define APLIC_MAX_IDC BIT(14) > +#define APLIC_MAX_SOURCE 1024 > + > +#define APLIC_DOMAINCFG 0x0000 > +#define APLIC_DOMAINCFG_RDONLY 0x80000000 > +#define APLIC_DOMAINCFG_IE BIT(8) > +#define APLIC_DOMAINCFG_DM BIT(2) > +#define APLIC_DOMAINCFG_BE BIT(0) > + > +#define APLIC_SOURCECFG_BASE 0x0004 > +#define APLIC_SOURCECFG_D BIT(10) > +#define APLIC_SOURCECFG_CHILDIDX_MASK 0x000003ff > +#define APLIC_SOURCECFG_SM_MASK 0x00000007 > +#define APLIC_SOURCECFG_SM_INACTIVE 0x0 > +#define APLIC_SOURCECFG_SM_DETACH 0x1 > +#define APLIC_SOURCECFG_SM_EDGE_RISE 0x4 > +#define APLIC_SOURCECFG_SM_EDGE_FALL 0x5 > +#define APLIC_SOURCECFG_SM_LEVEL_HIGH 0x6 > +#define APLIC_SOURCECFG_SM_LEVEL_LOW 0x7 > + > +#define APLIC_MMSICFGADDR 0x1bc0 > +#define APLIC_MMSICFGADDRH 0x1bc4 > +#define APLIC_SMSICFGADDR 0x1bc8 > +#define APLIC_SMSICFGADDRH 0x1bcc > + > +#ifdef CONFIG_RISCV_M_MODE > +#define APLIC_xMSICFGADDR APLIC_MMSICFGADDR > +#define APLIC_xMSICFGADDRH APLIC_MMSICFGADDRH > +#else > +#define APLIC_xMSICFGADDR APLIC_SMSICFGADDR > +#define APLIC_xMSICFGADDRH APLIC_SMSICFGADDRH > +#endif > + > +#define APLIC_xMSICFGADDRH_L BIT(31) > +#define APLIC_xMSICFGADDRH_HHXS_MASK 0x1f > +#define APLIC_xMSICFGADDRH_HHXS_SHIFT 24 > +#define APLIC_xMSICFGADDRH_LHXS_MASK 0x7 > +#define APLIC_xMSICFGADDRH_LHXS_SHIFT 20 > +#define APLIC_xMSICFGADDRH_HHXW_MASK 0x7 > +#define APLIC_xMSICFGADDRH_HHXW_SHIFT 16 > +#define APLIC_xMSICFGADDRH_LHXW_MASK 0xf > +#define APLIC_xMSICFGADDRH_LHXW_SHIFT 12 > +#define APLIC_xMSICFGADDRH_BAPPN_MASK 0xfff > + > +#define APLIC_xMSICFGADDR_PPN_SHIFT 12 > + > +#define APLIC_xMSICFGADDR_PPN_HART(__lhxs) \ > + (BIT(__lhxs) - 1) > + > +#define APLIC_xMSICFGADDR_PPN_LHX_MASK(__lhxw) \ > + (BIT(__lhxw) - 1) > +#define APLIC_xMSICFGADDR_PPN_LHX_SHIFT(__lhxs) \ > + ((__lhxs)) > +#define APLIC_xMSICFGADDR_PPN_LHX(__lhxw, __lhxs) \ > + (APLIC_xMSICFGADDR_PPN_LHX_MASK(__lhxw) << \ > + APLIC_xMSICFGADDR_PPN_LHX_SHIFT(__lhxs)) > + > +#define APLIC_xMSICFGADDR_PPN_HHX_MASK(__hhxw) \ > + (BIT(__hhxw) - 1) > +#define APLIC_xMSICFGADDR_PPN_HHX_SHIFT(__hhxs) \ > + ((__hhxs) + APLIC_xMSICFGADDR_PPN_SHIFT) > +#define APLIC_xMSICFGADDR_PPN_HHX(__hhxw, __hhxs) \ > + (APLIC_xMSICFGADDR_PPN_HHX_MASK(__hhxw) << \ > + APLIC_xMSICFGADDR_PPN_HHX_SHIFT(__hhxs)) > + > +#define APLIC_IRQBITS_PER_REG 32 > + > +#define APLIC_SETIP_BASE 0x1c00 > +#define APLIC_SETIPNUM 0x1cdc > + > +#define APLIC_CLRIP_BASE 0x1d00 > +#define APLIC_CLRIPNUM 0x1ddc > + > +#define APLIC_SETIE_BASE 0x1e00 > +#define APLIC_SETIENUM 0x1edc > + > +#define APLIC_CLRIE_BASE 0x1f00 > +#define APLIC_CLRIENUM 0x1fdc > + > +#define APLIC_SETIPNUM_LE 0x2000 > +#define APLIC_SETIPNUM_BE 0x2004 > + > +#define APLIC_GENMSI 0x3000 > + > +#define APLIC_TARGET_BASE 0x3004 > +#define APLIC_TARGET_HART_IDX_SHIFT 18 > +#define APLIC_TARGET_HART_IDX_MASK 0x3fff > +#define APLIC_TARGET_GUEST_IDX_SHIFT 12 > +#define APLIC_TARGET_GUEST_IDX_MASK 0x3f > +#define APLIC_TARGET_IPRIO_MASK 0xff > +#define APLIC_TARGET_EIID_MASK 0x7ff > + > +#define APLIC_IDC_BASE 0x4000 > +#define APLIC_IDC_SIZE 32 > + > +#define APLIC_IDC_IDELIVERY 0x00 > + > +#define APLIC_IDC_IFORCE 0x04 > + > +#define APLIC_IDC_ITHRESHOLD 0x08 > + > +#define APLIC_IDC_TOPI 0x18 > +#define APLIC_IDC_TOPI_ID_SHIFT 16 > +#define APLIC_IDC_TOPI_ID_MASK 0x3ff > +#define APLIC_IDC_TOPI_PRIO_MASK 0xff > + > +#define APLIC_IDC_CLAIMI 0x1c > + > +#endif > -- > 2.34.1 >
On Mon, Sep 25, 2023 at 01:26:17PM +0530, Sunil V L wrote: > Hi Anup, > > On Tue, Sep 12, 2023 at 11:19:25PM +0530, Anup Patel wrote: > > The RISC-V advanced interrupt architecture (AIA) specification defines > > advanced platform-level interrupt controller (APLIC) which has two modes > > of operation: 1) Direct mode and 2) MSI mode. > > (For more details, refer https://github.com/riscv/riscv-aia) > > > > In APLIC direct-mode, wired interrupts are forwared to CPUs (or HARTs) > > as a local external interrupt. > > > > We add a platform irqchip driver for the RISC-V APLIC direct-mode to > > support RISC-V platforms having only wired interrupts. > > > > Signed-off-by: Anup Patel <apatel@ventanamicro.com> > > --- > > drivers/irqchip/Kconfig | 5 + > > drivers/irqchip/Makefile | 1 + > > drivers/irqchip/irq-riscv-aplic-direct.c | 326 +++++++++++++++++++++++ > > drivers/irqchip/irq-riscv-aplic-main.c | 240 +++++++++++++++++ > > drivers/irqchip/irq-riscv-aplic-main.h | 45 ++++ > > include/linux/irqchip/riscv-aplic.h | 119 +++++++++ > > 6 files changed, 736 insertions(+) > > create mode 100644 drivers/irqchip/irq-riscv-aplic-direct.c > > create mode 100644 drivers/irqchip/irq-riscv-aplic-main.c > > create mode 100644 drivers/irqchip/irq-riscv-aplic-main.h > > create mode 100644 include/linux/irqchip/riscv-aplic.h > > > > diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig > > index a6aad78076a0..44c455084d09 100644 > > --- a/drivers/irqchip/Kconfig > > +++ b/drivers/irqchip/Kconfig > > @@ -545,6 +545,11 @@ config SIFIVE_PLIC > > select IRQ_DOMAIN_HIERARCHY > > select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP > > > > +config RISCV_APLIC > > + bool > > + depends on RISCV > > + select IRQ_DOMAIN_HIERARCHY > > + > > config RISCV_IMSIC > > bool > > depends on RISCV > > diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile > > index abca445a3229..7f8289790ed8 100644 > > --- a/drivers/irqchip/Makefile > > +++ b/drivers/irqchip/Makefile > > @@ -95,6 +95,7 @@ obj-$(CONFIG_QCOM_MPM) += irq-qcom-mpm.o > > obj-$(CONFIG_CSKY_MPINTC) += irq-csky-mpintc.o > > obj-$(CONFIG_CSKY_APB_INTC) += irq-csky-apb-intc.o > > obj-$(CONFIG_RISCV_INTC) += irq-riscv-intc.o > > +obj-$(CONFIG_RISCV_APLIC) += irq-riscv-aplic-main.o irq-riscv-aplic-direct.o > > obj-$(CONFIG_RISCV_IMSIC) += irq-riscv-imsic-state.o irq-riscv-imsic-early.o irq-riscv-imsic-platform.o > > obj-$(CONFIG_SIFIVE_PLIC) += irq-sifive-plic.o > > obj-$(CONFIG_IMX_IRQSTEER) += irq-imx-irqsteer.o > > diff --git a/drivers/irqchip/irq-riscv-aplic-direct.c b/drivers/irqchip/irq-riscv-aplic-direct.c > > new file mode 100644 > > index 000000000000..e36d655a1490 > > --- /dev/null > > +++ b/drivers/irqchip/irq-riscv-aplic-direct.c > > @@ -0,0 +1,326 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Copyright (C) 2021 Western Digital Corporation or its affiliates. > > + * Copyright (C) 2022 Ventana Micro Systems Inc. > > + */ > > + > > +#include <linux/bitops.h> > > +#include <linux/cpu.h> > > +#include <linux/interrupt.h> > > +#include <linux/irqchip.h> > > +#include <linux/irqchip/chained_irq.h> > > +#include <linux/irqchip/riscv-aplic.h> > > +#include <linux/module.h> > > +#include <linux/of_address.h> > > +#include <linux/printk.h> > > +#include <linux/smp.h> > > + > > +#include "irq-riscv-aplic-main.h" > > + > > +#define APLIC_DISABLE_IDELIVERY 0 > > +#define APLIC_ENABLE_IDELIVERY 1 > > +#define APLIC_DISABLE_ITHRESHOLD 1 > > +#define APLIC_ENABLE_ITHRESHOLD 0 > > + > > +struct aplic_direct { > > + struct aplic_priv priv; > > + struct irq_domain *irqdomain; > > + struct cpumask lmask; > > +}; > > + > > +struct aplic_idc { > > + unsigned int hart_index; > > + void __iomem *regs; > > + struct aplic_direct *direct; > > +}; > > + > > +static unsigned int aplic_direct_parent_irq; > > +static DEFINE_PER_CPU(struct aplic_idc, aplic_idcs); > > + > > +static void aplic_direct_irq_eoi(struct irq_data *d) > > +{ > > + /* > > + * The fasteoi_handler requires irq_eoi() callback hence > > + * provide a dummy handler. > > + */ > > +} > > + > > +#ifdef CONFIG_SMP > > +static int aplic_direct_set_affinity(struct irq_data *d, > > + const struct cpumask *mask_val, bool force) > > +{ > > + struct aplic_priv *priv = irq_data_get_irq_chip_data(d); > > + struct aplic_direct *direct = > > + container_of(priv, struct aplic_direct, priv); > > + struct aplic_idc *idc; > > + unsigned int cpu, val; > > + struct cpumask amask; > > + void __iomem *target; > > + > > + cpumask_and(&amask, &direct->lmask, mask_val); > > + > > + if (force) > > + cpu = cpumask_first(&amask); > > + else > > + cpu = cpumask_any_and(&amask, cpu_online_mask); > > + > > + if (cpu >= nr_cpu_ids) > > + return -EINVAL; > > + > > + idc = per_cpu_ptr(&aplic_idcs, cpu); > > + target = priv->regs + APLIC_TARGET_BASE; > > + target += (d->hwirq - 1) * sizeof(u32); > > + val = idc->hart_index & APLIC_TARGET_HART_IDX_MASK; > > + val <<= APLIC_TARGET_HART_IDX_SHIFT; > > + val |= APLIC_DEFAULT_PRIORITY; > > + writel(val, target); > > + > > + irq_data_update_effective_affinity(d, cpumask_of(cpu)); > > + > > + return IRQ_SET_MASK_OK_DONE; > > +} > > +#endif > > + > > +static struct irq_chip aplic_direct_chip = { > > + .name = "APLIC-DIRECT", > > + .irq_mask = aplic_irq_mask, > > + .irq_unmask = aplic_irq_unmask, > > + .irq_set_type = aplic_irq_set_type, > > + .irq_eoi = aplic_direct_irq_eoi, > > +#ifdef CONFIG_SMP > > + .irq_set_affinity = aplic_direct_set_affinity, > > +#endif > > + .flags = IRQCHIP_SET_TYPE_MASKED | > > + IRQCHIP_SKIP_SET_WAKE | > > + IRQCHIP_MASK_ON_SUSPEND, > > +}; > > + > > +static int aplic_direct_irqdomain_translate(struct irq_domain *d, > > + struct irq_fwspec *fwspec, > > + unsigned long *hwirq, > > + unsigned int *type) > > +{ > > + struct aplic_priv *priv = d->host_data; > > + > > + return aplic_irqdomain_translate(fwspec, priv->gsi_base, > > + hwirq, type); > > +} > > + > > +static int aplic_direct_irqdomain_alloc(struct irq_domain *domain, > > + unsigned int virq, unsigned int nr_irqs, > > + void *arg) > > +{ > > + int i, ret; > > + unsigned int type; > > + irq_hw_number_t hwirq; > > + struct irq_fwspec *fwspec = arg; > > + struct aplic_priv *priv = domain->host_data; > > + struct aplic_direct *direct = > > + container_of(priv, struct aplic_direct, priv); > > + > > + ret = aplic_irqdomain_translate(fwspec, priv->gsi_base, > > + &hwirq, &type); > > + if (ret) > > + return ret; > > + > > + for (i = 0; i < nr_irqs; i++) { > > + irq_domain_set_info(domain, virq + i, hwirq + i, > > + &aplic_direct_chip, priv, > > + handle_fasteoi_irq, NULL, NULL); > > + irq_set_affinity(virq + i, &direct->lmask); > > + /* See the reason described in aplic_msi_irqdomain_alloc() */ > > + irq_set_status_flags(virq + i, IRQ_DISABLE_UNLAZY); > > + } > > + > > + return 0; > > +} > > + > > +static const struct irq_domain_ops aplic_direct_irqdomain_ops = { > > + .translate = aplic_direct_irqdomain_translate, > > + .alloc = aplic_direct_irqdomain_alloc, > > + .free = irq_domain_free_irqs_top, > > +}; > > + > > +/* > > + * To handle an APLIC direct interrupts, we just read the CLAIMI register > > + * which will return highest priority pending interrupt and clear the > > + * pending bit of the interrupt. This process is repeated until CLAIMI > > + * register return zero value. > > + */ > > +static void aplic_direct_handle_irq(struct irq_desc *desc) > > +{ > > + struct aplic_idc *idc = this_cpu_ptr(&aplic_idcs); > > + struct irq_chip *chip = irq_desc_get_chip(desc); > > + struct irq_domain *irqdomain = idc->direct->irqdomain; > > + irq_hw_number_t hw_irq; > > + int irq; > > + > > + chained_irq_enter(chip, desc); > > + > > + while ((hw_irq = readl(idc->regs + APLIC_IDC_CLAIMI))) { > > + hw_irq = hw_irq >> APLIC_IDC_TOPI_ID_SHIFT; > > + irq = irq_find_mapping(irqdomain, hw_irq); > > + > > + if (unlikely(irq <= 0)) > > + dev_warn_ratelimited(idc->direct->priv.dev, > > + "hw_irq %lu mapping not found\n", > > + hw_irq); > > + else > > + generic_handle_irq(irq); > > + } > > + > > + chained_irq_exit(chip, desc); > > +} > > + > > +static void aplic_idc_set_delivery(struct aplic_idc *idc, bool en) > > +{ > > + u32 de = (en) ? APLIC_ENABLE_IDELIVERY : APLIC_DISABLE_IDELIVERY; > > + u32 th = (en) ? APLIC_ENABLE_ITHRESHOLD : APLIC_DISABLE_ITHRESHOLD; > > + > > + /* Priority must be less than threshold for interrupt triggering */ > > + writel(th, idc->regs + APLIC_IDC_ITHRESHOLD); > > + > > + /* Delivery must be set to 1 for interrupt triggering */ > > + writel(de, idc->regs + APLIC_IDC_IDELIVERY); > > +} > > + > > +static int aplic_direct_dying_cpu(unsigned int cpu) > > +{ > > + if (aplic_direct_parent_irq) > > + disable_percpu_irq(aplic_direct_parent_irq); > > + > > + return 0; > > +} > > + > > +static int aplic_direct_starting_cpu(unsigned int cpu) > > +{ > > + if (aplic_direct_parent_irq) > > + enable_percpu_irq(aplic_direct_parent_irq, > > + irq_get_trigger_type(aplic_direct_parent_irq)); > > + > > + return 0; > > +} > > + > > +int aplic_direct_setup(struct device *dev, void __iomem *regs) > > +{ > > + int i, j, rc, cpu, setup_count = 0; > > + struct fwnode_reference_args parent; > > + struct aplic_direct *direct; > > + struct aplic_priv *priv; > > + struct irq_domain *domain; > > + unsigned long hartid; > > + struct aplic_idc *idc; > > + u32 val; > > + > > + direct = kzalloc(sizeof(*direct), GFP_KERNEL); > > + if (!direct) > > + return -ENOMEM; > > + priv = &direct->priv; > > + > > + rc = aplic_setup_priv(priv, dev, regs); > > + if (rc) { > > + dev_err(dev, "failed to create APLIC context\n"); > > + kfree(direct); > > + return rc; > > + } > > + > > + /* Setup per-CPU IDC and target CPU mask */ > > + for (i = 0; i < priv->nr_idcs; i++) { > > + rc = fwnode_property_get_reference_args(dev->fwnode, > > + "interrupts-extended", "#interrupt-cells", > > + 0, i, &parent); > > + if (rc) { > > + dev_warn(dev, "parent irq for IDC%d not found\n", i); > > + continue; > > + } > > + > > + /* > > + * Skip interrupts other than external interrupts for > > + * current privilege level. > > + */ > > + if (parent.args[0] != RV_IRQ_EXT) > > + continue; > > + > > + rc = riscv_get_intc_hartid(parent.fwnode, &hartid); > > + if (rc) { > > + dev_warn(dev, "invalid hartid for IDC%d\n", i); > > + continue; > > + } > > + > > + cpu = riscv_hartid_to_cpuid(hartid); > > + if (cpu < 0) { > > + dev_warn(dev, "invalid cpuid for IDC%d\n", i); > > + continue; > > + } > > + > > + cpumask_set_cpu(cpu, &direct->lmask); > > + > > + idc = per_cpu_ptr(&aplic_idcs, cpu); > > + idc->hart_index = i; > > + idc->regs = priv->regs + APLIC_IDC_BASE + i * APLIC_IDC_SIZE; > > + idc->direct = direct; > > + > > + aplic_idc_set_delivery(idc, true); > > + > > + /* > > + * Boot cpu might not have APLIC hart_index = 0 so check > > + * and update target registers of all interrupts. > > + */ > > + if (cpu == smp_processor_id() && idc->hart_index) { > > + val = idc->hart_index & APLIC_TARGET_HART_IDX_MASK; > > + val <<= APLIC_TARGET_HART_IDX_SHIFT; > > + val |= APLIC_DEFAULT_PRIORITY; > > + for (j = 1; j <= priv->nr_irqs; j++) > > + writel(val, priv->regs + APLIC_TARGET_BASE + > > + (j - 1) * sizeof(u32)); > > + } > > + > > + setup_count++; > > + } > > + > > + /* Find parent domain and register chained handler */ > > + domain = irq_find_matching_fwnode(riscv_get_intc_hwnode(), > > + DOMAIN_BUS_ANY); > > + if (!aplic_direct_parent_irq && domain) { > > + aplic_direct_parent_irq = irq_create_mapping(domain, RV_IRQ_EXT); > > + if (aplic_direct_parent_irq) { > > + irq_set_chained_handler(aplic_direct_parent_irq, > > + aplic_direct_handle_irq); > > + > > + /* > > + * Setup CPUHP notifier to enable parent > > + * interrupt on all CPUs > > + */ > > + cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, > > + "irqchip/riscv/aplic:starting", > > + aplic_direct_starting_cpu, > > + aplic_direct_dying_cpu); > > + } > > + } > > + > > + /* Fail if we were not able to setup IDC for any CPU */ > > + if (!setup_count) { > > + kfree(direct); > > + return -ENODEV; > > + } > > + > > + /* Setup global config and interrupt delivery */ > > + aplic_init_hw_global(priv, false); > > + > > + /* Create irq domain instance for the APLIC */ > > + direct->irqdomain = irq_domain_create_linear(dev->fwnode, > > + priv->nr_irqs + 1, > > + &aplic_direct_irqdomain_ops, > > + priv); > > + if (!direct->irqdomain) { > > + dev_err(dev, "failed to create direct irq domain\n"); > > + kfree(direct); > > + return -ENOMEM; > > + } > > + > > + /* Advertise the interrupt controller */ > > + dev_info(dev, "%d interrupts directly connected to %d CPUs\n", > > + priv->nr_irqs, priv->nr_idcs); > > + > > + return 0; > > +} > > diff --git a/drivers/irqchip/irq-riscv-aplic-main.c b/drivers/irqchip/irq-riscv-aplic-main.c > > new file mode 100644 > > index 000000000000..d62a096774c4 > > --- /dev/null > > +++ b/drivers/irqchip/irq-riscv-aplic-main.c > > @@ -0,0 +1,240 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Copyright (C) 2021 Western Digital Corporation or its affiliates. > > + * Copyright (C) 2022 Ventana Micro Systems Inc. > > + */ > > + > > +#include <linux/printk.h> > > +#include <linux/module.h> > > +#include <linux/platform_device.h> > > +#include <linux/irqchip/riscv-aplic.h> > > + > > +#include "irq-riscv-aplic-main.h" > > + > > +void aplic_irq_unmask(struct irq_data *d) > > +{ > > + struct aplic_priv *priv = irq_data_get_irq_chip_data(d); > > + > > + writel(d->hwirq, priv->regs + APLIC_SETIENUM); > > +} > > + > > +void aplic_irq_mask(struct irq_data *d) > > +{ > > + struct aplic_priv *priv = irq_data_get_irq_chip_data(d); > > + > > + writel(d->hwirq, priv->regs + APLIC_CLRIENUM); > > +} > > + > > +int aplic_irq_set_type(struct irq_data *d, unsigned int type) > > +{ > > + u32 val = 0; > > + void __iomem *sourcecfg; > > + struct aplic_priv *priv = irq_data_get_irq_chip_data(d); > > + > > + switch (type) { > > + case IRQ_TYPE_NONE: > > + val = APLIC_SOURCECFG_SM_INACTIVE; > > + break; > > + case IRQ_TYPE_LEVEL_LOW: > > + val = APLIC_SOURCECFG_SM_LEVEL_LOW; > > + break; > > + case IRQ_TYPE_LEVEL_HIGH: > > + val = APLIC_SOURCECFG_SM_LEVEL_HIGH; > > + break; > > + case IRQ_TYPE_EDGE_FALLING: > > + val = APLIC_SOURCECFG_SM_EDGE_FALL; > > + break; > > + case IRQ_TYPE_EDGE_RISING: > > + val = APLIC_SOURCECFG_SM_EDGE_RISE; > > + break; > > + default: > > + return -EINVAL; > > + } > > + > > + sourcecfg = priv->regs + APLIC_SOURCECFG_BASE; > > + sourcecfg += (d->hwirq - 1) * sizeof(u32); > > + writel(val, sourcecfg); > > + > > + return 0; > > +} > > + > > +int aplic_irqdomain_translate(struct irq_fwspec *fwspec, u32 gsi_base, > > + unsigned long *hwirq, unsigned int *type) > > +{ > > + if (WARN_ON(fwspec->param_count < 2)) > > + return -EINVAL; > > + if (WARN_ON(!fwspec->param[0])) > > + return -EINVAL; > > + > > + /* For DT, gsi_base is always zero. */ > > + *hwirq = fwspec->param[0] - gsi_base; > > + *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; > > + > > + WARN_ON(*type == IRQ_TYPE_NONE); > > + > > + return 0; > > +} > > + > > +void aplic_init_hw_global(struct aplic_priv *priv, bool msi_mode) > > +{ > > + u32 val; > > +#ifdef CONFIG_RISCV_M_MODE > > + u32 valH; > > + > > + if (msi_mode) { > > + val = priv->msicfg.base_ppn; > > + valH = ((u64)priv->msicfg.base_ppn >> 32) & > > + APLIC_xMSICFGADDRH_BAPPN_MASK; > > + valH |= (priv->msicfg.lhxw & APLIC_xMSICFGADDRH_LHXW_MASK) > > + << APLIC_xMSICFGADDRH_LHXW_SHIFT; > > + valH |= (priv->msicfg.hhxw & APLIC_xMSICFGADDRH_HHXW_MASK) > > + << APLIC_xMSICFGADDRH_HHXW_SHIFT; > > + valH |= (priv->msicfg.lhxs & APLIC_xMSICFGADDRH_LHXS_MASK) > > + << APLIC_xMSICFGADDRH_LHXS_SHIFT; > > + valH |= (priv->msicfg.hhxs & APLIC_xMSICFGADDRH_HHXS_MASK) > > + << APLIC_xMSICFGADDRH_HHXS_SHIFT; > > + writel(val, priv->regs + APLIC_xMSICFGADDR); > > + writel(valH, priv->regs + APLIC_xMSICFGADDRH); > > + } > > +#endif > > + > > + /* Setup APLIC domaincfg register */ > > + val = readl(priv->regs + APLIC_DOMAINCFG); > > + val |= APLIC_DOMAINCFG_IE; > > + if (msi_mode) > > + val |= APLIC_DOMAINCFG_DM; > > + writel(val, priv->regs + APLIC_DOMAINCFG); > > + if (readl(priv->regs + APLIC_DOMAINCFG) != val) > > + dev_warn(priv->dev, "unable to write 0x%x in domaincfg\n", > > + val); > > +} > > + > > +static void aplic_init_hw_irqs(struct aplic_priv *priv) > > +{ > > + int i; > > + > > + /* Disable all interrupts */ > > + for (i = 0; i <= priv->nr_irqs; i += 32) > > + writel(-1U, priv->regs + APLIC_CLRIE_BASE + > > + (i / 32) * sizeof(u32)); > > + > > + /* Set interrupt type and default priority for all interrupts */ > > + for (i = 1; i <= priv->nr_irqs; i++) { > > + writel(0, priv->regs + APLIC_SOURCECFG_BASE + > > + (i - 1) * sizeof(u32)); > > + writel(APLIC_DEFAULT_PRIORITY, > > + priv->regs + APLIC_TARGET_BASE + > > + (i - 1) * sizeof(u32)); > > + } > > + > > + /* Clear APLIC domaincfg */ > > + writel(0, priv->regs + APLIC_DOMAINCFG); > > +} > > + > > +int aplic_setup_priv(struct aplic_priv *priv, struct device *dev, > > + void __iomem *regs) > > +{ > > + struct fwnode_reference_args parent; > > + int rc; > > + > > + /* Save device pointer and register base */ > > + priv->dev = dev; > > + priv->regs = regs; > > + > > + /* > > + * Find out GSI base number > > + * > > + * Note: DT does not define "riscv,gsi-base" property so GSI > > + * base is always zero for DT. > > + */ > > + rc = fwnode_property_read_u32_array(dev->fwnode, "riscv,gsi-base", > > + &priv->gsi_base, 1); > For DT, you can just initialize this to 0 without reading the property. > > > + if (rc) > > + priv->gsi_base = 0; > > + > > + /* Find out number of interrupt sources */ > > + rc = fwnode_property_read_u32_array(dev->fwnode, "riscv,num-sources", > > + &priv->nr_irqs, 1); > > + if (rc) { > > + dev_err(dev, "failed to get number of interrupt sources\n"); > > + return rc; > > + } > > + > > + /* Setup initial state APLIC interrupts */ > > + aplic_init_hw_irqs(priv); > > + > > + /* > > + * Find out number of IDCs based on parent interrupts > > + * > > + * If "msi-parent" property is present then we ignore the > > + * APLIC IDCs which forces the APLIC driver to use MSI mode. > > + */ > > + if (!fwnode_property_present(dev->fwnode, "msi-parent")) { > > + while (!fwnode_property_get_reference_args(dev->fwnode, > > + "interrupts-extended", "#interrupt-cells", > > + 0, priv->nr_idcs, &parent)) > > + priv->nr_idcs++; > > + } > > + > Can this finding nr_idcs be done after aplic_init_hw_irqs() above? > Sorry, I meant prior to calling aplic_init_hw_irqs(). Thanks, Sunl
On 2023/9/13 1:49, Anup Patel wrote: > The Linux platform MSI support requires a platform MSI irqdomain so > let us add a platform irqchip driver for RISC-V IMSIC which provides > a base IRQ domain and platform MSI domain. This driver assumes that > the IMSIC state is already initialized by the IMSIC early driver. > > Signed-off-by: Anup Patel <apatel@ventanamicro.com> > --- > drivers/irqchip/Makefile | 2 +- > drivers/irqchip/irq-riscv-imsic-platform.c | 280 +++++++++++++++++++++ > 2 files changed, 281 insertions(+), 1 deletion(-) > create mode 100644 drivers/irqchip/irq-riscv-imsic-platform.c > > diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile > index d714724387ce..abca445a3229 100644 > --- a/drivers/irqchip/Makefile > +++ b/drivers/irqchip/Makefile > @@ -95,7 +95,7 @@ obj-$(CONFIG_QCOM_MPM) += irq-qcom-mpm.o > obj-$(CONFIG_CSKY_MPINTC) += irq-csky-mpintc.o > obj-$(CONFIG_CSKY_APB_INTC) += irq-csky-apb-intc.o > obj-$(CONFIG_RISCV_INTC) += irq-riscv-intc.o > -obj-$(CONFIG_RISCV_IMSIC) += irq-riscv-imsic-state.o irq-riscv-imsic-early.o > +obj-$(CONFIG_RISCV_IMSIC) += irq-riscv-imsic-state.o irq-riscv-imsic-early.o irq-riscv-imsic-platform.o > obj-$(CONFIG_SIFIVE_PLIC) += irq-sifive-plic.o > obj-$(CONFIG_IMX_IRQSTEER) += irq-imx-irqsteer.o > obj-$(CONFIG_IMX_INTMUX) += irq-imx-intmux.o > diff --git a/drivers/irqchip/irq-riscv-imsic-platform.c b/drivers/irqchip/irq-riscv-imsic-platform.c > new file mode 100644 > index 000000000000..b78f1b2ee3dc > --- /dev/null > +++ b/drivers/irqchip/irq-riscv-imsic-platform.c > @@ -0,0 +1,280 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2021 Western Digital Corporation or its affiliates. > + * Copyright (C) 2022 Ventana Micro Systems Inc. > + */ > + > +#include <linux/bitmap.h> > +#include <linux/cpu.h> > +#include <linux/interrupt.h> > +#include <linux/irq.h> > +#include <linux/irqchip.h> > +#include <linux/irqdomain.h> > +#include <linux/module.h> > +#include <linux/msi.h> > +#include <linux/platform_device.h> > +#include <linux/spinlock.h> > +#include <linux/smp.h> > + > +#include "irq-riscv-imsic-state.h" > + > +static int imsic_cpu_page_phys(unsigned int cpu, > + unsigned int guest_index, > + phys_addr_t *out_msi_pa) > +{ > + struct imsic_global_config *global; > + struct imsic_local_config *local; > + > + global = &imsic->global; > + local = per_cpu_ptr(global->local, cpu); > + > + if (BIT(global->guest_index_bits) <= guest_index) > + return -EINVAL; > + > + if (out_msi_pa) > + *out_msi_pa = local->msi_pa + > + (guest_index * IMSIC_MMIO_PAGE_SZ); > + > + return 0; > +} > + > +static int imsic_get_cpu(const struct cpumask *mask_val, bool force, > + unsigned int *out_target_cpu) > +{ > + unsigned int cpu; > + > + if (force) > + cpu = cpumask_first(mask_val); > + else > + cpu = cpumask_any_and(mask_val, cpu_online_mask); > + > + if (cpu >= nr_cpu_ids) > + return -EINVAL; > + > + if (out_target_cpu) > + *out_target_cpu = cpu; > + > + return 0; > +} > + > +static void imsic_irq_mask(struct irq_data *d) > +{ > + unsigned long flags; > + > + raw_spin_lock_irqsave(&imsic->ids_lock, flags); > + bitmap_clear(imsic->ids_enabled_bimap, d->hwirq, 1); > + __imsic_id_disable(d->hwirq); > + raw_spin_unlock_irqrestore(&imsic->ids_lock, flags); > + > + imsic_ids_remote_sync(); > +} > + > +static void imsic_irq_unmask(struct irq_data *d) > +{ > + unsigned long flags; > + > + raw_spin_lock_irqsave(&imsic->ids_lock, flags); > + bitmap_set(imsic->ids_enabled_bimap, d->hwirq, 1); > + __imsic_id_enable(d->hwirq); > + raw_spin_unlock_irqrestore(&imsic->ids_lock, flags); > + > + imsic_ids_remote_sync(); > +} > + > +static void imsic_irq_compose_msi_msg(struct irq_data *d, > + struct msi_msg *msg) > +{ > + phys_addr_t msi_addr; > + unsigned int cpu; > + int err; > + > + cpu = imsic_id_get_target(d->hwirq); > + if (WARN_ON(cpu == UINT_MAX)) > + return; > + > + err = imsic_cpu_page_phys(cpu, 0, &msi_addr); > + if (WARN_ON(err)) > + return; > + > + msg->address_hi = upper_32_bits(msi_addr); > + msg->address_lo = lower_32_bits(msi_addr); > + msg->data = d->hwirq; > +} > + > +#ifdef CONFIG_SMP > +static int imsic_irq_set_affinity(struct irq_data *d, > + const struct cpumask *mask_val, > + bool force) > +{ > + unsigned int target_cpu; > + int rc; > + > + rc = imsic_get_cpu(mask_val, force, &target_cpu); > + if (rc) > + return rc; > + > + imsic_id_set_target(d->hwirq, target_cpu); > + irq_data_update_effective_affinity(d, cpumask_of(target_cpu)); According to the “The RISC-V Advanced Interrupt Architecture Version 0.2-draft”,the "3.1 Interrupt files and interrupt identities" has following description. Thus the total number of MSI sources that can be separately distinguished within a system is potentially the product of the number of interrupt identities at a single interrupt file times the total number of interrupt files in the system, over all harts. In my opinion, the MSI interrupt number is a local interrupt number. However, when the above interrupt affinity is set, it is processed as a global interrupt number, which seems not comply with the above RISC-V specifications. > + > + return IRQ_SET_MASK_OK; > +} > +#endif > + > +static struct irq_chip imsic_irq_base_chip = { > + .name = "IMSIC-BASE", > + .irq_mask = imsic_irq_mask, > + .irq_unmask = imsic_irq_unmask, > +#ifdef CONFIG_SMP > + .irq_set_affinity = imsic_irq_set_affinity, > +#endif > + .irq_compose_msi_msg = imsic_irq_compose_msi_msg, > + .flags = IRQCHIP_SKIP_SET_WAKE | > + IRQCHIP_MASK_ON_SUSPEND, > +}; > + > +static int imsic_irq_domain_alloc(struct irq_domain *domain, > + unsigned int virq, > + unsigned int nr_irqs, > + void *args) > +{ > + int i, hwirq, err = 0; > + unsigned int cpu; > + > + err = imsic_get_cpu(cpu_online_mask, false, &cpu); > + if (err) > + return err; > + > + hwirq = imsic_ids_alloc(get_count_order(nr_irqs)); > + if (hwirq < 0) > + return hwirq; > + > + for (i = 0; i < nr_irqs; i++) { > + imsic_id_set_target(hwirq + i, cpu); > + irq_domain_set_info(domain, virq + i, hwirq + i, > + &imsic_irq_base_chip, imsic, > + handle_simple_irq, NULL, NULL); > + irq_set_noprobe(virq + i); > + irq_set_affinity(virq + i, cpu_online_mask); > + /* > + * IMSIC does not implement irq_disable() so Linux interrupt > + * subsystem will take a lazy approach for disabling an IMSIC > + * interrupt. This means IMSIC interrupts are left unmasked > + * upon system suspend and interrupts are not processed > + * immediately upon system wake up. To tackle this, we disable > + * the lazy approach for all IMSIC interrupts. > + */ > + irq_set_status_flags(virq + i, IRQ_DISABLE_UNLAZY); > + } > + > + return 0; > +} > + > +static void imsic_irq_domain_free(struct irq_domain *domain, > + unsigned int virq, > + unsigned int nr_irqs) > +{ > + struct irq_data *d = irq_domain_get_irq_data(domain, virq); > + > + imsic_ids_free(d->hwirq, get_count_order(nr_irqs)); > + irq_domain_free_irqs_parent(domain, virq, nr_irqs); > +} > + > +static const struct irq_domain_ops imsic_base_domain_ops = { > + .alloc = imsic_irq_domain_alloc, > + .free = imsic_irq_domain_free, > +}; > + > +static struct irq_chip imsic_plat_irq_chip = { > + .name = "IMSIC-PLAT", > +}; > + > +static struct msi_domain_ops imsic_plat_domain_ops = { > +}; > + > +static struct msi_domain_info imsic_plat_domain_info = { > + .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS), > + .ops = &imsic_plat_domain_ops, > + .chip = &imsic_plat_irq_chip, > +}; > + > +static int imsic_irq_domains_init(struct device *dev) > +{ > + /* Create Base IRQ domain */ > + imsic->base_domain = irq_domain_create_tree(dev->fwnode, > + &imsic_base_domain_ops, imsic); > + if (!imsic->base_domain) { > + dev_err(dev, "failed to create IMSIC base domain\n"); > + return -ENOMEM; > + } > + irq_domain_update_bus_token(imsic->base_domain, DOMAIN_BUS_NEXUS); > + > + /* Create Platform MSI domain */ > + imsic->plat_domain = platform_msi_create_irq_domain(dev->fwnode, > + &imsic_plat_domain_info, > + imsic->base_domain); > + if (!imsic->plat_domain) { > + dev_err(dev, "failed to create IMSIC platform domain\n"); > + irq_domain_remove(imsic->base_domain); > + return -ENOMEM; > + } > + > + return 0; > +} > + > +static int imsic_platform_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct imsic_global_config *global; > + int rc; > + > + if (!imsic) { > + dev_err(dev, "early driver not probed\n"); > + return -ENODEV; > + } > + > + if (imsic->base_domain) { > + dev_err(dev, "irq domain already created\n"); > + return -ENODEV; > + } > + > + global = &imsic->global; > + > + /* Initialize IRQ and MSI domains */ > + rc = imsic_irq_domains_init(dev); > + if (rc) { > + dev_err(dev, "failed to initialize IRQ and MSI domains\n"); > + return rc; > + } > + > + dev_info(dev, " hart-index-bits: %d, guest-index-bits: %d\n", > + global->hart_index_bits, global->guest_index_bits); > + dev_info(dev, " group-index-bits: %d, group-index-shift: %d\n", > + global->group_index_bits, global->group_index_shift); > + dev_info(dev, " mapped %d interrupts at base PPN %pa\n", > + global->nr_ids, &global->base_addr); > + > + return 0; > +} > + > +static const struct of_device_id imsic_platform_match[] = { > + { .compatible = "riscv,imsics" }, > + {} > +}; > + > +static struct platform_driver imsic_platform_driver = { > + .driver = { > + .name = "riscv-imsic", > + .of_match_table = imsic_platform_match, > + }, > + .probe = imsic_platform_probe, > +}; > + > +static int __init imsic_platform_init(void) > +{ > + /* > + * Register IMSIC driver as early as possible so that IMSIC > + * platform device is probed as soon as it is created. > + */ > + return platform_driver_register(&imsic_platform_driver); > +} > +core_initcall(imsic_platform_init);
On Mon, Sep 25, 2023 at 6:31 PM Ruan Jinjie <ruanjinjie@huawei.com> wrote: > > > > On 2023/9/13 1:49, Anup Patel wrote: > > The Linux platform MSI support requires a platform MSI irqdomain so > > let us add a platform irqchip driver for RISC-V IMSIC which provides > > a base IRQ domain and platform MSI domain. This driver assumes that > > the IMSIC state is already initialized by the IMSIC early driver. > > > > Signed-off-by: Anup Patel <apatel@ventanamicro.com> > > --- > > drivers/irqchip/Makefile | 2 +- > > drivers/irqchip/irq-riscv-imsic-platform.c | 280 +++++++++++++++++++++ > > 2 files changed, 281 insertions(+), 1 deletion(-) > > create mode 100644 drivers/irqchip/irq-riscv-imsic-platform.c > > > > diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile > > index d714724387ce..abca445a3229 100644 > > --- a/drivers/irqchip/Makefile > > +++ b/drivers/irqchip/Makefile > > @@ -95,7 +95,7 @@ obj-$(CONFIG_QCOM_MPM) += irq-qcom-mpm.o > > obj-$(CONFIG_CSKY_MPINTC) += irq-csky-mpintc.o > > obj-$(CONFIG_CSKY_APB_INTC) += irq-csky-apb-intc.o > > obj-$(CONFIG_RISCV_INTC) += irq-riscv-intc.o > > -obj-$(CONFIG_RISCV_IMSIC) += irq-riscv-imsic-state.o irq-riscv-imsic-early.o > > +obj-$(CONFIG_RISCV_IMSIC) += irq-riscv-imsic-state.o irq-riscv-imsic-early.o irq-riscv-imsic-platform.o > > obj-$(CONFIG_SIFIVE_PLIC) += irq-sifive-plic.o > > obj-$(CONFIG_IMX_IRQSTEER) += irq-imx-irqsteer.o > > obj-$(CONFIG_IMX_INTMUX) += irq-imx-intmux.o > > diff --git a/drivers/irqchip/irq-riscv-imsic-platform.c b/drivers/irqchip/irq-riscv-imsic-platform.c > > new file mode 100644 > > index 000000000000..b78f1b2ee3dc > > --- /dev/null > > +++ b/drivers/irqchip/irq-riscv-imsic-platform.c > > @@ -0,0 +1,280 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Copyright (C) 2021 Western Digital Corporation or its affiliates. > > + * Copyright (C) 2022 Ventana Micro Systems Inc. > > + */ > > + > > +#include <linux/bitmap.h> > > +#include <linux/cpu.h> > > +#include <linux/interrupt.h> > > +#include <linux/irq.h> > > +#include <linux/irqchip.h> > > +#include <linux/irqdomain.h> > > +#include <linux/module.h> > > +#include <linux/msi.h> > > +#include <linux/platform_device.h> > > +#include <linux/spinlock.h> > > +#include <linux/smp.h> > > + > > +#include "irq-riscv-imsic-state.h" > > + > > +static int imsic_cpu_page_phys(unsigned int cpu, > > + unsigned int guest_index, > > + phys_addr_t *out_msi_pa) > > +{ > > + struct imsic_global_config *global; > > + struct imsic_local_config *local; > > + > > + global = &imsic->global; > > + local = per_cpu_ptr(global->local, cpu); > > + > > + if (BIT(global->guest_index_bits) <= guest_index) > > + return -EINVAL; > > + > > + if (out_msi_pa) > > + *out_msi_pa = local->msi_pa + > > + (guest_index * IMSIC_MMIO_PAGE_SZ); > > + > > + return 0; > > +} > > + > > +static int imsic_get_cpu(const struct cpumask *mask_val, bool force, > > + unsigned int *out_target_cpu) > > +{ > > + unsigned int cpu; > > + > > + if (force) > > + cpu = cpumask_first(mask_val); > > + else > > + cpu = cpumask_any_and(mask_val, cpu_online_mask); > > + > > + if (cpu >= nr_cpu_ids) > > + return -EINVAL; > > + > > + if (out_target_cpu) > > + *out_target_cpu = cpu; > > + > > + return 0; > > +} > > + > > +static void imsic_irq_mask(struct irq_data *d) > > +{ > > + unsigned long flags; > > + > > + raw_spin_lock_irqsave(&imsic->ids_lock, flags); > > + bitmap_clear(imsic->ids_enabled_bimap, d->hwirq, 1); > > + __imsic_id_disable(d->hwirq); > > + raw_spin_unlock_irqrestore(&imsic->ids_lock, flags); > > + > > + imsic_ids_remote_sync(); > > +} > > + > > +static void imsic_irq_unmask(struct irq_data *d) > > +{ > > + unsigned long flags; > > + > > + raw_spin_lock_irqsave(&imsic->ids_lock, flags); > > + bitmap_set(imsic->ids_enabled_bimap, d->hwirq, 1); > > + __imsic_id_enable(d->hwirq); > > + raw_spin_unlock_irqrestore(&imsic->ids_lock, flags); > > + > > + imsic_ids_remote_sync(); > > +} > > + > > +static void imsic_irq_compose_msi_msg(struct irq_data *d, > > + struct msi_msg *msg) > > +{ > > + phys_addr_t msi_addr; > > + unsigned int cpu; > > + int err; > > + > > + cpu = imsic_id_get_target(d->hwirq); > > + if (WARN_ON(cpu == UINT_MAX)) > > + return; > > + > > + err = imsic_cpu_page_phys(cpu, 0, &msi_addr); > > + if (WARN_ON(err)) > > + return; > > + > > + msg->address_hi = upper_32_bits(msi_addr); > > + msg->address_lo = lower_32_bits(msi_addr); > > + msg->data = d->hwirq; > > +} > > + > > +#ifdef CONFIG_SMP > > +static int imsic_irq_set_affinity(struct irq_data *d, > > + const struct cpumask *mask_val, > > + bool force) > > +{ > > + unsigned int target_cpu; > > + int rc; > > + > > + rc = imsic_get_cpu(mask_val, force, &target_cpu); > > + if (rc) > > + return rc; > > + > > + imsic_id_set_target(d->hwirq, target_cpu); > > + irq_data_update_effective_affinity(d, cpumask_of(target_cpu)); > > According to the “The RISC-V Advanced Interrupt Architecture Version > 0.2-draft”,the "3.1 Interrupt files and interrupt identities" has > following description. > > Thus the total number of MSI sources that can be separately distinguished > within a system is potentially the product of the number of interrupt > identities at a single interrupt > file times the total number of interrupt files in the system, over all > harts. > > In my opinion, the MSI interrupt number is a local interrupt number. > However, when the above interrupt affinity is set, it is processed as a > global interrupt number, which seems not comply with the above RISC-V > specifications. Treating IMSIC minor interrupt identities as global instead of local is a design choice we made to integrate cleanly with Linux IRQ subsystem because otherwise MSI interrupts will be percpu interrupts and we can't steer device MSIs to different CPUs using set_irq_affinity(). Regards, Anup > > > + > > + return IRQ_SET_MASK_OK; > > +} > > +#endif > > + > > +static struct irq_chip imsic_irq_base_chip = { > > + .name = "IMSIC-BASE", > > + .irq_mask = imsic_irq_mask, > > + .irq_unmask = imsic_irq_unmask, > > +#ifdef CONFIG_SMP > > + .irq_set_affinity = imsic_irq_set_affinity, > > +#endif > > + .irq_compose_msi_msg = imsic_irq_compose_msi_msg, > > + .flags = IRQCHIP_SKIP_SET_WAKE | > > + IRQCHIP_MASK_ON_SUSPEND, > > +}; > > + > > +static int imsic_irq_domain_alloc(struct irq_domain *domain, > > + unsigned int virq, > > + unsigned int nr_irqs, > > + void *args) > > +{ > > + int i, hwirq, err = 0; > > + unsigned int cpu; > > + > > + err = imsic_get_cpu(cpu_online_mask, false, &cpu); > > + if (err) > > + return err; > > + > > + hwirq = imsic_ids_alloc(get_count_order(nr_irqs)); > > + if (hwirq < 0) > > + return hwirq; > > + > > + for (i = 0; i < nr_irqs; i++) { > > + imsic_id_set_target(hwirq + i, cpu); > > + irq_domain_set_info(domain, virq + i, hwirq + i, > > + &imsic_irq_base_chip, imsic, > > + handle_simple_irq, NULL, NULL); > > + irq_set_noprobe(virq + i); > > + irq_set_affinity(virq + i, cpu_online_mask); > > + /* > > + * IMSIC does not implement irq_disable() so Linux interrupt > > + * subsystem will take a lazy approach for disabling an IMSIC > > + * interrupt. This means IMSIC interrupts are left unmasked > > + * upon system suspend and interrupts are not processed > > + * immediately upon system wake up. To tackle this, we disable > > + * the lazy approach for all IMSIC interrupts. > > + */ > > + irq_set_status_flags(virq + i, IRQ_DISABLE_UNLAZY); > > + } > > + > > + return 0; > > +} > > + > > +static void imsic_irq_domain_free(struct irq_domain *domain, > > + unsigned int virq, > > + unsigned int nr_irqs) > > +{ > > + struct irq_data *d = irq_domain_get_irq_data(domain, virq); > > + > > + imsic_ids_free(d->hwirq, get_count_order(nr_irqs)); > > + irq_domain_free_irqs_parent(domain, virq, nr_irqs); > > +} > > + > > +static const struct irq_domain_ops imsic_base_domain_ops = { > > + .alloc = imsic_irq_domain_alloc, > > + .free = imsic_irq_domain_free, > > +}; > > + > > +static struct irq_chip imsic_plat_irq_chip = { > > + .name = "IMSIC-PLAT", > > +}; > > + > > +static struct msi_domain_ops imsic_plat_domain_ops = { > > +}; > > + > > +static struct msi_domain_info imsic_plat_domain_info = { > > + .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS), > > + .ops = &imsic_plat_domain_ops, > > + .chip = &imsic_plat_irq_chip, > > +}; > > + > > +static int imsic_irq_domains_init(struct device *dev) > > +{ > > + /* Create Base IRQ domain */ > > + imsic->base_domain = irq_domain_create_tree(dev->fwnode, > > + &imsic_base_domain_ops, imsic); > > + if (!imsic->base_domain) { > > + dev_err(dev, "failed to create IMSIC base domain\n"); > > + return -ENOMEM; > > + } > > + irq_domain_update_bus_token(imsic->base_domain, DOMAIN_BUS_NEXUS); > > + > > + /* Create Platform MSI domain */ > > + imsic->plat_domain = platform_msi_create_irq_domain(dev->fwnode, > > + &imsic_plat_domain_info, > > + imsic->base_domain); > > + if (!imsic->plat_domain) { > > + dev_err(dev, "failed to create IMSIC platform domain\n"); > > + irq_domain_remove(imsic->base_domain); > > + return -ENOMEM; > > + } > > + > > + return 0; > > +} > > + > > +static int imsic_platform_probe(struct platform_device *pdev) > > +{ > > + struct device *dev = &pdev->dev; > > + struct imsic_global_config *global; > > + int rc; > > + > > + if (!imsic) { > > + dev_err(dev, "early driver not probed\n"); > > + return -ENODEV; > > + } > > + > > + if (imsic->base_domain) { > > + dev_err(dev, "irq domain already created\n"); > > + return -ENODEV; > > + } > > + > > + global = &imsic->global; > > + > > + /* Initialize IRQ and MSI domains */ > > + rc = imsic_irq_domains_init(dev); > > + if (rc) { > > + dev_err(dev, "failed to initialize IRQ and MSI domains\n"); > > + return rc; > > + } > > + > > + dev_info(dev, " hart-index-bits: %d, guest-index-bits: %d\n", > > + global->hart_index_bits, global->guest_index_bits); > > + dev_info(dev, " group-index-bits: %d, group-index-shift: %d\n", > > + global->group_index_bits, global->group_index_shift); > > + dev_info(dev, " mapped %d interrupts at base PPN %pa\n", > > + global->nr_ids, &global->base_addr); > > + > > + return 0; > > +} > > + > > +static const struct of_device_id imsic_platform_match[] = { > > + { .compatible = "riscv,imsics" }, > > + {} > > +}; > > + > > +static struct platform_driver imsic_platform_driver = { > > + .driver = { > > + .name = "riscv-imsic", > > + .of_match_table = imsic_platform_match, > > + }, > > + .probe = imsic_platform_probe, > > +}; > > + > > +static int __init imsic_platform_init(void) > > +{ > > + /* > > + * Register IMSIC driver as early as possible so that IMSIC > > + * platform device is probed as soon as it is created. > > + */ > > + return platform_driver_register(&imsic_platform_driver); > > +} > > +core_initcall(imsic_platform_init);
On Mon, Sep 25, 2023 at 1:08 PM Sunil V L <sunilvl@ventanamicro.com> wrote: > > Hi Anup, > > On Tue, Sep 12, 2023 at 11:19:14PM +0530, Anup Patel wrote: > > We add a common riscv_get_intc_hartid() which help device drivers to > > get hartid of the HART associated with a INTC (i.e. local interrupt > > controller) fwnode. This new function is more generic compared to > > the existing riscv_of_parent_hartid() function hence we also replace > > use of riscv_of_parent_hartid() with riscv_get_intc_hartid(). > > > > Signed-off-by: Anup Patel <apatel@ventanamicro.com> > > --- > > arch/riscv/include/asm/processor.h | 4 +++- > > arch/riscv/kernel/cpu.c | 13 ++++++++++++- > > drivers/irqchip/irq-riscv-intc.c | 2 +- > > drivers/irqchip/irq-sifive-plic.c | 3 ++- > > 4 files changed, 18 insertions(+), 4 deletions(-) > > > > diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h > > index 3e23e1786d05..3ce64b3bea4e 100644 > > --- a/arch/riscv/include/asm/processor.h > > +++ b/arch/riscv/include/asm/processor.h > > @@ -119,7 +119,9 @@ static inline void wait_for_interrupt(void) > > struct device_node; > > int riscv_of_processor_hartid(struct device_node *node, unsigned long *hartid); > > int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *hartid); > > -int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid); > > + > > +struct fwnode_handle; > > +int riscv_get_intc_hartid(struct fwnode_handle *node, unsigned long *hartid); > > > > extern void riscv_fill_hwcap(void); > > extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src); > > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > > index 157ace8b262c..ee583eac3c5b 100644 > > --- a/arch/riscv/kernel/cpu.c > > +++ b/arch/riscv/kernel/cpu.c > > @@ -123,7 +123,8 @@ int __init riscv_early_of_processor_hartid(struct device_node *node, unsigned lo > > * To achieve this, we walk up the DT tree until we find an active > > * RISC-V core (HART) node and extract the cpuid from it. > > */ > > -int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid) > > +static int riscv_of_parent_hartid(struct device_node *node, > > + unsigned long *hartid) > > { > > for (; node; node = node->parent) { > > if (of_device_is_compatible(node, "riscv")) { > > @@ -139,6 +140,16 @@ int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid) > > return -1; > > } > > > > +/* Find hart ID of the INTC fwnode. */ > > +int riscv_get_intc_hartid(struct fwnode_handle *node, unsigned long *hartid) > > +{ > > + /* Extend this function ACPI in the future. */ > > As per Marc's feedback, we can't use swnode for ACPI irchips. So, there > is no need to create this wrapper function and this patch can be > dropped. Okay, I will drop this patch. Regards, Anup > > Thanks, > Sunil > > > + if (!is_of_node(node)) > > + return -ENODEV; > > + > > + return riscv_of_parent_hartid(to_of_node(node), hartid); > > +} > > + > > DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); > > > > unsigned long riscv_cached_mvendorid(unsigned int cpu_id) > > diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c > > index 4adeee1bc391..65f4a2afb381 100644 > > --- a/drivers/irqchip/irq-riscv-intc.c > > +++ b/drivers/irqchip/irq-riscv-intc.c > > @@ -143,7 +143,7 @@ static int __init riscv_intc_init(struct device_node *node, > > int rc; > > unsigned long hartid; > > > > - rc = riscv_of_parent_hartid(node, &hartid); > > + rc = riscv_get_intc_hartid(of_fwnode_handle(node), &hartid); > > if (rc < 0) { > > pr_warn("unable to find hart id for %pOF\n", node); > > return 0; > > diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c > > index e1484905b7bd..56b0544b1f27 100644 > > --- a/drivers/irqchip/irq-sifive-plic.c > > +++ b/drivers/irqchip/irq-sifive-plic.c > > @@ -477,7 +477,8 @@ static int __init __plic_init(struct device_node *node, > > continue; > > } > > > > - error = riscv_of_parent_hartid(parent.np, &hartid); > > + error = riscv_get_intc_hartid(of_fwnode_handle(parent.np), > > + &hartid); > > if (error < 0) { > > pr_warn("failed to parse hart ID for context %d.\n", i); > > continue; > > -- > > 2.34.1 > >
On Mon, Sep 25, 2023 at 1:19 PM Sunil V L <sunilvl@ventanamicro.com> wrote: > > Hi Anup, > > On Tue, Sep 12, 2023 at 11:19:21PM +0530, Anup Patel wrote: > > The RISC-V advanced interrupt architecture (AIA) specification > > defines a new MSI controller called incoming message signalled > > interrupt controller (IMSIC) which manages MSI on per-HART (or > > per-CPU) basis. It also supports IPIs as software injected MSIs. > > (For more details refer https://github.com/riscv/riscv-aia) > > > > Let us add an early irqchip driver for RISC-V IMSIC which sets > > up the IMSIC state and provide IPIs. > > > > Signed-off-by: Anup Patel <apatel@ventanamicro.com> > > --- > > drivers/irqchip/Kconfig | 7 +- > > drivers/irqchip/Makefile | 1 + > > drivers/irqchip/irq-riscv-imsic-early.c | 258 ++++++++++++ > > drivers/irqchip/irq-riscv-imsic-state.c | 523 ++++++++++++++++++++++++ > > drivers/irqchip/irq-riscv-imsic-state.h | 66 +++ > > include/linux/irqchip/riscv-imsic.h | 86 ++++ > > 6 files changed, 940 insertions(+), 1 deletion(-) > > create mode 100644 drivers/irqchip/irq-riscv-imsic-early.c > > create mode 100644 drivers/irqchip/irq-riscv-imsic-state.c > > create mode 100644 drivers/irqchip/irq-riscv-imsic-state.h > > create mode 100644 include/linux/irqchip/riscv-imsic.h > > > > diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig > > index f7149d0f3d45..ee99aacbefcc 100644 > > --- a/drivers/irqchip/Kconfig > > +++ b/drivers/irqchip/Kconfig > > @@ -30,7 +30,6 @@ config ARM_GIC_V2M > > > > config GIC_NON_BANKED > > bool > > - > > config ARM_GIC_V3 > > bool > > select IRQ_DOMAIN_HIERARCHY > > @@ -546,6 +545,12 @@ config SIFIVE_PLIC > > select IRQ_DOMAIN_HIERARCHY > > select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP > > > > +config RISCV_IMSIC > > + bool > > + depends on RISCV > > + select IRQ_DOMAIN_HIERARCHY > > + select GENERIC_MSI_IRQ > > + > > config EXYNOS_IRQ_COMBINER > > bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST > > depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST > > diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile > > index ffd945fe71aa..d714724387ce 100644 > > --- a/drivers/irqchip/Makefile > > +++ b/drivers/irqchip/Makefile > > @@ -95,6 +95,7 @@ obj-$(CONFIG_QCOM_MPM) += irq-qcom-mpm.o > > obj-$(CONFIG_CSKY_MPINTC) += irq-csky-mpintc.o > > obj-$(CONFIG_CSKY_APB_INTC) += irq-csky-apb-intc.o > > obj-$(CONFIG_RISCV_INTC) += irq-riscv-intc.o > > +obj-$(CONFIG_RISCV_IMSIC) += irq-riscv-imsic-state.o irq-riscv-imsic-early.o > > obj-$(CONFIG_SIFIVE_PLIC) += irq-sifive-plic.o > > obj-$(CONFIG_IMX_IRQSTEER) += irq-imx-irqsteer.o > > obj-$(CONFIG_IMX_INTMUX) += irq-imx-intmux.o > > diff --git a/drivers/irqchip/irq-riscv-imsic-early.c b/drivers/irqchip/irq-riscv-imsic-early.c > > new file mode 100644 > > index 000000000000..1de89ce1ec2f > > --- /dev/null > > +++ b/drivers/irqchip/irq-riscv-imsic-early.c > > @@ -0,0 +1,258 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Copyright (C) 2021 Western Digital Corporation or its affiliates. > > + * Copyright (C) 2022 Ventana Micro Systems Inc. > > + */ > > + > > +#define pr_fmt(fmt) "riscv-imsic: " fmt > > +#include <linux/cpu.h> > > +#include <linux/interrupt.h> > > +#include <linux/io.h> > > +#include <linux/irq.h> > > +#include <linux/irqchip.h> > > +#include <linux/irqchip/chained_irq.h> > > +#include <linux/module.h> > > +#include <linux/spinlock.h> > > +#include <linux/smp.h> > > + > > +#include "irq-riscv-imsic-state.h" > > + > > +/* > > + * The IMSIC driver uses 1 IPI for ID synchronization and > > + * arch/riscv/kernel/smp.c require 6 IPIs so we fix the > > + * total number of IPIs to 8. > > + */ > > +#define IMSIC_NR_IPI 8 > > + > > +static int imsic_parent_irq; > > + > > +#ifdef CONFIG_SMP > > +static irqreturn_t imsic_ids_sync_handler(int irq, void *data) > > +{ > > + imsic_ids_local_sync(); > > + return IRQ_HANDLED; > > +} > > + > > +void imsic_ids_remote_sync(void) > > +{ > > + struct cpumask amask; > > + > > + /* > > + * We simply inject ID synchronization IPI to all target CPUs > > + * except current CPU. The ipi_send_mask() implementation of > > + * IPI mux will inject ID synchronization IPI only for CPUs > > + * that have enabled it so offline CPUs won't receive IPI. > > + * An offline CPU will unconditionally synchronize IDs through > > + * imsic_starting_cpu() when the CPU is brought up. > > + */ > > + cpumask_andnot(&amask, cpu_online_mask, cpumask_of(smp_processor_id())); > > + __ipi_send_mask(imsic->ipi_lsync_desc, &amask); > > +} > > + > > +static void imsic_ipi_send(unsigned int cpu) > > +{ > > + struct imsic_local_config *local = > > + per_cpu_ptr(imsic->global.local, cpu); > > + > > + writel(imsic->ipi_id, local->msi_va); > > +} > > + > > +static void imsic_ipi_starting_cpu(void) > > +{ > > + /* Enable IPIs for current CPU. */ > > + __imsic_id_enable(imsic->ipi_id); > > + > > + /* Enable virtual IPI used for IMSIC ID synchronization */ > > + enable_percpu_irq(imsic->ipi_virq, 0); > > +} > > + > > +static void imsic_ipi_dying_cpu(void) > > +{ > > + /* > > + * Disable virtual IPI used for IMSIC ID synchronization so > > + * that we don't receive ID synchronization requests. > > + */ > > + disable_percpu_irq(imsic->ipi_virq); > > +} > > + > > +static int __init imsic_ipi_domain_init(void) > > +{ > > + int virq; > > + > > + /* Allocate interrupt identity for IPIs */ > > + virq = imsic_ids_alloc(get_count_order(1)); > > + if (virq < 0) > > + return virq; > > + imsic->ipi_id = virq; > > + > > + /* Create IMSIC IPI multiplexing */ > > + virq = ipi_mux_create(IMSIC_NR_IPI, imsic_ipi_send); > > + if (virq <= 0) { > > + imsic_ids_free(imsic->ipi_id, get_count_order(1)); > > + return (virq < 0) ? virq : -ENOMEM; > > + } > > + imsic->ipi_virq = virq; > > + > > + /* First vIRQ is used for IMSIC ID synchronization */ > > + virq = request_percpu_irq(imsic->ipi_virq, imsic_ids_sync_handler, > > + "riscv-imsic-lsync", imsic->global.local); > > + if (virq) { > > + imsic_ids_free(imsic->ipi_id, get_count_order(1)); > > + return virq; > > + } > > + irq_set_status_flags(imsic->ipi_virq, IRQ_HIDDEN); > > + imsic->ipi_lsync_desc = irq_to_desc(imsic->ipi_virq); > > + > > + /* Set vIRQ range */ > > + riscv_ipi_set_virq_range(imsic->ipi_virq + 1, IMSIC_NR_IPI - 1, true); > > + > > + /* Announce that IMSIC is providing IPIs */ > > + pr_info("%pfwP: providing IPIs using interrupt %d\n", > > + imsic->fwnode, imsic->ipi_id); > > + > > + return 0; > > +} > > +#else > > +static void imsic_ipi_starting_cpu(void) > > +{ > > +} > > + > > +static void imsic_ipi_dying_cpu(void) > > +{ > > +} > > + > > +static int __init imsic_ipi_domain_init(void) > > +{ > > + /* Clear the IPI id because we are not using IPIs */ > > + imsic->ipi_id = 0; > > + return 0; > > +} > > +#endif > > + > > +/* > > + * To handle an interrupt, we read the TOPEI CSR and write zero in one > > + * instruction. If TOPEI CSR is non-zero then we translate TOPEI.ID to > > + * Linux interrupt number and let Linux IRQ subsystem handle it. > > + */ > > +static void imsic_handle_irq(struct irq_desc *desc) > > +{ > > + struct irq_chip *chip = irq_desc_get_chip(desc); > > + irq_hw_number_t hwirq; > > + int err; > > + > > + chained_irq_enter(chip, desc); > > + > > + while ((hwirq = csr_swap(CSR_TOPEI, 0))) { > > + hwirq = hwirq >> TOPEI_ID_SHIFT; > > + > > + if (hwirq == imsic->ipi_id) { > > +#ifdef CONFIG_SMP > > + ipi_mux_process(); > > +#endif > > + continue; > > + } > > + > > + if (unlikely(!imsic->base_domain)) > > + continue; > > + > > + err = generic_handle_domain_irq(imsic->base_domain, hwirq); > > + if (unlikely(err)) > > + pr_warn_ratelimited( > > + "hwirq %lu mapping not found\n", hwirq); > > + } > > + > > + chained_irq_exit(chip, desc); > > +} > > + > > +static int imsic_starting_cpu(unsigned int cpu) > > +{ > > + /* Enable per-CPU parent interrupt */ > > + enable_percpu_irq(imsic_parent_irq, > > + irq_get_trigger_type(imsic_parent_irq)); > > + > > + /* Setup IPIs */ > > + imsic_ipi_starting_cpu(); > > + > > + /* > > + * Interrupts identities might have been enabled/disabled while > > + * this CPU was not running so sync-up local enable/disable state. > > + */ > > + imsic_ids_local_sync(); > > + > > + /* Enable local interrupt delivery */ > > + imsic_ids_local_delivery(true); > > + > > + return 0; > > +} > > + > > +static int imsic_dying_cpu(unsigned int cpu) > > +{ > > + /* Cleanup IPIs */ > > + imsic_ipi_dying_cpu(); > > + > > + return 0; > > +} > > + > > +static int __init imsic_early_probe(struct fwnode_handle *fwnode) > > Can this imsic_early_probe() take an additional pointer as parameter? > This parameter can be NULL for DT and we can use to pass the MADT > structure in case of ACPI since fwnode in ACPI will not have any > properties. The parameter needs to be passed to imsic_setup_state() > also. Instead, I am thinking of moving the imsic_setup_state() call to imsic_early_dt_init() so that we can directly pass extra parameters from imsic_early_dt_init(). > > > +{ > > + int rc; > > + struct irq_domain *domain; > > + > > + /* Setup IMSIC state */ > > + rc = imsic_setup_state(fwnode); > > + if (rc) { > > + pr_err("%pfwP: failed to setup state (error %d)\n", > > + fwnode, rc); > > + return rc; > > + } > > + > > + /* Find parent domain and register chained handler */ > > + domain = irq_find_matching_fwnode(riscv_get_intc_hwnode(), > > + DOMAIN_BUS_ANY); > > + if (!domain) { > > + pr_err("%pfwP: Failed to find INTC domain\n", fwnode); > > + return -ENOENT; > > + } > > + imsic_parent_irq = irq_create_mapping(domain, RV_IRQ_EXT); > > + if (!imsic_parent_irq) { > > + pr_err("%pfwP: Failed to create INTC mapping\n", fwnode); > > + return -ENOENT; > > + } > > + irq_set_chained_handler(imsic_parent_irq, imsic_handle_irq); > > + > > + /* Initialize IPI domain */ > > + rc = imsic_ipi_domain_init(); > > + if (rc) { > > + pr_err("%pfwP: Failed to initialize IPI domain\n", fwnode); > > + return rc; > > + } > > + > > + /* > > + * Setup cpuhp state (must be done after setting imsic_parent_irq) > > + * > > + * Don't disable per-CPU IMSIC file when CPU goes offline > > + * because this affects IPI and the masking/unmasking of > > + * virtual IPIs is done via generic IPI-Mux > > + */ > > + cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, > > + "irqchip/riscv/imsic:starting", > > + imsic_starting_cpu, imsic_dying_cpu); > > + > > + return 0; > > +} > > + > > +static int __init imsic_early_dt_init(struct device_node *node, > > + struct device_node *parent) > > +{ > > + int rc; > > + > > + /* Do early setup of IMSIC state and IPIs */ > > + rc = imsic_early_probe(&node->fwnode); > > + if (rc) > > + return rc; > > + > > + /* Ensure that OF platform device gets probed */ > > + of_node_clear_flag(node, OF_POPULATED); > > + return 0; > > +} > > +IRQCHIP_DECLARE(riscv_imsic, "riscv,imsics", imsic_early_dt_init); > > diff --git a/drivers/irqchip/irq-riscv-imsic-state.c b/drivers/irqchip/irq-riscv-imsic-state.c > > new file mode 100644 > > index 000000000000..412b5b919dcc > > --- /dev/null > > +++ b/drivers/irqchip/irq-riscv-imsic-state.c > > @@ -0,0 +1,523 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Copyright (C) 2021 Western Digital Corporation or its affiliates. > > + * Copyright (C) 2022 Ventana Micro Systems Inc. > > + */ > > + > > +#define pr_fmt(fmt) "riscv-imsic: " fmt > > +#include <linux/bitmap.h> > > +#include <linux/module.h> > > +#include <linux/of_address.h> > > +#include <linux/spinlock.h> > > +#include <linux/smp.h> > > +#include <asm/hwcap.h> > > + > > +#include "irq-riscv-imsic-state.h" > > + > > +#define IMSIC_DISABLE_EIDELIVERY 0 > > +#define IMSIC_ENABLE_EIDELIVERY 1 > > +#define IMSIC_DISABLE_EITHRESHOLD 1 > > +#define IMSIC_ENABLE_EITHRESHOLD 0 > > + > > +#define imsic_csr_write(__c, __v) \ > > +do { \ > > + csr_write(CSR_ISELECT, __c); \ > > + csr_write(CSR_IREG, __v); \ > > +} while (0) > > + > > +#define imsic_csr_read(__c) \ > > +({ \ > > + unsigned long __v; \ > > + csr_write(CSR_ISELECT, __c); \ > > + __v = csr_read(CSR_IREG); \ > > + __v; \ > > +}) > > + > > +#define imsic_csr_set(__c, __v) \ > > +do { \ > > + csr_write(CSR_ISELECT, __c); \ > > + csr_set(CSR_IREG, __v); \ > > +} while (0) > > + > > +#define imsic_csr_clear(__c, __v) \ > > +do { \ > > + csr_write(CSR_ISELECT, __c); \ > > + csr_clear(CSR_IREG, __v); \ > > +} while (0) > > + > > +struct imsic_priv *imsic; > > + > > +const struct imsic_global_config *imsic_get_global_config(void) > > +{ > > + return (imsic) ? &imsic->global : NULL; > > +} > > +EXPORT_SYMBOL_GPL(imsic_get_global_config); > > + > > +void __imsic_eix_update(unsigned long base_id, > > + unsigned long num_id, bool pend, bool val) > > +{ > > + unsigned long i, isel, ireg; > > + unsigned long id = base_id, last_id = base_id + num_id; > > + > > + while (id < last_id) { > > + isel = id / BITS_PER_LONG; > > + isel *= BITS_PER_LONG / IMSIC_EIPx_BITS; > > + isel += (pend) ? IMSIC_EIP0 : IMSIC_EIE0; > > + > > + ireg = 0; > > + for (i = id & (__riscv_xlen - 1); > > + (id < last_id) && (i < __riscv_xlen); i++) { > > + ireg |= BIT(i); > > + id++; > > + } > > + > > + /* > > + * The IMSIC EIEx and EIPx registers are indirectly > > + * accessed via using ISELECT and IREG CSRs so we > > + * need to access these CSRs without getting preempted. > > + * > > + * All existing users of this function call this > > + * function with local IRQs disabled so we don't > > + * need to do anything special here. > > + */ > > + if (val) > > + imsic_csr_set(isel, ireg); > > + else > > + imsic_csr_clear(isel, ireg); > > + } > > +} > > + > > +void imsic_id_set_target(unsigned int id, unsigned int target_cpu) > > +{ > > + unsigned long flags; > > + > > + raw_spin_lock_irqsave(&imsic->ids_lock, flags); > > + imsic->ids_target_cpu[id] = target_cpu; > > + raw_spin_unlock_irqrestore(&imsic->ids_lock, flags); > > +} > > + > > +unsigned int imsic_id_get_target(unsigned int id) > > +{ > > + unsigned int ret; > > + unsigned long flags; > > + > > + raw_spin_lock_irqsave(&imsic->ids_lock, flags); > > + ret = imsic->ids_target_cpu[id]; > > + raw_spin_unlock_irqrestore(&imsic->ids_lock, flags); > > + > > + return ret; > > +} > > + > > +void imsic_ids_local_sync(void) > > +{ > > + int i; > > + unsigned long flags; > > + > > + raw_spin_lock_irqsave(&imsic->ids_lock, flags); > > + for (i = 1; i <= imsic->global.nr_ids; i++) { > > + if (imsic->ipi_id == i) > > + continue; > > + > > + if (test_bit(i, imsic->ids_enabled_bimap)) > > + __imsic_id_enable(i); > > + else > > + __imsic_id_disable(i); > > + } > > + raw_spin_unlock_irqrestore(&imsic->ids_lock, flags); > > +} > > + > > +void imsic_ids_local_delivery(bool enable) > > +{ > > + if (enable) { > > + imsic_csr_write(IMSIC_EITHRESHOLD, IMSIC_ENABLE_EITHRESHOLD); > > + imsic_csr_write(IMSIC_EIDELIVERY, IMSIC_ENABLE_EIDELIVERY); > > + } else { > > + imsic_csr_write(IMSIC_EIDELIVERY, IMSIC_DISABLE_EIDELIVERY); > > + imsic_csr_write(IMSIC_EITHRESHOLD, IMSIC_DISABLE_EITHRESHOLD); > > + } > > +} > > + > > +int imsic_ids_alloc(unsigned int order) > > +{ > > + int ret; > > + unsigned long flags; > > + > > + raw_spin_lock_irqsave(&imsic->ids_lock, flags); > > + ret = bitmap_find_free_region(imsic->ids_used_bimap, > > + imsic->global.nr_ids + 1, order); > > + raw_spin_unlock_irqrestore(&imsic->ids_lock, flags); > > + > > + return ret; > > +} > > + > > +void imsic_ids_free(unsigned int base_id, unsigned int order) > > +{ > > + unsigned long flags; > > + > > + raw_spin_lock_irqsave(&imsic->ids_lock, flags); > > + bitmap_release_region(imsic->ids_used_bimap, base_id, order); > > + raw_spin_unlock_irqrestore(&imsic->ids_lock, flags); > > +} > > + > > +static int __init imsic_ids_init(void) > > +{ > > + int i; > > + struct imsic_global_config *global = &imsic->global; > > + > > + raw_spin_lock_init(&imsic->ids_lock); > > + > > + /* Allocate used bitmap */ > > + imsic->ids_used_bimap = bitmap_zalloc(global->nr_ids + 1, GFP_KERNEL); > > + if (!imsic->ids_used_bimap) > > + return -ENOMEM; > > + > > + /* Allocate enabled bitmap */ > > + imsic->ids_enabled_bimap = bitmap_zalloc(global->nr_ids + 1, > > + GFP_KERNEL); > > + if (!imsic->ids_enabled_bimap) { > > + kfree(imsic->ids_used_bimap); > > + return -ENOMEM; > > + } > > + > > + /* Allocate target CPU array */ > > + imsic->ids_target_cpu = kcalloc(global->nr_ids + 1, > > + sizeof(unsigned int), GFP_KERNEL); > > + if (!imsic->ids_target_cpu) { > > + bitmap_free(imsic->ids_enabled_bimap); > > + bitmap_free(imsic->ids_used_bimap); > > + return -ENOMEM; > > + } > > + for (i = 0; i <= global->nr_ids; i++) > > + imsic->ids_target_cpu[i] = UINT_MAX; > > + > > + /* Reserve ID#0 because it is special and never implemented */ > > + bitmap_set(imsic->ids_used_bimap, 0, 1); > > + > > + return 0; > > +} > > + > > +static void __init imsic_ids_cleanup(void) > > +{ > > + kfree(imsic->ids_target_cpu); > > + bitmap_free(imsic->ids_enabled_bimap); > > + bitmap_free(imsic->ids_used_bimap); > > +} > > + > > +static int __init imsic_get_parent_hartid(struct fwnode_handle *fwnode, > > + u32 index, unsigned long *hartid) > > +{ > > + int rc; > > + struct fwnode_reference_args parent; > > + > > + rc = fwnode_property_get_reference_args(fwnode, > > + "interrupts-extended", "#interrupt-cells", > > + 0, index, &parent); > > + if (rc) > > + return rc; > > + > > + /* > > + * Skip interrupts other than external interrupts for > > + * current privilege level. > > + */ > > + if (parent.args[0] != RV_IRQ_EXT) > > + return -EINVAL; > > + > > + return riscv_get_intc_hartid(parent.fwnode, hartid); > > +} > > + > > +static int __init imsic_get_mmio_resource(struct fwnode_handle *fwnode, > > + u32 index, struct resource *res) > > +{ > > + /* > > + * Currently, only OF fwnode is support so extend this function > > + * for other types of fwnode for ACPI support. > > + */ > > + if (!is_of_node(fwnode)) > > + return -EINVAL; > > + return of_address_to_resource(to_of_node(fwnode), index, res); > > +} > > + > > +int __init imsic_setup_state(struct fwnode_handle *fwnode) > > +{ > > + int rc, cpu; > > + phys_addr_t base_addr; > > + void __iomem **mmios_va = NULL; > > + struct resource res, *mmios = NULL; > > + struct imsic_local_config *local; > > + struct imsic_global_config *global; > > + unsigned long reloff, hartid; > > + u32 i, j, index, nr_parent_irqs, nr_handlers = 0, num_mmios = 0; > > + > > + /* > > + * Only one IMSIC instance allowed in a platform for clean > > + * implementation of SMP IRQ affinity and per-CPU IPIs. > > + * > > + * This means on a multi-socket (or multi-die) platform we > > + * will have multiple MMIO regions for one IMSIC instance. > > + */ > > + if (imsic) { > > + pr_err("%pfwP: already initialized hence ignoring\n", > > + fwnode); > > + return -EALREADY; > > + } > > + > > + if (!riscv_isa_extension_available(NULL, SxAIA)) { > > + pr_err("%pfwP: AIA support not available\n", fwnode); > > + return -ENODEV; > > + } > > + > > + imsic = kzalloc(sizeof(*imsic), GFP_KERNEL); > > + if (!imsic) > > + return -ENOMEM; > > + imsic->fwnode = fwnode; > > + global = &imsic->global; > > + > > + global->local = alloc_percpu(typeof(*(global->local))); > > + if (!global->local) { > > + rc = -ENOMEM; > > + goto out_free_priv; > > + } > > + > > + /* Find number of parent interrupts */ > > + nr_parent_irqs = 0; > > + while (!imsic_get_parent_hartid(fwnode, nr_parent_irqs, &hartid)) > > + nr_parent_irqs++; > > + if (!nr_parent_irqs) { > > + pr_err("%pfwP: no parent irqs available\n", fwnode); > > + rc = -EINVAL; > > + goto out_free_local; > > + } > > + > > + /* Find number of guest index bits in MSI address */ > > + rc = fwnode_property_read_u32_array(fwnode, "riscv,guest-index-bits", > > + &global->guest_index_bits, 1); > > + if (rc) > > + global->guest_index_bits = 0; > > + i = BITS_PER_LONG - IMSIC_MMIO_PAGE_SHIFT; > > + if (i < global->guest_index_bits) { > > + pr_err("%pfwP: guest index bits too big\n", fwnode); > > + rc = -EINVAL; > > + goto out_free_local; > > + } > > + > > + /* Find number of HART index bits */ > > + rc = fwnode_property_read_u32_array(fwnode, "riscv,hart-index-bits", > > + &global->hart_index_bits, 1); > > + if (rc) { > > + /* Assume default value */ > > + global->hart_index_bits = __fls(nr_parent_irqs); > > + if (BIT(global->hart_index_bits) < nr_parent_irqs) > > + global->hart_index_bits++; > > + } > > + i = BITS_PER_LONG - IMSIC_MMIO_PAGE_SHIFT - global->guest_index_bits; > > + if (i < global->hart_index_bits) { > > + pr_err("%pfwP: HART index bits too big\n", fwnode); > > + rc = -EINVAL; > > + goto out_free_local; > > + } > > + > > + /* Find number of group index bits */ > > + rc = fwnode_property_read_u32_array(fwnode, "riscv,group-index-bits", > > + &global->group_index_bits, 1); > > + if (rc) > > + global->group_index_bits = 0; > > + i = BITS_PER_LONG - IMSIC_MMIO_PAGE_SHIFT - > > + global->guest_index_bits - global->hart_index_bits; > > + if (i < global->group_index_bits) { > > + pr_err("%pfwP: group index bits too big\n", fwnode); > > + rc = -EINVAL; > > + goto out_free_local; > > + } > > + > > + /* > > + * Find first bit position of group index. > > + * If not specified assumed the default APLIC-IMSIC configuration. > > + */ > > + rc = fwnode_property_read_u32_array(fwnode, "riscv,group-index-shift", > > + &global->group_index_shift, 1); > > + if (rc) > > + global->group_index_shift = IMSIC_MMIO_PAGE_SHIFT * 2; > > + i = global->group_index_bits + global->group_index_shift - 1; > > + if (i >= BITS_PER_LONG) { > > + pr_err("%pfwP: group index shift too big\n", fwnode); > > + rc = -EINVAL; > > + goto out_free_local; > > + } > > + > > + /* Find number of interrupt identities */ > > + rc = fwnode_property_read_u32_array(fwnode, "riscv,num-ids", > > + &global->nr_ids, 1); > > + if (rc) { > > + pr_err("%pfwP: number of interrupt identities not found\n", > > + fwnode); > > + goto out_free_local; > > + } > > + if ((global->nr_ids < IMSIC_MIN_ID) || > > + (global->nr_ids >= IMSIC_MAX_ID) || > > + ((global->nr_ids & IMSIC_MIN_ID) != IMSIC_MIN_ID)) { > > + pr_err("%pfwP: invalid number of interrupt identities\n", > > + fwnode); > > + rc = -EINVAL; > > + goto out_free_local; > > + } > > + > > + /* Find number of guest interrupt identities */ > > + if (fwnode_property_read_u32_array(fwnode, "riscv,num-guest-ids", > > + &global->nr_guest_ids, 1)) > > + global->nr_guest_ids = global->nr_ids; > > + if ((global->nr_guest_ids < IMSIC_MIN_ID) || > > + (global->nr_guest_ids >= IMSIC_MAX_ID) || > > + ((global->nr_guest_ids & IMSIC_MIN_ID) != IMSIC_MIN_ID)) { > > + pr_err("%pfwP: invalid number of guest interrupt identities\n", > > + fwnode); > > + rc = -EINVAL; > > + goto out_free_local; > > + } > > + > > Could you create a separate function for DT to fill up this > imsic_global structure? In case of ACPI, we can not get this data from > the fwnode and hence need to have separate function to fill up this > structure. Okay, I will update. Regards, Anup > > Thanks! > Sunil > > + /* Compute base address */ > > + rc = imsic_get_mmio_resource(fwnode, 0, &res); > > + if (rc) { > > + pr_err("%pfwP: first MMIO resource not found\n", fwnode); > > + rc = -EINVAL; > > + goto out_free_local; > > + } > > + global->base_addr = res.start; > > + global->base_addr &= ~(BIT(global->guest_index_bits + > > + global->hart_index_bits + > > + IMSIC_MMIO_PAGE_SHIFT) - 1); > > + global->base_addr &= ~((BIT(global->group_index_bits) - 1) << > > + global->group_index_shift); > > + > > + /* Find number of MMIO register sets */ > > + while (!imsic_get_mmio_resource(fwnode, num_mmios, &res)) > > + num_mmios++; > > + > > + /* Allocate MMIO resource array */ > > + mmios = kcalloc(num_mmios, sizeof(*mmios), GFP_KERNEL); > > + if (!mmios) { > > + rc = -ENOMEM; > > + goto out_free_local; > > + } > > + > > + /* Allocate MMIO virtual address array */ > > + mmios_va = kcalloc(num_mmios, sizeof(*mmios_va), GFP_KERNEL); > > + if (!mmios_va) { > > + rc = -ENOMEM; > > + goto out_iounmap; > > + } > > + > > + /* Parse and map MMIO register sets */ > > + for (i = 0; i < num_mmios; i++) { > > + rc = imsic_get_mmio_resource(fwnode, i, &mmios[i]); > > + if (rc) { > > + pr_err("%pfwP: unable to parse MMIO regset %d\n", > > + fwnode, i); > > + goto out_iounmap; > > + } > > + > > + base_addr = mmios[i].start; > > + base_addr &= ~(BIT(global->guest_index_bits + > > + global->hart_index_bits + > > + IMSIC_MMIO_PAGE_SHIFT) - 1); > > + base_addr &= ~((BIT(global->group_index_bits) - 1) << > > + global->group_index_shift); > > + if (base_addr != global->base_addr) { > > + rc = -EINVAL; > > + pr_err("%pfwP: address mismatch for regset %d\n", > > + fwnode, i); > > + goto out_iounmap; > > + } > > + > > + mmios_va[i] = ioremap(mmios[i].start, resource_size(&mmios[i])); > > + if (!mmios_va[i]) { > > + rc = -EIO; > > + pr_err("%pfwP: unable to map MMIO regset %d\n", > > + fwnode, i); > > + goto out_iounmap; > > + } > > + } > > + > > + /* Initialize interrupt identity management */ > > + rc = imsic_ids_init(); > > + if (rc) { > > + pr_err("%pfwP: failed to initialize interrupt management\n", > > + fwnode); > > + goto out_iounmap; > > + } > > + > > + /* Configure handlers for target CPUs */ > > + for (i = 0; i < nr_parent_irqs; i++) { > > + rc = imsic_get_parent_hartid(fwnode, i, &hartid); > > + if (rc) { > > + pr_warn("%pfwP: hart ID for parent irq%d not found\n", > > + fwnode, i); > > + continue; > > + } > > + > > + cpu = riscv_hartid_to_cpuid(hartid); > > + if (cpu < 0) { > > + pr_warn("%pfwP: invalid cpuid for parent irq%d\n", > > + fwnode, i); > > + continue; > > + } > > + > > + /* Find MMIO location of MSI page */ > > + index = num_mmios; > > + reloff = i * BIT(global->guest_index_bits) * > > + IMSIC_MMIO_PAGE_SZ; > > + for (j = 0; num_mmios; j++) { > > + if (reloff < resource_size(&mmios[j])) { > > + index = j; > > + break; > > + } > > + > > + /* > > + * MMIO region size may not be aligned to > > + * BIT(global->guest_index_bits) * IMSIC_MMIO_PAGE_SZ > > + * if holes are present. > > + */ > > + reloff -= ALIGN(resource_size(&mmios[j]), > > + BIT(global->guest_index_bits) * IMSIC_MMIO_PAGE_SZ); > > + } > > + if (index >= num_mmios) { > > + pr_warn("%pfwP: MMIO not found for parent irq%d\n", > > + fwnode, i); > > + continue; > > + } > > + > > + local = per_cpu_ptr(global->local, cpu); > > + local->msi_pa = mmios[index].start + reloff; > > + local->msi_va = mmios_va[index] + reloff; > > + > > + nr_handlers++; > > + } > > + > > + /* If no CPU handlers found then can't take interrupts */ > > + if (!nr_handlers) { > > + pr_err("%pfwP: No CPU handlers found\n", fwnode); > > + rc = -ENODEV; > > + goto out_ids_cleanup; > > + } > > + > > + /* We don't need MMIO arrays anymore so let's free-up */ > > + kfree(mmios_va); > > + kfree(mmios); > > + > > + return 0; > > + > > +out_ids_cleanup: > > + imsic_ids_cleanup(); > > +out_iounmap: > > + for (i = 0; i < num_mmios; i++) { > > + if (mmios_va[i]) > > + iounmap(mmios_va[i]); > > + } > > + kfree(mmios_va); > > + kfree(mmios); > > +out_free_local: > > + free_percpu(imsic->global.local); > > +out_free_priv: > > + kfree(imsic); > > + imsic = NULL; > > + return rc; > > +} > > diff --git a/drivers/irqchip/irq-riscv-imsic-state.h b/drivers/irqchip/irq-riscv-imsic-state.h > > new file mode 100644 > > index 000000000000..3170018949a8 > > --- /dev/null > > +++ b/drivers/irqchip/irq-riscv-imsic-state.h > > @@ -0,0 +1,66 @@ > > +/* SPDX-License-Identifier: GPL-2.0-only */ > > +/* > > + * Copyright (C) 2021 Western Digital Corporation or its affiliates. > > + * Copyright (C) 2022 Ventana Micro Systems Inc. > > + */ > > + > > +#ifndef _IRQ_RISCV_IMSIC_STATE_H > > +#define _IRQ_RISCV_IMSIC_STATE_H > > + > > +#include <linux/irqchip/riscv-imsic.h> > > +#include <linux/irqdomain.h> > > +#include <linux/fwnode.h> > > + > > +struct imsic_priv { > > + /* Device details */ > > + struct fwnode_handle *fwnode; > > + > > + /* Global configuration common for all HARTs */ > > + struct imsic_global_config global; > > + > > + /* Global state of interrupt identities */ > > + raw_spinlock_t ids_lock; > > + unsigned long *ids_used_bimap; > > + unsigned long *ids_enabled_bimap; > > + unsigned int *ids_target_cpu; > > + > > + /* IPI interrupt identity and synchronization */ > > + u32 ipi_id; > > + int ipi_virq; > > + struct irq_desc *ipi_lsync_desc; > > + > > + /* IRQ domains (created by platform driver) */ > > + struct irq_domain *base_domain; > > + struct irq_domain *plat_domain; > > +}; > > + > > +extern struct imsic_priv *imsic; > > + > > +void __imsic_eix_update(unsigned long base_id, > > + unsigned long num_id, bool pend, bool val); > > + > > +#define __imsic_id_enable(__id) \ > > + __imsic_eix_update((__id), 1, false, true) > > +#define __imsic_id_disable(__id) \ > > + __imsic_eix_update((__id), 1, false, false) > > + > > +void imsic_id_set_target(unsigned int id, unsigned int target_cpu); > > +unsigned int imsic_id_get_target(unsigned int id); > > + > > +void imsic_ids_local_sync(void); > > +void imsic_ids_local_delivery(bool enable); > > + > > +#ifdef CONFIG_SMP > > +void imsic_ids_remote_sync(void); > > +#else > > +static inline void imsic_ids_remote_sync(void) > > +{ > > +} > > +#endif > > + > > +int imsic_ids_alloc(unsigned int order); > > +void imsic_ids_free(unsigned int base_id, unsigned int order); > > + > > +int imsic_setup_state(struct fwnode_handle *fwnode); > > + > > +#endif > > diff --git a/include/linux/irqchip/riscv-imsic.h b/include/linux/irqchip/riscv-imsic.h > > new file mode 100644 > > index 000000000000..1f6fc9a57218 > > --- /dev/null > > +++ b/include/linux/irqchip/riscv-imsic.h > > @@ -0,0 +1,86 @@ > > +/* SPDX-License-Identifier: GPL-2.0-only */ > > +/* > > + * Copyright (C) 2021 Western Digital Corporation or its affiliates. > > + * Copyright (C) 2022 Ventana Micro Systems Inc. > > + */ > > +#ifndef __LINUX_IRQCHIP_RISCV_IMSIC_H > > +#define __LINUX_IRQCHIP_RISCV_IMSIC_H > > + > > +#include <linux/types.h> > > +#include <asm/csr.h> > > + > > +#define IMSIC_MMIO_PAGE_SHIFT 12 > > +#define IMSIC_MMIO_PAGE_SZ (1UL << IMSIC_MMIO_PAGE_SHIFT) > > +#define IMSIC_MMIO_PAGE_LE 0x00 > > +#define IMSIC_MMIO_PAGE_BE 0x04 > > + > > +#define IMSIC_MIN_ID 63 > > +#define IMSIC_MAX_ID 2048 > > + > > +#define IMSIC_EIDELIVERY 0x70 > > + > > +#define IMSIC_EITHRESHOLD 0x72 > > + > > +#define IMSIC_EIP0 0x80 > > +#define IMSIC_EIP63 0xbf > > +#define IMSIC_EIPx_BITS 32 > > + > > +#define IMSIC_EIE0 0xc0 > > +#define IMSIC_EIE63 0xff > > +#define IMSIC_EIEx_BITS 32 > > + > > +#define IMSIC_FIRST IMSIC_EIDELIVERY > > +#define IMSIC_LAST IMSIC_EIE63 > > + > > +#define IMSIC_MMIO_SETIPNUM_LE 0x00 > > +#define IMSIC_MMIO_SETIPNUM_BE 0x04 > > + > > +struct imsic_local_config { > > + phys_addr_t msi_pa; > > + void __iomem *msi_va; > > +}; > > + > > +struct imsic_global_config { > > + /* > > + * MSI Target Address Scheme > > + * > > + * XLEN-1 12 0 > > + * | | | > > + * ------------------------------------------------------------- > > + * |xxxxxx|Group Index|xxxxxxxxxxx|HART Index|Guest Index| 0 | > > + * ------------------------------------------------------------- > > + */ > > + > > + /* Bits representing Guest index, HART index, and Group index */ > > + u32 guest_index_bits; > > + u32 hart_index_bits; > > + u32 group_index_bits; > > + u32 group_index_shift; > > + > > + /* Global base address matching all target MSI addresses */ > > + phys_addr_t base_addr; > > + > > + /* Number of interrupt identities */ > > + u32 nr_ids; > > + > > + /* Number of guest interrupt identities */ > > + u32 nr_guest_ids; > > + > > + /* Per-CPU IMSIC addresses */ > > + struct imsic_local_config __percpu *local; > > +}; > > + > > +#ifdef CONFIG_RISCV_IMSIC > > + > > +extern const struct imsic_global_config *imsic_get_global_config(void); > > + > > +#else > > + > > +static inline const struct imsic_global_config *imsic_get_global_config(void) > > +{ > > + return NULL; > > +} > > + > > +#endif > > + > > +#endif > > -- > > 2.34.1 > >
On Mon, Sep 25, 2023 at 1:26 PM Sunil V L <sunilvl@ventanamicro.com> wrote: > > Hi Anup, > > On Tue, Sep 12, 2023 at 11:19:25PM +0530, Anup Patel wrote: > > The RISC-V advanced interrupt architecture (AIA) specification defines > > advanced platform-level interrupt controller (APLIC) which has two modes > > of operation: 1) Direct mode and 2) MSI mode. > > (For more details, refer https://github.com/riscv/riscv-aia) > > > > In APLIC direct-mode, wired interrupts are forwared to CPUs (or HARTs) > > as a local external interrupt. > > > > We add a platform irqchip driver for the RISC-V APLIC direct-mode to > > support RISC-V platforms having only wired interrupts. > > > > Signed-off-by: Anup Patel <apatel@ventanamicro.com> > > --- > > drivers/irqchip/Kconfig | 5 + > > drivers/irqchip/Makefile | 1 + > > drivers/irqchip/irq-riscv-aplic-direct.c | 326 +++++++++++++++++++++++ > > drivers/irqchip/irq-riscv-aplic-main.c | 240 +++++++++++++++++ > > drivers/irqchip/irq-riscv-aplic-main.h | 45 ++++ > > include/linux/irqchip/riscv-aplic.h | 119 +++++++++ > > 6 files changed, 736 insertions(+) > > create mode 100644 drivers/irqchip/irq-riscv-aplic-direct.c > > create mode 100644 drivers/irqchip/irq-riscv-aplic-main.c > > create mode 100644 drivers/irqchip/irq-riscv-aplic-main.h > > create mode 100644 include/linux/irqchip/riscv-aplic.h > > > > diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig > > index a6aad78076a0..44c455084d09 100644 > > --- a/drivers/irqchip/Kconfig > > +++ b/drivers/irqchip/Kconfig > > @@ -545,6 +545,11 @@ config SIFIVE_PLIC > > select IRQ_DOMAIN_HIERARCHY > > select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP > > > > +config RISCV_APLIC > > + bool > > + depends on RISCV > > + select IRQ_DOMAIN_HIERARCHY > > + > > config RISCV_IMSIC > > bool > > depends on RISCV > > diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile > > index abca445a3229..7f8289790ed8 100644 > > --- a/drivers/irqchip/Makefile > > +++ b/drivers/irqchip/Makefile > > @@ -95,6 +95,7 @@ obj-$(CONFIG_QCOM_MPM) += irq-qcom-mpm.o > > obj-$(CONFIG_CSKY_MPINTC) += irq-csky-mpintc.o > > obj-$(CONFIG_CSKY_APB_INTC) += irq-csky-apb-intc.o > > obj-$(CONFIG_RISCV_INTC) += irq-riscv-intc.o > > +obj-$(CONFIG_RISCV_APLIC) += irq-riscv-aplic-main.o irq-riscv-aplic-direct.o > > obj-$(CONFIG_RISCV_IMSIC) += irq-riscv-imsic-state.o irq-riscv-imsic-early.o irq-riscv-imsic-platform.o > > obj-$(CONFIG_SIFIVE_PLIC) += irq-sifive-plic.o > > obj-$(CONFIG_IMX_IRQSTEER) += irq-imx-irqsteer.o > > diff --git a/drivers/irqchip/irq-riscv-aplic-direct.c b/drivers/irqchip/irq-riscv-aplic-direct.c > > new file mode 100644 > > index 000000000000..e36d655a1490 > > --- /dev/null > > +++ b/drivers/irqchip/irq-riscv-aplic-direct.c > > @@ -0,0 +1,326 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Copyright (C) 2021 Western Digital Corporation or its affiliates. > > + * Copyright (C) 2022 Ventana Micro Systems Inc. > > + */ > > + > > +#include <linux/bitops.h> > > +#include <linux/cpu.h> > > +#include <linux/interrupt.h> > > +#include <linux/irqchip.h> > > +#include <linux/irqchip/chained_irq.h> > > +#include <linux/irqchip/riscv-aplic.h> > > +#include <linux/module.h> > > +#include <linux/of_address.h> > > +#include <linux/printk.h> > > +#include <linux/smp.h> > > + > > +#include "irq-riscv-aplic-main.h" > > + > > +#define APLIC_DISABLE_IDELIVERY 0 > > +#define APLIC_ENABLE_IDELIVERY 1 > > +#define APLIC_DISABLE_ITHRESHOLD 1 > > +#define APLIC_ENABLE_ITHRESHOLD 0 > > + > > +struct aplic_direct { > > + struct aplic_priv priv; > > + struct irq_domain *irqdomain; > > + struct cpumask lmask; > > +}; > > + > > +struct aplic_idc { > > + unsigned int hart_index; > > + void __iomem *regs; > > + struct aplic_direct *direct; > > +}; > > + > > +static unsigned int aplic_direct_parent_irq; > > +static DEFINE_PER_CPU(struct aplic_idc, aplic_idcs); > > + > > +static void aplic_direct_irq_eoi(struct irq_data *d) > > +{ > > + /* > > + * The fasteoi_handler requires irq_eoi() callback hence > > + * provide a dummy handler. > > + */ > > +} > > + > > +#ifdef CONFIG_SMP > > +static int aplic_direct_set_affinity(struct irq_data *d, > > + const struct cpumask *mask_val, bool force) > > +{ > > + struct aplic_priv *priv = irq_data_get_irq_chip_data(d); > > + struct aplic_direct *direct = > > + container_of(priv, struct aplic_direct, priv); > > + struct aplic_idc *idc; > > + unsigned int cpu, val; > > + struct cpumask amask; > > + void __iomem *target; > > + > > + cpumask_and(&amask, &direct->lmask, mask_val); > > + > > + if (force) > > + cpu = cpumask_first(&amask); > > + else > > + cpu = cpumask_any_and(&amask, cpu_online_mask); > > + > > + if (cpu >= nr_cpu_ids) > > + return -EINVAL; > > + > > + idc = per_cpu_ptr(&aplic_idcs, cpu); > > + target = priv->regs + APLIC_TARGET_BASE; > > + target += (d->hwirq - 1) * sizeof(u32); > > + val = idc->hart_index & APLIC_TARGET_HART_IDX_MASK; > > + val <<= APLIC_TARGET_HART_IDX_SHIFT; > > + val |= APLIC_DEFAULT_PRIORITY; > > + writel(val, target); > > + > > + irq_data_update_effective_affinity(d, cpumask_of(cpu)); > > + > > + return IRQ_SET_MASK_OK_DONE; > > +} > > +#endif > > + > > +static struct irq_chip aplic_direct_chip = { > > + .name = "APLIC-DIRECT", > > + .irq_mask = aplic_irq_mask, > > + .irq_unmask = aplic_irq_unmask, > > + .irq_set_type = aplic_irq_set_type, > > + .irq_eoi = aplic_direct_irq_eoi, > > +#ifdef CONFIG_SMP > > + .irq_set_affinity = aplic_direct_set_affinity, > > +#endif > > + .flags = IRQCHIP_SET_TYPE_MASKED | > > + IRQCHIP_SKIP_SET_WAKE | > > + IRQCHIP_MASK_ON_SUSPEND, > > +}; > > + > > +static int aplic_direct_irqdomain_translate(struct irq_domain *d, > > + struct irq_fwspec *fwspec, > > + unsigned long *hwirq, > > + unsigned int *type) > > +{ > > + struct aplic_priv *priv = d->host_data; > > + > > + return aplic_irqdomain_translate(fwspec, priv->gsi_base, > > + hwirq, type); > > +} > > + > > +static int aplic_direct_irqdomain_alloc(struct irq_domain *domain, > > + unsigned int virq, unsigned int nr_irqs, > > + void *arg) > > +{ > > + int i, ret; > > + unsigned int type; > > + irq_hw_number_t hwirq; > > + struct irq_fwspec *fwspec = arg; > > + struct aplic_priv *priv = domain->host_data; > > + struct aplic_direct *direct = > > + container_of(priv, struct aplic_direct, priv); > > + > > + ret = aplic_irqdomain_translate(fwspec, priv->gsi_base, > > + &hwirq, &type); > > + if (ret) > > + return ret; > > + > > + for (i = 0; i < nr_irqs; i++) { > > + irq_domain_set_info(domain, virq + i, hwirq + i, > > + &aplic_direct_chip, priv, > > + handle_fasteoi_irq, NULL, NULL); > > + irq_set_affinity(virq + i, &direct->lmask); > > + /* See the reason described in aplic_msi_irqdomain_alloc() */ > > + irq_set_status_flags(virq + i, IRQ_DISABLE_UNLAZY); > > + } > > + > > + return 0; > > +} > > + > > +static const struct irq_domain_ops aplic_direct_irqdomain_ops = { > > + .translate = aplic_direct_irqdomain_translate, > > + .alloc = aplic_direct_irqdomain_alloc, > > + .free = irq_domain_free_irqs_top, > > +}; > > + > > +/* > > + * To handle an APLIC direct interrupts, we just read the CLAIMI register > > + * which will return highest priority pending interrupt and clear the > > + * pending bit of the interrupt. This process is repeated until CLAIMI > > + * register return zero value. > > + */ > > +static void aplic_direct_handle_irq(struct irq_desc *desc) > > +{ > > + struct aplic_idc *idc = this_cpu_ptr(&aplic_idcs); > > + struct irq_chip *chip = irq_desc_get_chip(desc); > > + struct irq_domain *irqdomain = idc->direct->irqdomain; > > + irq_hw_number_t hw_irq; > > + int irq; > > + > > + chained_irq_enter(chip, desc); > > + > > + while ((hw_irq = readl(idc->regs + APLIC_IDC_CLAIMI))) { > > + hw_irq = hw_irq >> APLIC_IDC_TOPI_ID_SHIFT; > > + irq = irq_find_mapping(irqdomain, hw_irq); > > + > > + if (unlikely(irq <= 0)) > > + dev_warn_ratelimited(idc->direct->priv.dev, > > + "hw_irq %lu mapping not found\n", > > + hw_irq); > > + else > > + generic_handle_irq(irq); > > + } > > + > > + chained_irq_exit(chip, desc); > > +} > > + > > +static void aplic_idc_set_delivery(struct aplic_idc *idc, bool en) > > +{ > > + u32 de = (en) ? APLIC_ENABLE_IDELIVERY : APLIC_DISABLE_IDELIVERY; > > + u32 th = (en) ? APLIC_ENABLE_ITHRESHOLD : APLIC_DISABLE_ITHRESHOLD; > > + > > + /* Priority must be less than threshold for interrupt triggering */ > > + writel(th, idc->regs + APLIC_IDC_ITHRESHOLD); > > + > > + /* Delivery must be set to 1 for interrupt triggering */ > > + writel(de, idc->regs + APLIC_IDC_IDELIVERY); > > +} > > + > > +static int aplic_direct_dying_cpu(unsigned int cpu) > > +{ > > + if (aplic_direct_parent_irq) > > + disable_percpu_irq(aplic_direct_parent_irq); > > + > > + return 0; > > +} > > + > > +static int aplic_direct_starting_cpu(unsigned int cpu) > > +{ > > + if (aplic_direct_parent_irq) > > + enable_percpu_irq(aplic_direct_parent_irq, > > + irq_get_trigger_type(aplic_direct_parent_irq)); > > + > > + return 0; > > +} > > + > > +int aplic_direct_setup(struct device *dev, void __iomem *regs) > > +{ > > + int i, j, rc, cpu, setup_count = 0; > > + struct fwnode_reference_args parent; > > + struct aplic_direct *direct; > > + struct aplic_priv *priv; > > + struct irq_domain *domain; > > + unsigned long hartid; > > + struct aplic_idc *idc; > > + u32 val; > > + > > + direct = kzalloc(sizeof(*direct), GFP_KERNEL); > > + if (!direct) > > + return -ENOMEM; > > + priv = &direct->priv; > > + > > + rc = aplic_setup_priv(priv, dev, regs); > > + if (rc) { > > + dev_err(dev, "failed to create APLIC context\n"); > > + kfree(direct); > > + return rc; > > + } > > + > > + /* Setup per-CPU IDC and target CPU mask */ > > + for (i = 0; i < priv->nr_idcs; i++) { > > + rc = fwnode_property_get_reference_args(dev->fwnode, > > + "interrupts-extended", "#interrupt-cells", > > + 0, i, &parent); > > + if (rc) { > > + dev_warn(dev, "parent irq for IDC%d not found\n", i); > > + continue; > > + } > > + > > + /* > > + * Skip interrupts other than external interrupts for > > + * current privilege level. > > + */ > > + if (parent.args[0] != RV_IRQ_EXT) > > + continue; > > + > > + rc = riscv_get_intc_hartid(parent.fwnode, &hartid); > > + if (rc) { > > + dev_warn(dev, "invalid hartid for IDC%d\n", i); > > + continue; > > + } > > + > > + cpu = riscv_hartid_to_cpuid(hartid); > > + if (cpu < 0) { > > + dev_warn(dev, "invalid cpuid for IDC%d\n", i); > > + continue; > > + } > > + > > + cpumask_set_cpu(cpu, &direct->lmask); > > + > > + idc = per_cpu_ptr(&aplic_idcs, cpu); > > + idc->hart_index = i; > > + idc->regs = priv->regs + APLIC_IDC_BASE + i * APLIC_IDC_SIZE; > > + idc->direct = direct; > > + > > + aplic_idc_set_delivery(idc, true); > > + > > + /* > > + * Boot cpu might not have APLIC hart_index = 0 so check > > + * and update target registers of all interrupts. > > + */ > > + if (cpu == smp_processor_id() && idc->hart_index) { > > + val = idc->hart_index & APLIC_TARGET_HART_IDX_MASK; > > + val <<= APLIC_TARGET_HART_IDX_SHIFT; > > + val |= APLIC_DEFAULT_PRIORITY; > > + for (j = 1; j <= priv->nr_irqs; j++) > > + writel(val, priv->regs + APLIC_TARGET_BASE + > > + (j - 1) * sizeof(u32)); > > + } > > + > > + setup_count++; > > + } > > + > > + /* Find parent domain and register chained handler */ > > + domain = irq_find_matching_fwnode(riscv_get_intc_hwnode(), > > + DOMAIN_BUS_ANY); > > + if (!aplic_direct_parent_irq && domain) { > > + aplic_direct_parent_irq = irq_create_mapping(domain, RV_IRQ_EXT); > > + if (aplic_direct_parent_irq) { > > + irq_set_chained_handler(aplic_direct_parent_irq, > > + aplic_direct_handle_irq); > > + > > + /* > > + * Setup CPUHP notifier to enable parent > > + * interrupt on all CPUs > > + */ > > + cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, > > + "irqchip/riscv/aplic:starting", > > + aplic_direct_starting_cpu, > > + aplic_direct_dying_cpu); > > + } > > + } > > + > > + /* Fail if we were not able to setup IDC for any CPU */ > > + if (!setup_count) { > > + kfree(direct); > > + return -ENODEV; > > + } > > + > > + /* Setup global config and interrupt delivery */ > > + aplic_init_hw_global(priv, false); > > + > > + /* Create irq domain instance for the APLIC */ > > + direct->irqdomain = irq_domain_create_linear(dev->fwnode, > > + priv->nr_irqs + 1, > > + &aplic_direct_irqdomain_ops, > > + priv); > > + if (!direct->irqdomain) { > > + dev_err(dev, "failed to create direct irq domain\n"); > > + kfree(direct); > > + return -ENOMEM; > > + } > > + > > + /* Advertise the interrupt controller */ > > + dev_info(dev, "%d interrupts directly connected to %d CPUs\n", > > + priv->nr_irqs, priv->nr_idcs); > > + > > + return 0; > > +} > > diff --git a/drivers/irqchip/irq-riscv-aplic-main.c b/drivers/irqchip/irq-riscv-aplic-main.c > > new file mode 100644 > > index 000000000000..d62a096774c4 > > --- /dev/null > > +++ b/drivers/irqchip/irq-riscv-aplic-main.c > > @@ -0,0 +1,240 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Copyright (C) 2021 Western Digital Corporation or its affiliates. > > + * Copyright (C) 2022 Ventana Micro Systems Inc. > > + */ > > + > > +#include <linux/printk.h> > > +#include <linux/module.h> > > +#include <linux/platform_device.h> > > +#include <linux/irqchip/riscv-aplic.h> > > + > > +#include "irq-riscv-aplic-main.h" > > + > > +void aplic_irq_unmask(struct irq_data *d) > > +{ > > + struct aplic_priv *priv = irq_data_get_irq_chip_data(d); > > + > > + writel(d->hwirq, priv->regs + APLIC_SETIENUM); > > +} > > + > > +void aplic_irq_mask(struct irq_data *d) > > +{ > > + struct aplic_priv *priv = irq_data_get_irq_chip_data(d); > > + > > + writel(d->hwirq, priv->regs + APLIC_CLRIENUM); > > +} > > + > > +int aplic_irq_set_type(struct irq_data *d, unsigned int type) > > +{ > > + u32 val = 0; > > + void __iomem *sourcecfg; > > + struct aplic_priv *priv = irq_data_get_irq_chip_data(d); > > + > > + switch (type) { > > + case IRQ_TYPE_NONE: > > + val = APLIC_SOURCECFG_SM_INACTIVE; > > + break; > > + case IRQ_TYPE_LEVEL_LOW: > > + val = APLIC_SOURCECFG_SM_LEVEL_LOW; > > + break; > > + case IRQ_TYPE_LEVEL_HIGH: > > + val = APLIC_SOURCECFG_SM_LEVEL_HIGH; > > + break; > > + case IRQ_TYPE_EDGE_FALLING: > > + val = APLIC_SOURCECFG_SM_EDGE_FALL; > > + break; > > + case IRQ_TYPE_EDGE_RISING: > > + val = APLIC_SOURCECFG_SM_EDGE_RISE; > > + break; > > + default: > > + return -EINVAL; > > + } > > + > > + sourcecfg = priv->regs + APLIC_SOURCECFG_BASE; > > + sourcecfg += (d->hwirq - 1) * sizeof(u32); > > + writel(val, sourcecfg); > > + > > + return 0; > > +} > > + > > +int aplic_irqdomain_translate(struct irq_fwspec *fwspec, u32 gsi_base, > > + unsigned long *hwirq, unsigned int *type) > > +{ > > + if (WARN_ON(fwspec->param_count < 2)) > > + return -EINVAL; > > + if (WARN_ON(!fwspec->param[0])) > > + return -EINVAL; > > + > > + /* For DT, gsi_base is always zero. */ > > + *hwirq = fwspec->param[0] - gsi_base; > > + *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; > > + > > + WARN_ON(*type == IRQ_TYPE_NONE); > > + > > + return 0; > > +} > > + > > +void aplic_init_hw_global(struct aplic_priv *priv, bool msi_mode) > > +{ > > + u32 val; > > +#ifdef CONFIG_RISCV_M_MODE > > + u32 valH; > > + > > + if (msi_mode) { > > + val = priv->msicfg.base_ppn; > > + valH = ((u64)priv->msicfg.base_ppn >> 32) & > > + APLIC_xMSICFGADDRH_BAPPN_MASK; > > + valH |= (priv->msicfg.lhxw & APLIC_xMSICFGADDRH_LHXW_MASK) > > + << APLIC_xMSICFGADDRH_LHXW_SHIFT; > > + valH |= (priv->msicfg.hhxw & APLIC_xMSICFGADDRH_HHXW_MASK) > > + << APLIC_xMSICFGADDRH_HHXW_SHIFT; > > + valH |= (priv->msicfg.lhxs & APLIC_xMSICFGADDRH_LHXS_MASK) > > + << APLIC_xMSICFGADDRH_LHXS_SHIFT; > > + valH |= (priv->msicfg.hhxs & APLIC_xMSICFGADDRH_HHXS_MASK) > > + << APLIC_xMSICFGADDRH_HHXS_SHIFT; > > + writel(val, priv->regs + APLIC_xMSICFGADDR); > > + writel(valH, priv->regs + APLIC_xMSICFGADDRH); > > + } > > +#endif > > + > > + /* Setup APLIC domaincfg register */ > > + val = readl(priv->regs + APLIC_DOMAINCFG); > > + val |= APLIC_DOMAINCFG_IE; > > + if (msi_mode) > > + val |= APLIC_DOMAINCFG_DM; > > + writel(val, priv->regs + APLIC_DOMAINCFG); > > + if (readl(priv->regs + APLIC_DOMAINCFG) != val) > > + dev_warn(priv->dev, "unable to write 0x%x in domaincfg\n", > > + val); > > +} > > + > > +static void aplic_init_hw_irqs(struct aplic_priv *priv) > > +{ > > + int i; > > + > > + /* Disable all interrupts */ > > + for (i = 0; i <= priv->nr_irqs; i += 32) > > + writel(-1U, priv->regs + APLIC_CLRIE_BASE + > > + (i / 32) * sizeof(u32)); > > + > > + /* Set interrupt type and default priority for all interrupts */ > > + for (i = 1; i <= priv->nr_irqs; i++) { > > + writel(0, priv->regs + APLIC_SOURCECFG_BASE + > > + (i - 1) * sizeof(u32)); > > + writel(APLIC_DEFAULT_PRIORITY, > > + priv->regs + APLIC_TARGET_BASE + > > + (i - 1) * sizeof(u32)); > > + } > > + > > + /* Clear APLIC domaincfg */ > > + writel(0, priv->regs + APLIC_DOMAINCFG); > > +} > > + > > +int aplic_setup_priv(struct aplic_priv *priv, struct device *dev, > > + void __iomem *regs) > > +{ > > + struct fwnode_reference_args parent; > > + int rc; > > + > > + /* Save device pointer and register base */ > > + priv->dev = dev; > > + priv->regs = regs; > > + > > + /* > > + * Find out GSI base number > > + * > > + * Note: DT does not define "riscv,gsi-base" property so GSI > > + * base is always zero for DT. > > + */ > > + rc = fwnode_property_read_u32_array(dev->fwnode, "riscv,gsi-base", > > + &priv->gsi_base, 1); > For DT, you can just initialize this to 0 without reading the property. Okay, I will update. > > > + if (rc) > > + priv->gsi_base = 0; > > + > > + /* Find out number of interrupt sources */ > > + rc = fwnode_property_read_u32_array(dev->fwnode, "riscv,num-sources", > > + &priv->nr_irqs, 1); > > + if (rc) { > > + dev_err(dev, "failed to get number of interrupt sources\n"); > > + return rc; > > + } > > + > > + /* Setup initial state APLIC interrupts */ > > + aplic_init_hw_irqs(priv); > > + > > + /* > > + * Find out number of IDCs based on parent interrupts > > + * > > + * If "msi-parent" property is present then we ignore the > > + * APLIC IDCs which forces the APLIC driver to use MSI mode. > > + */ > > + if (!fwnode_property_present(dev->fwnode, "msi-parent")) { > > + while (!fwnode_property_get_reference_args(dev->fwnode, > > + "interrupts-extended", "#interrupt-cells", > > + 0, priv->nr_idcs, &parent)) > > + priv->nr_idcs++; > > + } > > + > Can this finding nr_idcs be done after aplic_init_hw_irqs() above? Okay, I will update. > > > + return 0; > > +} > > + > > +static int aplic_probe(struct platform_device *pdev) > > +{ > > + struct device *dev = &pdev->dev; > > + struct resource *res; > > + void __iomem *regs; > > + int rc; > > + > > + /* Map the MMIO registers */ > > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > > + if (!res) { > > + dev_err(dev, "failed to get MMIO resource\n"); > > + return -EINVAL; > > + } > > + regs = devm_ioremap(&pdev->dev, res->start, resource_size(res)); > > + if (!regs) { > > + dev_err(dev, "failed map MMIO registers\n"); > > + return -ENOMEM; > > + } > > + > > + /* > > + * If msi-parent property is present then setup APLIC MSI mode > > + * otherwise setup APLIC direct mode. > > + */ > > + if (fwnode_property_present(dev->fwnode, "msi-parent")) > Can this check be based on nr_idcs instead of checking for msi-parent > again? nr_idcs are not available at this point. I will think of something else and maybe you can comment on v9 if it does not work for you. > > Thanks! > Sunil > > + rc = -ENODEV; > > + else > > + rc = aplic_direct_setup(dev, regs); > > + if (rc) { > > + dev_err(dev, "failed setup APLIC in %s mode\n", > > + fwnode_property_present(dev->fwnode, "msi-parent") ? > > + "MSI" : "direct"); > > + return rc; > > + } > > + > > + return 0; > > +} > > + > > +static const struct of_device_id aplic_match[] = { > > + { .compatible = "riscv,aplic" }, > > + {} > > +}; > > + > > +static struct platform_driver aplic_driver = { > > + .driver = { > > + .name = "riscv-aplic", > > + .of_match_table = aplic_match, > > + }, > > + .probe = aplic_probe, > > +}; > > + > > +static int __init aplic_init(void) > > +{ > > + /* > > + * Register APLIC driver as early as possible so that APLIC > > + * platform device is probed as soon as it is created. > > + */ > > + return platform_driver_register(&aplic_driver); > > +} > > +core_initcall(aplic_init); > > diff --git a/drivers/irqchip/irq-riscv-aplic-main.h b/drivers/irqchip/irq-riscv-aplic-main.h > > new file mode 100644 > > index 000000000000..474a04229334 > > --- /dev/null > > +++ b/drivers/irqchip/irq-riscv-aplic-main.h > > @@ -0,0 +1,45 @@ > > +/* SPDX-License-Identifier: GPL-2.0-only */ > > +/* > > + * Copyright (C) 2021 Western Digital Corporation or its affiliates. > > + * Copyright (C) 2022 Ventana Micro Systems Inc. > > + */ > > + > > +#ifndef _IRQ_RISCV_APLIC_MAIN_H > > +#define _IRQ_RISCV_APLIC_MAIN_H > > + > > +#include <linux/device.h> > > +#include <linux/io.h> > > +#include <linux/irq.h> > > +#include <linux/irqdomain.h> > > +#include <linux/fwnode.h> > > + > > +#define APLIC_DEFAULT_PRIORITY 1 > > + > > +struct aplic_msicfg { > > + phys_addr_t base_ppn; > > + u32 hhxs; > > + u32 hhxw; > > + u32 lhxs; > > + u32 lhxw; > > +}; > > + > > +struct aplic_priv { > > + struct device *dev; > > + u32 gsi_base; > > + u32 nr_irqs; > > + u32 nr_idcs; > > + void __iomem *regs; > > + struct aplic_msicfg msicfg; > > +}; > > + > > +void aplic_irq_unmask(struct irq_data *d); > > +void aplic_irq_mask(struct irq_data *d); > > +int aplic_irq_set_type(struct irq_data *d, unsigned int type); > > +int aplic_irqdomain_translate(struct irq_fwspec *fwspec, u32 gsi_base, > > + unsigned long *hwirq, unsigned int *type); > > +void aplic_init_hw_global(struct aplic_priv *priv, bool msi_mode); > > +int aplic_setup_priv(struct aplic_priv *priv, struct device *dev, > > + void __iomem *regs); > > +int aplic_direct_setup(struct device *dev, void __iomem *regs); > > + > > +#endif > > diff --git a/include/linux/irqchip/riscv-aplic.h b/include/linux/irqchip/riscv-aplic.h > > new file mode 100644 > > index 000000000000..97e198ea0109 > > --- /dev/null > > +++ b/include/linux/irqchip/riscv-aplic.h > > @@ -0,0 +1,119 @@ > > +/* SPDX-License-Identifier: GPL-2.0-only */ > > +/* > > + * Copyright (C) 2021 Western Digital Corporation or its affiliates. > > + * Copyright (C) 2022 Ventana Micro Systems Inc. > > + */ > > +#ifndef __LINUX_IRQCHIP_RISCV_APLIC_H > > +#define __LINUX_IRQCHIP_RISCV_APLIC_H > > + > > +#include <linux/bitops.h> > > + > > +#define APLIC_MAX_IDC BIT(14) > > +#define APLIC_MAX_SOURCE 1024 > > + > > +#define APLIC_DOMAINCFG 0x0000 > > +#define APLIC_DOMAINCFG_RDONLY 0x80000000 > > +#define APLIC_DOMAINCFG_IE BIT(8) > > +#define APLIC_DOMAINCFG_DM BIT(2) > > +#define APLIC_DOMAINCFG_BE BIT(0) > > + > > +#define APLIC_SOURCECFG_BASE 0x0004 > > +#define APLIC_SOURCECFG_D BIT(10) > > +#define APLIC_SOURCECFG_CHILDIDX_MASK 0x000003ff > > +#define APLIC_SOURCECFG_SM_MASK 0x00000007 > > +#define APLIC_SOURCECFG_SM_INACTIVE 0x0 > > +#define APLIC_SOURCECFG_SM_DETACH 0x1 > > +#define APLIC_SOURCECFG_SM_EDGE_RISE 0x4 > > +#define APLIC_SOURCECFG_SM_EDGE_FALL 0x5 > > +#define APLIC_SOURCECFG_SM_LEVEL_HIGH 0x6 > > +#define APLIC_SOURCECFG_SM_LEVEL_LOW 0x7 > > + > > +#define APLIC_MMSICFGADDR 0x1bc0 > > +#define APLIC_MMSICFGADDRH 0x1bc4 > > +#define APLIC_SMSICFGADDR 0x1bc8 > > +#define APLIC_SMSICFGADDRH 0x1bcc > > + > > +#ifdef CONFIG_RISCV_M_MODE > > +#define APLIC_xMSICFGADDR APLIC_MMSICFGADDR > > +#define APLIC_xMSICFGADDRH APLIC_MMSICFGADDRH > > +#else > > +#define APLIC_xMSICFGADDR APLIC_SMSICFGADDR > > +#define APLIC_xMSICFGADDRH APLIC_SMSICFGADDRH > > +#endif > > + > > +#define APLIC_xMSICFGADDRH_L BIT(31) > > +#define APLIC_xMSICFGADDRH_HHXS_MASK 0x1f > > +#define APLIC_xMSICFGADDRH_HHXS_SHIFT 24 > > +#define APLIC_xMSICFGADDRH_LHXS_MASK 0x7 > > +#define APLIC_xMSICFGADDRH_LHXS_SHIFT 20 > > +#define APLIC_xMSICFGADDRH_HHXW_MASK 0x7 > > +#define APLIC_xMSICFGADDRH_HHXW_SHIFT 16 > > +#define APLIC_xMSICFGADDRH_LHXW_MASK 0xf > > +#define APLIC_xMSICFGADDRH_LHXW_SHIFT 12 > > +#define APLIC_xMSICFGADDRH_BAPPN_MASK 0xfff > > + > > +#define APLIC_xMSICFGADDR_PPN_SHIFT 12 > > + > > +#define APLIC_xMSICFGADDR_PPN_HART(__lhxs) \ > > + (BIT(__lhxs) - 1) > > + > > +#define APLIC_xMSICFGADDR_PPN_LHX_MASK(__lhxw) \ > > + (BIT(__lhxw) - 1) > > +#define APLIC_xMSICFGADDR_PPN_LHX_SHIFT(__lhxs) \ > > + ((__lhxs)) > > +#define APLIC_xMSICFGADDR_PPN_LHX(__lhxw, __lhxs) \ > > + (APLIC_xMSICFGADDR_PPN_LHX_MASK(__lhxw) << \ > > + APLIC_xMSICFGADDR_PPN_LHX_SHIFT(__lhxs)) > > + > > +#define APLIC_xMSICFGADDR_PPN_HHX_MASK(__hhxw) \ > > + (BIT(__hhxw) - 1) > > +#define APLIC_xMSICFGADDR_PPN_HHX_SHIFT(__hhxs) \ > > + ((__hhxs) + APLIC_xMSICFGADDR_PPN_SHIFT) > > +#define APLIC_xMSICFGADDR_PPN_HHX(__hhxw, __hhxs) \ > > + (APLIC_xMSICFGADDR_PPN_HHX_MASK(__hhxw) << \ > > + APLIC_xMSICFGADDR_PPN_HHX_SHIFT(__hhxs)) > > + > > +#define APLIC_IRQBITS_PER_REG 32 > > + > > +#define APLIC_SETIP_BASE 0x1c00 > > +#define APLIC_SETIPNUM 0x1cdc > > + > > +#define APLIC_CLRIP_BASE 0x1d00 > > +#define APLIC_CLRIPNUM 0x1ddc > > + > > +#define APLIC_SETIE_BASE 0x1e00 > > +#define APLIC_SETIENUM 0x1edc > > + > > +#define APLIC_CLRIE_BASE 0x1f00 > > +#define APLIC_CLRIENUM 0x1fdc > > + > > +#define APLIC_SETIPNUM_LE 0x2000 > > +#define APLIC_SETIPNUM_BE 0x2004 > > + > > +#define APLIC_GENMSI 0x3000 > > + > > +#define APLIC_TARGET_BASE 0x3004 > > +#define APLIC_TARGET_HART_IDX_SHIFT 18 > > +#define APLIC_TARGET_HART_IDX_MASK 0x3fff > > +#define APLIC_TARGET_GUEST_IDX_SHIFT 12 > > +#define APLIC_TARGET_GUEST_IDX_MASK 0x3f > > +#define APLIC_TARGET_IPRIO_MASK 0xff > > +#define APLIC_TARGET_EIID_MASK 0x7ff > > + > > +#define APLIC_IDC_BASE 0x4000 > > +#define APLIC_IDC_SIZE 32 > > + > > +#define APLIC_IDC_IDELIVERY 0x00 > > + > > +#define APLIC_IDC_IFORCE 0x04 > > + > > +#define APLIC_IDC_ITHRESHOLD 0x08 > > + > > +#define APLIC_IDC_TOPI 0x18 > > +#define APLIC_IDC_TOPI_ID_SHIFT 16 > > +#define APLIC_IDC_TOPI_ID_MASK 0x3ff > > +#define APLIC_IDC_TOPI_PRIO_MASK 0xff > > + > > +#define APLIC_IDC_CLAIMI 0x1c > > + > > +#endif > > -- > > 2.34.1 > > Regards, Anup