| Message ID | 20230829135818.2219438-1-quic_ipkumar@quicinc.com |
|---|---|
| Headers | show |
| Series | Enable USB3 for IPQ5332 | expand |
On Tue, 29 Aug 2023 at 17:00, Praveenkumar I <quic_ipkumar@quicinc.com> wrote: > > This patch updates the UNIPHY driver to be a common driver to > accommodate all UNIPHY / Combo PHY. This driver can be used for > both USB and PCIe UNIPHY. Using phy-mul-sel from DTS MUX selection > for USB / PCIe can be acheived. I'm not sure why you are talking about PCIe here. This patch adds only SS PHY support. Also, I'd like to point out that we had this 'USB and PCIe and everything else' design in the QMP driver. We had to split the driver into individual pieces to make it manageable again. > > Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> > --- > drivers/phy/qualcomm/phy-qcom-uniphy.c | 401 +++++++++++++++++++++---- > 1 file changed, 335 insertions(+), 66 deletions(-) > > diff --git a/drivers/phy/qualcomm/phy-qcom-uniphy.c b/drivers/phy/qualcomm/phy-qcom-uniphy.c > index da6f290af722..eb71588f5417 100644 > --- a/drivers/phy/qualcomm/phy-qcom-uniphy.c > +++ b/drivers/phy/qualcomm/phy-qcom-uniphy.c > @@ -5,141 +5,410 @@ > * Based on code from > * Allwinner Technology Co., Ltd. <www.allwinnertech.com> > * > + * Modified the driver to be common for Qualcomm UNIPHYs > + * Copyright (c) 2023, The Linux Foundation. All rights reserved. I'd not call this 'modified', but rather 'rewritten from scratch. > */ > > +#include <linux/bitfield.h> > +#include <linux/clk.h> > +#include <linux/clk-provider.h> > #include <linux/delay.h> > #include <linux/err.h> > #include <linux/io.h> > #include <linux/kernel.h> > +#include <linux/mfd/syscon.h> > #include <linux/module.h> > #include <linux/mutex.h> > #include <linux/of.h> > #include <linux/phy/phy.h> > #include <linux/platform_device.h> > +#include <linux/regmap.h> > +#include <linux/regulator/consumer.h> > #include <linux/reset.h> > > -struct ipq4019_usb_phy { > +struct uniphy_init_tbl { > + unsigned int offset; > + unsigned int val; > +}; unused > + > +#define UNIPHY_INIT_CFG(o, v) \ > + { \ > + .offset = o, \ > + .val = v, \ > + } unused > + > +struct uniphy_cfg { > + const struct uniphy_init_tbl *init_seq; > + int num_init_seq; > + const char * const *clk_list; > + int num_clks; > + const char * const *reset_list; > + int num_resets; > + const char * const *vreg_list; > + int num_vregs; > + unsigned int pipe_clk_rate; > + unsigned int reset_udelay; > + unsigned int autoload_udelay; > +}; > + > +struct qcom_uniphy { > struct device *dev; > + const struct uniphy_cfg *cfg; > struct phy *phy; > void __iomem *base; > - struct reset_control *por_rst; > - struct reset_control *srif_rst; > + struct clk_bulk_data *clks; > + struct reset_control_bulk_data *resets; > + struct regulator_bulk_data *vregs; > + struct clk_fixed_rate pipe_clk_fixed; > +}; > + > +static const char * const ipq4019_ssphy_reset_l[] = { > + "por_rst", > +}; > + > +static const struct uniphy_cfg ipq4019_usb_ssphy_cfg = { > + .reset_list = ipq4019_ssphy_reset_l, > + .num_resets = ARRAY_SIZE(ipq4019_ssphy_reset_l), > + .reset_udelay = 10000, > + > }; > > -static int ipq4019_ss_phy_power_off(struct phy *_phy) > +static const char * const ipq4019_hsphy_reset_l[] = { > + "por_rst", "srif_rst", > +}; + > +static const struct uniphy_cfg ipq4019_usb_hsphy_cfg = { > + .reset_list = ipq4019_hsphy_reset_l, > + .num_resets = ARRAY_SIZE(ipq4019_hsphy_reset_l), > + .reset_udelay = 10000, > +}; > + > +static int phy_mux_sel(struct phy *phy) > +{ > + struct qcom_uniphy *uniphy = phy_get_drvdata(phy); > + struct device *dev = uniphy->dev; > + struct regmap *tcsr; > + unsigned int args[2]; > + int ret; > + > + tcsr = syscon_regmap_lookup_by_phandle_args(dev->of_node, "qcom,phy-mux-sel", > + ARRAY_SIZE(args), args); No. mux data should come from match_data rather than polluting DT with it. > + if (IS_ERR(tcsr)) { > + ret = PTR_ERR(tcsr); > + if (ret == -ENOENT) > + return 0; > + > + dev_err(dev, "failed to lookup syscon for phy mux %d\n", ret); > + return ret; > + } > + > + /* PHY MUX registers only have this BIT0 */ huh? > + ret = regmap_write(tcsr, args[0], args[1]); > + if (ret < 0) { > + dev_err(dev, "PHY Mux selection failed: %d\n", ret); > + return ret; > + } > + > + return 0; > +} > + > +static int uniphy_enable(struct phy *phy) > { > - struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy); > + struct qcom_uniphy *uniphy = phy_get_drvdata(phy); > + const struct uniphy_cfg *cfg = uniphy->cfg; > + const struct uniphy_init_tbl *tbl; > + void __iomem *base = uniphy->base; > + int i, ret; > > - reset_control_assert(phy->por_rst); > - msleep(10); > + ret = regulator_bulk_enable(cfg->num_vregs, uniphy->vregs); > + if (ret) { > + dev_err(uniphy->dev, "failed to enable regulators: %d\n", ret); > + return ret; > + } > + > + /* Assert all available resets */ > + for (i = 0; i < cfg->num_resets; i++) { > + ret = reset_control_assert(uniphy->resets[i].rstc); > + if (ret) { > + dev_err(uniphy->dev, "reset assert failed: %d\n", ret); > + goto err_assert_reset; > + } > + if (cfg->reset_udelay) > + usleep_range(cfg->reset_udelay, cfg->reset_udelay + 10); > + } There is a whole reset_control_bulk_*() set of API. Please use it instead of hardcoding reset cycles. > + > + /* Deassert all available resets */ > + for (i = 0; i < cfg->num_resets; i++) { > + ret = reset_control_deassert(uniphy->resets[i].rstc); > + if (ret) { > + dev_err(uniphy->dev, "reset deassert failed: %d\n", ret); > + goto err_assert_reset; > + } > + if (cfg->reset_udelay) > + usleep_range(cfg->reset_udelay, cfg->reset_udelay + 10); > + } > + > + ret = phy_mux_sel(phy); > + if (ret < 0) > + goto err_assert_reset; > + > + ret = clk_bulk_prepare_enable(cfg->num_clks, uniphy->clks); > + if (ret) { > + dev_err(uniphy->dev, "failed to enable clocks: %d\n", ret); > + goto err_assert_reset; > + } > + > + if (cfg->autoload_udelay) > + usleep_range(cfg->autoload_udelay, cfg->autoload_udelay + 10); > + > + if (cfg->num_init_seq) { > + tbl = cfg->init_seq; > + for (i = 0; i < cfg->num_init_seq; i++, tbl++) > + writel(tbl->val, base + tbl->offset); > + } unused > > return 0; > + > +err_assert_reset: > + /* Assert all available resets */ > + for (i = 0; i < cfg->num_resets; i++) { > + reset_control_assert(uniphy->resets[i].rstc); > + if (cfg->reset_udelay) > + usleep_range(cfg->reset_udelay, cfg->reset_udelay + 10); > + } > + > + return ret; > } > > -static int ipq4019_ss_phy_power_on(struct phy *_phy) > +static int uniphy_disable(struct phy *phy) > { > - struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy); > + struct qcom_uniphy *uniphy = phy_get_drvdata(phy); > + const struct uniphy_cfg *cfg = uniphy->cfg; > + int i; > > - ipq4019_ss_phy_power_off(_phy); > + /* Assert all available resets */ > + for (i = 0; i < cfg->num_resets; i++) { > + reset_control_assert(uniphy->resets[i].rstc); > + if (cfg->reset_udelay) > + usleep_range(cfg->reset_udelay, cfg->reset_udelay + 10); > + } > > - reset_control_deassert(phy->por_rst); > + clk_bulk_disable_unprepare(cfg->num_clks, uniphy->clks); > + > + regulator_bulk_disable(cfg->num_vregs, uniphy->vregs); > > return 0; > } > > -static const struct phy_ops ipq4019_usb_ss_phy_ops = { > - .power_on = ipq4019_ss_phy_power_on, > - .power_off = ipq4019_ss_phy_power_off, > +static const struct phy_ops uniphy_phy_ops = { > + .power_on = uniphy_enable, > + .power_off = uniphy_disable, Using _enable / _disable for power_on() and power_off() isn't logical. > + .owner = THIS_MODULE, > }; > > -static int ipq4019_hs_phy_power_off(struct phy *_phy) > +static int qcom_uniphy_vreg_init(struct qcom_uniphy *uniphy) > +{ > + const struct uniphy_cfg *cfg = uniphy->cfg; > + struct device *dev = uniphy->dev; > + int i, ret; > + > + uniphy->vregs = devm_kcalloc(dev, cfg->num_vregs, > + sizeof(*uniphy->vregs), GFP_KERNEL); You know the maximum amount of regulators. Can you use an array instead of allocating data? > + if (!uniphy->vregs) > + return -ENOMEM; > + > + for (i = 0; i < cfg->num_vregs; i++) > + uniphy->vregs[i].supply = cfg->vreg_list[i]; > + > + ret = devm_regulator_bulk_get(dev, cfg->num_vregs, uniphy->vregs); > + Drop empty lines between ret assignment and check. > + if (ret) > + return dev_err_probe(dev, ret, "failed to get regulators\n"); > + > + return 0; > +} > + > +static int qcom_uniphy_reset_init(struct qcom_uniphy *uniphy) > { > - struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy); > + const struct uniphy_cfg *cfg = uniphy->cfg; > + struct device *dev = uniphy->dev; > + int i, ret; > + > + uniphy->resets = devm_kcalloc(dev, cfg->num_resets, > + sizeof(*uniphy->resets), GFP_KERNEL); Same here, can you use an array? > + if (!uniphy->resets) > + return -ENOMEM; > > - reset_control_assert(phy->por_rst); > - msleep(10); > + for (i = 0; i < cfg->num_resets; i++) > + uniphy->resets[i].id = cfg->reset_list[i]; Declare common resets list and use devm_reset_control_bulk_get_optional_exclusive(). > > - reset_control_assert(phy->srif_rst); > - msleep(10); > + ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, uniphy->resets); > + if (ret) > + return dev_err_probe(dev, ret, "failed to get resets\n"); > > return 0; > } > > -static int ipq4019_hs_phy_power_on(struct phy *_phy) > +static int qcom_uniphy_clk_init(struct qcom_uniphy *uniphy) I don't see clocks actually being used. Please do not introduce unused features. > { > - struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy); > + const struct uniphy_cfg *cfg = uniphy->cfg; > + struct device *dev = uniphy->dev; > + int i, ret; > > - ipq4019_hs_phy_power_off(_phy); > > - reset_control_deassert(phy->srif_rst); > - msleep(10); > + uniphy->clks = devm_kcalloc(dev, cfg->num_clks, > + sizeof(*uniphy->clks), GFP_KERNEL); > + if (!uniphy->clks) > + return -ENOMEM; > + > + for (i = 0; i < cfg->num_clks; i++) > + uniphy->clks[i].id = cfg->clk_list[i]; > > - reset_control_deassert(phy->por_rst); > + ret = devm_clk_bulk_get(dev, cfg->num_clks, uniphy->clks); > + if (ret) > + return dev_err_probe(dev, ret, "failed to get clocks\n"); > > return 0; > } > > -static const struct phy_ops ipq4019_usb_hs_phy_ops = { > - .power_on = ipq4019_hs_phy_power_on, > - .power_off = ipq4019_hs_phy_power_off, > -}; > +static void phy_clk_release_provider(void *res) > +{ > + of_clk_del_provider(res); > +} > > -static const struct of_device_id ipq4019_usb_phy_of_match[] = { > - { .compatible = "qcom,usb-hs-ipq4019-phy", .data = &ipq4019_usb_hs_phy_ops}, > - { .compatible = "qcom,usb-ss-ipq4019-phy", .data = &ipq4019_usb_ss_phy_ops}, > - { }, > -}; > -MODULE_DEVICE_TABLE(of, ipq4019_usb_phy_of_match); > +/* > + * Register a fixed rate pipe clock. > + * > + * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate > + * controls it. The <s>_pipe_clk coming out of the GCC is requested > + * by the PHY driver for its operations. > + * We register the <s>_pipe_clksrc here. The gcc driver takes care > + * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. > + * Below picture shows this relationship. > + * > + * +---------------+ > + * | PHY block |<<---------------------------------------+ > + * | | | > + * | +-------+ | +-----+ | > + * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ > + * clk | +-------+ | +-----+ > + * +---------------+ > + */ > +static int phy_pipe_clk_register(struct qcom_uniphy *uniphy, struct device_node *np) > +{ > + struct clk_fixed_rate *fixed = &uniphy->pipe_clk_fixed; > + const struct uniphy_cfg *cfg = uniphy->cfg; > + struct device *dev = uniphy->dev; > + struct clk_init_data init = { }; > + int ret; > + > + ret = of_property_read_string(np, "clock-output-names", &init.name); > + if (ret) { > + dev_err(dev, "%pOFn: No clock-output-names\n", np); > + return ret; > + } > + > + init.ops = &clk_fixed_rate_ops; > + > + fixed->fixed_rate = cfg->pipe_clk_rate; > + fixed->hw.init = &init; > > -static int ipq4019_usb_phy_probe(struct platform_device *pdev) > + ret = devm_clk_hw_register(dev, &fixed->hw); > + if (ret) > + return ret; > + > + ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); > + if (ret) > + return ret; When you c&p something, please take care to understand the code you are copying. Unlike QMP drivers you can (and should) use devm_of_clk_add_hw_provider() here. Not to mention that pipe clocks are not in this patch. > + > + /* > + * Roll a devm action because the clock provider is the child node, but > + * the child node is not actually a device. > + */ > + return devm_add_action_or_reset(dev, phy_clk_release_provider, np); > +} > + > +static int qcom_uniphy_probe(struct platform_device *pdev) > { > struct device *dev = &pdev->dev; > struct phy_provider *phy_provider; > - struct ipq4019_usb_phy *phy; > + struct qcom_uniphy *uniphy; > + struct device_node *np; > + int ret; > > - phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); > - if (!phy) > + uniphy = devm_kzalloc(dev, sizeof(*uniphy), GFP_KERNEL); > + if (!uniphy) > return -ENOMEM; > > - phy->dev = &pdev->dev; > - phy->base = devm_platform_ioremap_resource(pdev, 0); > - if (IS_ERR(phy->base)) { > - dev_err(dev, "failed to remap register memory\n"); > - return PTR_ERR(phy->base); > - } > + uniphy->dev = dev; > > - phy->por_rst = devm_reset_control_get(phy->dev, "por_rst"); > - if (IS_ERR(phy->por_rst)) { > - if (PTR_ERR(phy->por_rst) != -EPROBE_DEFER) > - dev_err(dev, "POR reset is missing\n"); > - return PTR_ERR(phy->por_rst); > + uniphy->cfg = of_device_get_match_data(dev); > + if (!uniphy->cfg) > + return -EINVAL; > + > + uniphy->base = devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(uniphy->base)) { > + ret = PTR_ERR(uniphy->base); > + dev_err_probe(dev, ret, "failed to remap register memory\n"); > + return ret; > } > > - phy->srif_rst = devm_reset_control_get_optional(phy->dev, "srif_rst"); > - if (IS_ERR(phy->srif_rst)) > - return PTR_ERR(phy->srif_rst); > + ret = qcom_uniphy_clk_init(uniphy); > + if (ret) > + return ret; > + > + ret = qcom_uniphy_reset_init(uniphy); > + if (ret) > + return ret; > + > + ret = qcom_uniphy_vreg_init(uniphy); > + if (ret < 0) > + return ret; > + > + if (uniphy->cfg->pipe_clk_rate) { > + np = of_node_get(dev->of_node); What for? Do you think that the driver can outlive struct device? > + ret = phy_pipe_clk_register(uniphy, np); > + if (ret) { > + dev_err_probe(dev, ret, "failed to register pipe clk\n"); > + goto err; > + } > + } > > - phy->phy = devm_phy_create(dev, NULL, of_device_get_match_data(dev)); > - if (IS_ERR(phy->phy)) { > - dev_err(dev, "failed to create PHY\n"); > - return PTR_ERR(phy->phy); > + uniphy->phy = devm_phy_create(dev, NULL, &uniphy_phy_ops); > + if (IS_ERR(uniphy->phy)) { > + ret = PTR_ERR(uniphy->phy); > + dev_err_probe(dev, ret, "failed to create PHY\n"); > + goto err; > } > - phy_set_drvdata(phy->phy, phy); > + > + phy_set_drvdata(uniphy->phy, uniphy); > > phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); > > - return PTR_ERR_OR_ZERO(phy_provider); > + ret = PTR_ERR_OR_ZERO(phy_provider); > + > +err: > + if (uniphy->cfg->pipe_clk_rate) > + of_node_put(np); > + return ret; > } > > -static struct platform_driver ipq4019_usb_phy_driver = { > - .probe = ipq4019_usb_phy_probe, > +static const struct of_device_id qcom_uniphy_of_match[] = { > + { .compatible = "qcom,usb-hs-ipq4019-phy", .data = &ipq4019_usb_hsphy_cfg}, > + { .compatible = "qcom,usb-ss-ipq4019-phy", .data = &ipq4019_usb_ssphy_cfg}, > + { }, > +}; > +MODULE_DEVICE_TABLE(of, qcom_uniphy_of_match); > + > +static struct platform_driver qcom_uniphy_driver = { > + .probe = qcom_uniphy_probe, > .driver = { > - .of_match_table = ipq4019_usb_phy_of_match, > - .name = "ipq4019-usb-phy", > + .of_match_table = qcom_uniphy_of_match, > + .name = "qcom-uniphy", > } > }; > -module_platform_driver(ipq4019_usb_phy_driver); > +module_platform_driver(qcom_uniphy_driver); > > -MODULE_DESCRIPTION("QCOM/IPQ4019 USB phy driver"); > +MODULE_DESCRIPTION("QCOM uniphy driver"); > MODULE_AUTHOR("John Crispin <john@phrozen.org>"); > MODULE_LICENSE("GPL v2"); General comment: please consider dropping this beast and starting from scratch, adding only really necessary bits to the existing ipq4019 USB PHY driver.
On Tue, 29 Aug 2023 at 17:00, Praveenkumar I <quic_ipkumar@quicinc.com> wrote: > > This patch adds ipq5332 USB SS UNIPHY support. First, please read to Documentation/process/submitting-patches.rst, then rewrite the commit message. Next, I tend to say that this driver doesn't have a lot in common with the ipq4019 driver you have modified. Please consider adding new driver for ipq5332, then we can see whether it makes sense to fold ipq4019 to use new infrastructure. > > Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> > --- > This patch depends on the below series which adds support for USB2 in > IPQ5332 > https://lore.kernel.org/all/cover.1692699472.git.quic_varada@quicinc.com/ > > drivers/phy/qualcomm/phy-qcom-uniphy.c | 37 ++++++++++++++++++++++++++ > 1 file changed, 37 insertions(+) > > diff --git a/drivers/phy/qualcomm/phy-qcom-uniphy.c b/drivers/phy/qualcomm/phy-qcom-uniphy.c > index eb71588f5417..91487e68bb6e 100644 > --- a/drivers/phy/qualcomm/phy-qcom-uniphy.c > +++ b/drivers/phy/qualcomm/phy-qcom-uniphy.c > @@ -26,6 +26,10 @@ > #include <linux/regulator/consumer.h> > #include <linux/reset.h> > > +#define PCIE_USB_COMBO_PHY_CFG_MISC1 0x214 > +#define PCIE_USB_COMBO_PHY_CFG_RX_AFE_2 0x7C4 > +#define PCIE_USB_COMBO_PHY_CFG_RX_DLF_DEMUX_2 0x7E8 > + > struct uniphy_init_tbl { > unsigned int offset; > unsigned int val; > @@ -37,6 +41,12 @@ struct uniphy_init_tbl { > .val = v, \ > } > > +static const struct uniphy_init_tbl ipq5332_usb_ssphy_init_tbl[] = { > + UNIPHY_INIT_CFG(PCIE_USB_COMBO_PHY_CFG_RX_AFE_2, 0x1076), > + UNIPHY_INIT_CFG(PCIE_USB_COMBO_PHY_CFG_RX_DLF_DEMUX_2, 0x3142), > + UNIPHY_INIT_CFG(PCIE_USB_COMBO_PHY_CFG_MISC1, 0x3), > +}; > + > struct uniphy_cfg { > const struct uniphy_init_tbl *init_seq; > int num_init_seq; > @@ -83,6 +93,32 @@ static const struct uniphy_cfg ipq4019_usb_hsphy_cfg = { > .reset_udelay = 10000, > }; > > +static const char * const ipq5332_usb_ssphy_clk_l[] = { > + "phy_ahb", "phy_cfg_ahb", "pipe", > +}; > + > +static const char * const ipq5332_usb_ssphy_reset_l[] = { > + "por_rst", > +}; > + > +static const char * const ipq5332_usb_ssphy_vreg_l[] = { > + "vdda-phy", > +}; > + > +static const struct uniphy_cfg ipq5332_usb_ssphy_cfg = { > + .init_seq = ipq5332_usb_ssphy_init_tbl, > + .num_init_seq = ARRAY_SIZE(ipq5332_usb_ssphy_init_tbl), > + .clk_list = ipq5332_usb_ssphy_clk_l, > + .num_clks = ARRAY_SIZE(ipq5332_usb_ssphy_clk_l), > + .reset_list = ipq5332_usb_ssphy_reset_l, > + .num_resets = ARRAY_SIZE(ipq5332_usb_ssphy_reset_l), > + .vreg_list = ipq5332_usb_ssphy_vreg_l, > + .num_vregs = ARRAY_SIZE(ipq5332_usb_ssphy_vreg_l), > + .pipe_clk_rate = 250000000, > + .reset_udelay = 1, > + .autoload_udelay = 35, > +}; > + > static int phy_mux_sel(struct phy *phy) > { > struct qcom_uniphy *uniphy = phy_get_drvdata(phy); > @@ -396,6 +432,7 @@ static int qcom_uniphy_probe(struct platform_device *pdev) > static const struct of_device_id qcom_uniphy_of_match[] = { > { .compatible = "qcom,usb-hs-ipq4019-phy", .data = &ipq4019_usb_hsphy_cfg}, > { .compatible = "qcom,usb-ss-ipq4019-phy", .data = &ipq4019_usb_ssphy_cfg}, > + { .compatible = "qcom,ipq5332-usb-ssphy", .data = &ipq5332_usb_ssphy_cfg}, > { }, > }; > MODULE_DEVICE_TABLE(of, qcom_uniphy_of_match); > -- > 2.34.1
On Tue, 29 Aug 2023 at 17:00, Praveenkumar I <quic_ipkumar@quicinc.com> wrote: > > Add SS UNIPHY and update controller node for USB3. > > Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> > --- > This patch depends on the below series which adds support for USB2 in > IPQ5332 > https://lore.kernel.org/all/cover.1692699472.git.quic_varada@quicinc.com/ > > arch/arm64/boot/dts/qcom/ipq5332.dtsi | 39 ++++++++++++++++++++++----- > 1 file changed, 32 insertions(+), 7 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi > index e6baf694488c..7fbe6c9f4784 100644 > --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi > @@ -158,6 +158,27 @@ usbphy0: phy@7b000 { > status = "disabled"; > }; > > + ssuniphy0: ssuniphy@4b0000 { > + compatible = "qcom,ipq5332-usb-ssphy"; > + reg = <0x4b0000 0x800>; > + clocks = <&gcc GCC_USB0_PIPE_CLK>, > + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, > + <&gcc GCC_PCIE3X1_PHY_AHB_CLK>; > + > + #clock-cells = <0>; > + clock-output-names = "usb_pcie_wrapper_pipe_clk"; > + > + clock-names = "pipe", > + "phy_cfg_ahb", > + "phy_ahb"; > + > + resets = <&gcc GCC_USB0_PHY_BCR>; > + reset-names = "por_rst"; > + #phy-cells = <0>; > + qcom,phy-mux-sel = <&tcsr 0x10540 0x1>; > + status = "disabled"; > + }; > + > qfprom: efuse@a4000 { > compatible = "qcom,ipq5332-qfprom", "qcom,qfprom"; > reg = <0x000a4000 0x721>; > @@ -313,30 +334,34 @@ usb: usb@8a00000 { > clocks = <&gcc GCC_USB0_MASTER_CLK>, > <&gcc GCC_SNOC_USB_CLK>, > <&gcc GCC_USB0_SLEEP_CLK>, > - <&gcc GCC_USB0_MOCK_UTMI_CLK>; > + <&gcc GCC_USB0_MOCK_UTMI_CLK>, > + <&gcc GCC_USB0_AUX_CLK>, > + <&gcc GCC_USB0_LFPS_CLK>; > + > clock-names = "core", > "iface", > "sleep", > - "mock_utmi"; > + "mock_utmi", > + "aux", > + "lfps"; > > resets = <&gcc GCC_USB_BCR>; > > - qcom,select-utmi-as-pipe-clk; > - > #address-cells = <1>; > #size-cells = <1>; > ranges; > > status = "disabled"; > > - usb2_0_dwc: usb@8a00000 { > + usb3_0_dwc: usb@8a00000 { At this point you have broken compilation of all ipq5332 DT files. Don't. The kernel should be bisectable. At each point, after each commit it should compile and work. > compatible = "snps,dwc3"; > reg = <0x08a00000 0xe000>; > clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; > clock-names = "ref"; > interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; > - phy-names = "usb2-phy"; > - phys = <&usbphy0>; > + phy-names = "usb2-phy", "usb3-phy"; > + phys = <&usbphy0>, <&ssuniphy0>; > + > tx-fifo-resize; > snps,is-utmi-l1-suspend; > snps,hird-threshold = /bits/ 8 <0x0>; > -- > 2.34.1 >
On 29/08/2023 15:58, Praveenkumar I wrote: > UNIPHY / Combo PHY used on various qualcomm SoC's are very similar to > ipq4019 PHY. Hence renaming this driver to uniphy driver and can be > used for other SoC's which are having the similar UNIPHY. > > Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> > --- > MAINTAINERS | 7 ++++--- > drivers/phy/qualcomm/Kconfig | 7 ++++--- > drivers/phy/qualcomm/Makefile | 2 +- > .../qualcomm/{phy-qcom-ipq4019-usb.c => phy-qcom-uniphy.c} | 0 > 4 files changed, 9 insertions(+), 7 deletions(-) > rename drivers/phy/qualcomm/{phy-qcom-ipq4019-usb.c => phy-qcom-uniphy.c} (100%) > > diff --git a/MAINTAINERS b/MAINTAINERS > index ff1f273b4f36..7f4553c1a69a 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -17774,13 +17774,14 @@ F: Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml > F: drivers/mailbox/qcom-ipcc.c > F: include/dt-bindings/mailbox/qcom-ipcc.h > > -QUALCOMM IPQ4019 USB PHY DRIVER > +QUALCOMM UNIPHY DRIVER > M: Robert Marko <robert.marko@sartura.hr> > M: Luka Perkov <luka.perkov@sartura.hr> > +M: Praveenkumar I <quic_ipkumar@quicinc.com> > L: linux-arm-msm@vger.kernel.org > S: Maintained > -F: Documentation/devicetree/bindings/phy/qcom-usb-ipq4019-phy.yaml > -F: drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c > +F: Documentation/devicetree/bindings/phy/qcom,uniphy.yaml You broke the path in your previous commit, but anyway this will go away. > +F: drivers/phy/qualcomm/phy-qcom-uniphy.c > > QUALCOMM IPQ4019 VQMMC REGULATOR DRIVER > M: Robert Marko <robert.marko@sartura.hr> > diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig > index d891058b7c39..e6981bc212b3 100644 > --- a/drivers/phy/qualcomm/Kconfig > +++ b/drivers/phy/qualcomm/Kconfig > @@ -28,12 +28,13 @@ config PHY_QCOM_EDP > Enable this driver to support the Qualcomm eDP PHY found in various > Qualcomm chipsets. > > -config PHY_QCOM_IPQ4019_USB > - tristate "Qualcomm IPQ4019 USB PHY driver" > +config PHY_QCOM_UNIPHY > + tristate "Qualcomm UNIPHY driver" > depends on OF && (ARCH_QCOM || COMPILE_TEST) > select GENERIC_PHY > help > - Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s. > + Enable this driver to support the Qualcomm UNIPHY found in various > + Qualcomm chipsets. I don't quite get why this is renamed, either. Just because you re-use it? Re-usage is not affected with old name... Best regards, Krzysztof
On 29/08/2023 15:58, Praveenkumar I wrote: > This patch updates the UNIPHY driver to be a common driver to Please do not use "This commit/patch", but imperative mood. See longer explanation here: https://elixir.bootlin.com/linux/v5.17.1/source/Documentation/process/submitting-patches.rst#L95 > accommodate all UNIPHY / Combo PHY. This driver can be used for > both USB and PCIe UNIPHY. Using phy-mul-sel from DTS MUX selection > for USB / PCIe can be acheived. This patch is entirely unreadable. You speak "unify" but change much more. There is no code removal, so what are you unifying? ... > - phy->phy = devm_phy_create(dev, NULL, of_device_get_match_data(dev)); > - if (IS_ERR(phy->phy)) { > - dev_err(dev, "failed to create PHY\n"); > - return PTR_ERR(phy->phy); > + uniphy->phy = devm_phy_create(dev, NULL, &uniphy_phy_ops); NAK, really, this does not make sense, is not explained and not needed. If needed, then it would deserve its own patch with own justification. > + if (IS_ERR(uniphy->phy)) { > + ret = PTR_ERR(uniphy->phy); > + dev_err_probe(dev, ret, "failed to create PHY\n"); That's not even the syntax. By "unifying" you introduce different, wrong code. > + goto err; > } > - phy_set_drvdata(phy->phy, phy); > + > + phy_set_drvdata(uniphy->phy, uniphy); > > phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); > > - return PTR_ERR_OR_ZERO(phy_provider); > + ret = PTR_ERR_OR_ZERO(phy_provider); > + > +err: > + if (uniphy->cfg->pipe_clk_rate) > + of_node_put(np); > + return ret; > } > > -static struct platform_driver ipq4019_usb_phy_driver = { > - .probe = ipq4019_usb_phy_probe, > +static const struct of_device_id qcom_uniphy_of_match[] = { > + { .compatible = "qcom,usb-hs-ipq4019-phy", .data = &ipq4019_usb_hsphy_cfg}, > + { .compatible = "qcom,usb-ss-ipq4019-phy", .data = &ipq4019_usb_ssphy_cfg}, > + { }, > +}; > +MODULE_DEVICE_TABLE(of, qcom_uniphy_of_match); What happens here? Best regards, Krzysztof
On 29/08/2023 15:58, Praveenkumar I wrote: > Add SS UNIPHY and update controller node for USB3. > > Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> > --- > This patch depends on the below series which adds support for USB2 in > IPQ5332 > https://lore.kernel.org/all/cover.1692699472.git.quic_varada@quicinc.com/ > > arch/arm64/boot/dts/qcom/ipq5332.dtsi | 39 ++++++++++++++++++++++----- > 1 file changed, 32 insertions(+), 7 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi > index e6baf694488c..7fbe6c9f4784 100644 > --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi > @@ -158,6 +158,27 @@ usbphy0: phy@7b000 { > status = "disabled"; > }; > > + ssuniphy0: ssuniphy@4b0000 { From where did you get such pattern of node naming? Downstream, right? Please, do not work on downstream but upstream. Node names should be generic. See also an explanation and list of examples (not exhaustive) in DT specification: https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation Best regards, Krzysztof
On 29/08/2023 15:58, Praveenkumar I wrote: > Enable USB3 SS UNIPHY and update USB node name. > > Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> > --- > This patch depends on the below series which adds support for USB2 in > IPQ5332 > https://lore.kernel.org/all/cover.1692699472.git.quic_varada@quicinc.com/ > > arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts > index 53696f4b46fc..c450153cfaac 100644 > --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts > +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts > @@ -95,10 +95,15 @@ &usbphy0 { > status = "okay"; > }; > > +&ssuniphy0 { > + vdd-supply = <®ulator_fixed_5p0>; > + status = "okay"; > +}; > + > &usb { > status = "okay"; > }; > > -&usb2_0_dwc { > +&usb3_0_dwc { This means previous patch was not even built. Sorry, that's bad. Please test your commits before sending. Best regards, Krzysztof
On 29/08/2023 15:58, Praveenkumar I wrote: > Enable UNIPHY driver for IPQ5322. This we see from the diff. You *must* say *why*, not *what*. Samsung IPQ5322 or NXP IPQ5322? Which boards need it? > > Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> > --- > This patch depends on the below series which adds support for USB2 in > IPQ5332 > https://lore.kernel.org/all/cover.1692699472.git.quic_varada@quicinc.com/ > How does it depend? Obviously it is part of the series, but what is depending here? Best regards, Krzysztof
On 29/08/2023 15:58, Praveenkumar I wrote: > IPQ5332 has UNIPHY for USB and PCIe which is similar to the UNIPHY > present in IPQ4019. Few extra settings like clock, reset delay, mux > selection and voltage regulator are required for IPQ5332. Hence > repurposed the IPQ4019 PHY driver for IPQ5332 UNIPHY. Few more Qualcomm > SoCs are also having the UNIPHY which can use the same driver for both > USB and PCIe PHY. > > Praveenkumar I (9): > dt-bindings: phy: qcom,uniphy: Rename ipq4019 usb PHY to UNIPHY > phy: qcom: uniphy: Rename ipq4019 USB phy driver to UNIPHY driver > phy: qcom: uniphy: Update UNIPHY driver to be a common driver > dt-bindings: phy: qcom,uniphy: Add ipq5332 USB3 SS UNIPHY > dt-bindings: usb: dwc3: Update IPQ5332 compatible > arm64: dts: qcom: ipq5332: Add USB3 related nodes > arm64: dts: qcom: ipq5332: Enable USB SS UNIPHY DTS does not go before drivers. DTS should be sent separately or as the last patches. If you stuff it in the middle, means your patchset has dependencies which it cannot have. Thus it is broken. Best regards, Krzysztof
On 8/29/2023 8:07 PM, Dmitry Baryshkov wrote: > On Tue, 29 Aug 2023 at 17:00, Praveenkumar I <quic_ipkumar@quicinc.com> wrote: >> This patch updates the UNIPHY driver to be a common driver to >> accommodate all UNIPHY / Combo PHY. This driver can be used for >> both USB and PCIe UNIPHY. Using phy-mul-sel from DTS MUX selection >> for USB / PCIe can be acheived. > I'm not sure why you are talking about PCIe here. This patch adds only > SS PHY support. > > Also, I'd like to point out that we had this 'USB and PCIe and > everything else' design in the QMP driver. We had to split the driver > into individual pieces to make it manageable again. This Uniphy 22ull is a combo PHY used between USB GEN3 or PCIe GEN3. Via mux selection the one of the controller interface can use it. Hence thought to have a same PHY driver for both USB3 and PCIe. Will drop the plan of adding the PCIe support. > >> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> >> --- >> drivers/phy/qualcomm/phy-qcom-uniphy.c | 401 +++++++++++++++++++++---- >> 1 file changed, 335 insertions(+), 66 deletions(-) >> >> diff --git a/drivers/phy/qualcomm/phy-qcom-uniphy.c b/drivers/phy/qualcomm/phy-qcom-uniphy.c >> index da6f290af722..eb71588f5417 100644 >> --- a/drivers/phy/qualcomm/phy-qcom-uniphy.c >> +++ b/drivers/phy/qualcomm/phy-qcom-uniphy.c >> @@ -5,141 +5,410 @@ >> * Based on code from >> * Allwinner Technology Co., Ltd. <www.allwinnertech.com> >> * >> + * Modified the driver to be common for Qualcomm UNIPHYs >> + * Copyright (c) 2023, The Linux Foundation. All rights reserved. > I'd not call this 'modified', but rather 'rewritten from scratch. Sure, will correct. > >> */ >> >> +#include <linux/bitfield.h> >> +#include <linux/clk.h> >> +#include <linux/clk-provider.h> >> #include <linux/delay.h> >> #include <linux/err.h> >> #include <linux/io.h> >> #include <linux/kernel.h> >> +#include <linux/mfd/syscon.h> >> #include <linux/module.h> >> #include <linux/mutex.h> >> #include <linux/of.h> >> #include <linux/phy/phy.h> >> #include <linux/platform_device.h> >> +#include <linux/regmap.h> >> +#include <linux/regulator/consumer.h> >> #include <linux/reset.h> >> >> -struct ipq4019_usb_phy { >> +struct uniphy_init_tbl { >> + unsigned int offset; >> + unsigned int val; >> +}; > unused > >> + >> +#define UNIPHY_INIT_CFG(o, v) \ >> + { \ >> + .offset = o, \ >> + .val = v, \ >> + } > unused > >> + >> +struct uniphy_cfg { >> + const struct uniphy_init_tbl *init_seq; >> + int num_init_seq; >> + const char * const *clk_list; >> + int num_clks; >> + const char * const *reset_list; >> + int num_resets; >> + const char * const *vreg_list; >> + int num_vregs; >> + unsigned int pipe_clk_rate; >> + unsigned int reset_udelay; >> + unsigned int autoload_udelay; >> +}; >> + >> +struct qcom_uniphy { >> struct device *dev; >> + const struct uniphy_cfg *cfg; >> struct phy *phy; >> void __iomem *base; >> - struct reset_control *por_rst; >> - struct reset_control *srif_rst; >> + struct clk_bulk_data *clks; >> + struct reset_control_bulk_data *resets; >> + struct regulator_bulk_data *vregs; >> + struct clk_fixed_rate pipe_clk_fixed; >> +}; >> + >> +static const char * const ipq4019_ssphy_reset_l[] = { >> + "por_rst", >> +}; >> + >> +static const struct uniphy_cfg ipq4019_usb_ssphy_cfg = { >> + .reset_list = ipq4019_ssphy_reset_l, >> + .num_resets = ARRAY_SIZE(ipq4019_ssphy_reset_l), >> + .reset_udelay = 10000, >> + >> }; >> >> -static int ipq4019_ss_phy_power_off(struct phy *_phy) >> +static const char * const ipq4019_hsphy_reset_l[] = { >> + "por_rst", "srif_rst", >> +}; > + >> +static const struct uniphy_cfg ipq4019_usb_hsphy_cfg = { >> + .reset_list = ipq4019_hsphy_reset_l, >> + .num_resets = ARRAY_SIZE(ipq4019_hsphy_reset_l), >> + .reset_udelay = 10000, >> +}; >> + >> +static int phy_mux_sel(struct phy *phy) >> +{ >> + struct qcom_uniphy *uniphy = phy_get_drvdata(phy); >> + struct device *dev = uniphy->dev; >> + struct regmap *tcsr; >> + unsigned int args[2]; >> + int ret; >> + >> + tcsr = syscon_regmap_lookup_by_phandle_args(dev->of_node, "qcom,phy-mux-sel", >> + ARRAY_SIZE(args), args); > No. mux data should come from match_data rather than polluting DT with it. > >> + if (IS_ERR(tcsr)) { >> + ret = PTR_ERR(tcsr); >> + if (ret == -ENOENT) >> + return 0; >> + >> + dev_err(dev, "failed to lookup syscon for phy mux %d\n", ret); >> + return ret; >> + } >> + >> + /* PHY MUX registers only have this BIT0 */ > huh? > >> + ret = regmap_write(tcsr, args[0], args[1]); >> + if (ret < 0) { >> + dev_err(dev, "PHY Mux selection failed: %d\n", ret); >> + return ret; >> + } >> + >> + return 0; >> +} >> + >> +static int uniphy_enable(struct phy *phy) >> { >> - struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy); >> + struct qcom_uniphy *uniphy = phy_get_drvdata(phy); >> + const struct uniphy_cfg *cfg = uniphy->cfg; >> + const struct uniphy_init_tbl *tbl; >> + void __iomem *base = uniphy->base; >> + int i, ret; >> >> - reset_control_assert(phy->por_rst); >> - msleep(10); >> + ret = regulator_bulk_enable(cfg->num_vregs, uniphy->vregs); >> + if (ret) { >> + dev_err(uniphy->dev, "failed to enable regulators: %d\n", ret); >> + return ret; >> + } >> + >> + /* Assert all available resets */ >> + for (i = 0; i < cfg->num_resets; i++) { >> + ret = reset_control_assert(uniphy->resets[i].rstc); >> + if (ret) { >> + dev_err(uniphy->dev, "reset assert failed: %d\n", ret); >> + goto err_assert_reset; >> + } >> + if (cfg->reset_udelay) >> + usleep_range(cfg->reset_udelay, cfg->reset_udelay + 10); >> + } > There is a whole reset_control_bulk_*() set of API. Please use it > instead of hardcoding reset cycles. > >> + >> + /* Deassert all available resets */ >> + for (i = 0; i < cfg->num_resets; i++) { >> + ret = reset_control_deassert(uniphy->resets[i].rstc); >> + if (ret) { >> + dev_err(uniphy->dev, "reset deassert failed: %d\n", ret); >> + goto err_assert_reset; >> + } >> + if (cfg->reset_udelay) >> + usleep_range(cfg->reset_udelay, cfg->reset_udelay + 10); >> + } >> + >> + ret = phy_mux_sel(phy); >> + if (ret < 0) >> + goto err_assert_reset; >> + >> + ret = clk_bulk_prepare_enable(cfg->num_clks, uniphy->clks); >> + if (ret) { >> + dev_err(uniphy->dev, "failed to enable clocks: %d\n", ret); >> + goto err_assert_reset; >> + } >> + >> + if (cfg->autoload_udelay) >> + usleep_range(cfg->autoload_udelay, cfg->autoload_udelay + 10); >> + >> + if (cfg->num_init_seq) { >> + tbl = cfg->init_seq; >> + for (i = 0; i < cfg->num_init_seq; i++, tbl++) >> + writel(tbl->val, base + tbl->offset); >> + } > unused > >> return 0; >> + >> +err_assert_reset: >> + /* Assert all available resets */ >> + for (i = 0; i < cfg->num_resets; i++) { >> + reset_control_assert(uniphy->resets[i].rstc); >> + if (cfg->reset_udelay) >> + usleep_range(cfg->reset_udelay, cfg->reset_udelay + 10); >> + } >> + >> + return ret; >> } >> >> -static int ipq4019_ss_phy_power_on(struct phy *_phy) >> +static int uniphy_disable(struct phy *phy) >> { >> - struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy); >> + struct qcom_uniphy *uniphy = phy_get_drvdata(phy); >> + const struct uniphy_cfg *cfg = uniphy->cfg; >> + int i; >> >> - ipq4019_ss_phy_power_off(_phy); >> + /* Assert all available resets */ >> + for (i = 0; i < cfg->num_resets; i++) { >> + reset_control_assert(uniphy->resets[i].rstc); >> + if (cfg->reset_udelay) >> + usleep_range(cfg->reset_udelay, cfg->reset_udelay + 10); >> + } >> >> - reset_control_deassert(phy->por_rst); >> + clk_bulk_disable_unprepare(cfg->num_clks, uniphy->clks); >> + >> + regulator_bulk_disable(cfg->num_vregs, uniphy->vregs); >> >> return 0; >> } >> >> -static const struct phy_ops ipq4019_usb_ss_phy_ops = { >> - .power_on = ipq4019_ss_phy_power_on, >> - .power_off = ipq4019_ss_phy_power_off, >> +static const struct phy_ops uniphy_phy_ops = { >> + .power_on = uniphy_enable, >> + .power_off = uniphy_disable, > Using _enable / _disable for power_on() and power_off() isn't logical. > >> + .owner = THIS_MODULE, >> }; >> >> -static int ipq4019_hs_phy_power_off(struct phy *_phy) >> +static int qcom_uniphy_vreg_init(struct qcom_uniphy *uniphy) >> +{ >> + const struct uniphy_cfg *cfg = uniphy->cfg; >> + struct device *dev = uniphy->dev; >> + int i, ret; >> + >> + uniphy->vregs = devm_kcalloc(dev, cfg->num_vregs, >> + sizeof(*uniphy->vregs), GFP_KERNEL); > You know the maximum amount of regulators. Can you use an array > instead of allocating data? > >> + if (!uniphy->vregs) >> + return -ENOMEM; >> + >> + for (i = 0; i < cfg->num_vregs; i++) >> + uniphy->vregs[i].supply = cfg->vreg_list[i]; >> + >> + ret = devm_regulator_bulk_get(dev, cfg->num_vregs, uniphy->vregs); >> + > Drop empty lines between ret assignment and check. > >> + if (ret) >> + return dev_err_probe(dev, ret, "failed to get regulators\n"); >> + >> + return 0; >> +} >> + >> +static int qcom_uniphy_reset_init(struct qcom_uniphy *uniphy) >> { >> - struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy); >> + const struct uniphy_cfg *cfg = uniphy->cfg; >> + struct device *dev = uniphy->dev; >> + int i, ret; >> + >> + uniphy->resets = devm_kcalloc(dev, cfg->num_resets, >> + sizeof(*uniphy->resets), GFP_KERNEL); > Same here, can you use an array? > >> + if (!uniphy->resets) >> + return -ENOMEM; >> >> - reset_control_assert(phy->por_rst); >> - msleep(10); >> + for (i = 0; i < cfg->num_resets; i++) >> + uniphy->resets[i].id = cfg->reset_list[i]; > Declare common resets list and use > devm_reset_control_bulk_get_optional_exclusive(). > >> - reset_control_assert(phy->srif_rst); >> - msleep(10); >> + ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, uniphy->resets); >> + if (ret) >> + return dev_err_probe(dev, ret, "failed to get resets\n"); >> >> return 0; >> } >> >> -static int ipq4019_hs_phy_power_on(struct phy *_phy) >> +static int qcom_uniphy_clk_init(struct qcom_uniphy *uniphy) > I don't see clocks actually being used. Please do not introduce unused features. > >> { >> - struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy); >> + const struct uniphy_cfg *cfg = uniphy->cfg; >> + struct device *dev = uniphy->dev; >> + int i, ret; >> >> - ipq4019_hs_phy_power_off(_phy); >> >> - reset_control_deassert(phy->srif_rst); >> - msleep(10); >> + uniphy->clks = devm_kcalloc(dev, cfg->num_clks, >> + sizeof(*uniphy->clks), GFP_KERNEL); >> + if (!uniphy->clks) >> + return -ENOMEM; >> + >> + for (i = 0; i < cfg->num_clks; i++) >> + uniphy->clks[i].id = cfg->clk_list[i]; >> >> - reset_control_deassert(phy->por_rst); >> + ret = devm_clk_bulk_get(dev, cfg->num_clks, uniphy->clks); >> + if (ret) >> + return dev_err_probe(dev, ret, "failed to get clocks\n"); >> >> return 0; >> } >> >> -static const struct phy_ops ipq4019_usb_hs_phy_ops = { >> - .power_on = ipq4019_hs_phy_power_on, >> - .power_off = ipq4019_hs_phy_power_off, >> -}; >> +static void phy_clk_release_provider(void *res) >> +{ >> + of_clk_del_provider(res); >> +} >> >> -static const struct of_device_id ipq4019_usb_phy_of_match[] = { >> - { .compatible = "qcom,usb-hs-ipq4019-phy", .data = &ipq4019_usb_hs_phy_ops}, >> - { .compatible = "qcom,usb-ss-ipq4019-phy", .data = &ipq4019_usb_ss_phy_ops}, >> - { }, >> -}; >> -MODULE_DEVICE_TABLE(of, ipq4019_usb_phy_of_match); >> +/* >> + * Register a fixed rate pipe clock. >> + * >> + * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate >> + * controls it. The <s>_pipe_clk coming out of the GCC is requested >> + * by the PHY driver for its operations. >> + * We register the <s>_pipe_clksrc here. The gcc driver takes care >> + * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. >> + * Below picture shows this relationship. >> + * >> + * +---------------+ >> + * | PHY block |<<---------------------------------------+ >> + * | | | >> + * | +-------+ | +-----+ | >> + * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ >> + * clk | +-------+ | +-----+ >> + * +---------------+ >> + */ >> +static int phy_pipe_clk_register(struct qcom_uniphy *uniphy, struct device_node *np) >> +{ >> + struct clk_fixed_rate *fixed = &uniphy->pipe_clk_fixed; >> + const struct uniphy_cfg *cfg = uniphy->cfg; >> + struct device *dev = uniphy->dev; >> + struct clk_init_data init = { }; >> + int ret; >> + >> + ret = of_property_read_string(np, "clock-output-names", &init.name); >> + if (ret) { >> + dev_err(dev, "%pOFn: No clock-output-names\n", np); >> + return ret; >> + } >> + >> + init.ops = &clk_fixed_rate_ops; >> + >> + fixed->fixed_rate = cfg->pipe_clk_rate; >> + fixed->hw.init = &init; >> >> -static int ipq4019_usb_phy_probe(struct platform_device *pdev) >> + ret = devm_clk_hw_register(dev, &fixed->hw); >> + if (ret) >> + return ret; >> + >> + ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); >> + if (ret) >> + return ret; > When you c&p something, please take care to understand the code you are copying. > Unlike QMP drivers you can (and should) use devm_of_clk_add_hw_provider() here. > > Not to mention that pipe clocks are not in this patch. > >> + >> + /* >> + * Roll a devm action because the clock provider is the child node, but >> + * the child node is not actually a device. >> + */ >> + return devm_add_action_or_reset(dev, phy_clk_release_provider, np); >> +} >> + >> +static int qcom_uniphy_probe(struct platform_device *pdev) >> { >> struct device *dev = &pdev->dev; >> struct phy_provider *phy_provider; >> - struct ipq4019_usb_phy *phy; >> + struct qcom_uniphy *uniphy; >> + struct device_node *np; >> + int ret; >> >> - phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); >> - if (!phy) >> + uniphy = devm_kzalloc(dev, sizeof(*uniphy), GFP_KERNEL); >> + if (!uniphy) >> return -ENOMEM; >> >> - phy->dev = &pdev->dev; >> - phy->base = devm_platform_ioremap_resource(pdev, 0); >> - if (IS_ERR(phy->base)) { >> - dev_err(dev, "failed to remap register memory\n"); >> - return PTR_ERR(phy->base); >> - } >> + uniphy->dev = dev; >> >> - phy->por_rst = devm_reset_control_get(phy->dev, "por_rst"); >> - if (IS_ERR(phy->por_rst)) { >> - if (PTR_ERR(phy->por_rst) != -EPROBE_DEFER) >> - dev_err(dev, "POR reset is missing\n"); >> - return PTR_ERR(phy->por_rst); >> + uniphy->cfg = of_device_get_match_data(dev); >> + if (!uniphy->cfg) >> + return -EINVAL; >> + >> + uniphy->base = devm_platform_ioremap_resource(pdev, 0); >> + if (IS_ERR(uniphy->base)) { >> + ret = PTR_ERR(uniphy->base); >> + dev_err_probe(dev, ret, "failed to remap register memory\n"); >> + return ret; >> } >> >> - phy->srif_rst = devm_reset_control_get_optional(phy->dev, "srif_rst"); >> - if (IS_ERR(phy->srif_rst)) >> - return PTR_ERR(phy->srif_rst); >> + ret = qcom_uniphy_clk_init(uniphy); >> + if (ret) >> + return ret; >> + >> + ret = qcom_uniphy_reset_init(uniphy); >> + if (ret) >> + return ret; >> + >> + ret = qcom_uniphy_vreg_init(uniphy); >> + if (ret < 0) >> + return ret; >> + >> + if (uniphy->cfg->pipe_clk_rate) { >> + np = of_node_get(dev->of_node); > What for? Do you think that the driver can outlive struct device? > >> + ret = phy_pipe_clk_register(uniphy, np); >> + if (ret) { >> + dev_err_probe(dev, ret, "failed to register pipe clk\n"); >> + goto err; >> + } >> + } >> >> - phy->phy = devm_phy_create(dev, NULL, of_device_get_match_data(dev)); >> - if (IS_ERR(phy->phy)) { >> - dev_err(dev, "failed to create PHY\n"); >> - return PTR_ERR(phy->phy); >> + uniphy->phy = devm_phy_create(dev, NULL, &uniphy_phy_ops); >> + if (IS_ERR(uniphy->phy)) { >> + ret = PTR_ERR(uniphy->phy); >> + dev_err_probe(dev, ret, "failed to create PHY\n"); >> + goto err; >> } >> - phy_set_drvdata(phy->phy, phy); >> + >> + phy_set_drvdata(uniphy->phy, uniphy); >> >> phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); >> >> - return PTR_ERR_OR_ZERO(phy_provider); >> + ret = PTR_ERR_OR_ZERO(phy_provider); >> + >> +err: >> + if (uniphy->cfg->pipe_clk_rate) >> + of_node_put(np); >> + return ret; >> } >> >> -static struct platform_driver ipq4019_usb_phy_driver = { >> - .probe = ipq4019_usb_phy_probe, >> +static const struct of_device_id qcom_uniphy_of_match[] = { >> + { .compatible = "qcom,usb-hs-ipq4019-phy", .data = &ipq4019_usb_hsphy_cfg}, >> + { .compatible = "qcom,usb-ss-ipq4019-phy", .data = &ipq4019_usb_ssphy_cfg}, >> + { }, >> +}; >> +MODULE_DEVICE_TABLE(of, qcom_uniphy_of_match); >> + >> +static struct platform_driver qcom_uniphy_driver = { >> + .probe = qcom_uniphy_probe, >> .driver = { >> - .of_match_table = ipq4019_usb_phy_of_match, >> - .name = "ipq4019-usb-phy", >> + .of_match_table = qcom_uniphy_of_match, >> + .name = "qcom-uniphy", >> } >> }; >> -module_platform_driver(ipq4019_usb_phy_driver); >> +module_platform_driver(qcom_uniphy_driver); >> >> -MODULE_DESCRIPTION("QCOM/IPQ4019 USB phy driver"); >> +MODULE_DESCRIPTION("QCOM uniphy driver"); >> MODULE_AUTHOR("John Crispin <john@phrozen.org>"); >> MODULE_LICENSE("GPL v2"); > General comment: please consider dropping this beast and starting from > scratch, adding only really necessary bits to the existing ipq4019 USB > PHY driver. Rewritten the entire driver considering the IPQ5332 as well and because of it there are unused code which are utilized in patch [8/9]. I should have added only the IPQ4019 support alone in this patch and then incrementally update it for IPQ5332. Will follow that here onwards. Will address all the review comments. - Praveenkumar
On 8/29/2023 10:37 PM, Krzysztof Kozlowski wrote: > On 29/08/2023 15:58, Praveenkumar I wrote: >> IPQ5332 has UNIPHY for USB and PCIe which is similar to the UNIPHY >> present in IPQ4019. Few extra settings like clock, reset delay, mux >> selection and voltage regulator are required for IPQ5332. Hence >> repurposed the IPQ4019 PHY driver for IPQ5332 UNIPHY. Few more Qualcomm >> SoCs are also having the UNIPHY which can use the same driver for both >> USB and PCIe PHY. >> >> Praveenkumar I (9): >> dt-bindings: phy: qcom,uniphy: Rename ipq4019 usb PHY to UNIPHY >> phy: qcom: uniphy: Rename ipq4019 USB phy driver to UNIPHY driver >> phy: qcom: uniphy: Update UNIPHY driver to be a common driver >> dt-bindings: phy: qcom,uniphy: Add ipq5332 USB3 SS UNIPHY >> dt-bindings: usb: dwc3: Update IPQ5332 compatible >> arm64: dts: qcom: ipq5332: Add USB3 related nodes >> arm64: dts: qcom: ipq5332: Enable USB SS UNIPHY > DTS does not go before drivers. DTS should be sent separately or as the > last patches. If you stuff it in the middle, means your patchset has > dependencies which it cannot have. Thus it is broken. Sorry, I ordered it wrongly. Will correct in the next patches. - Praveenkumar > > Best regards, > Krzysztof >
On 8/29/2023 10:37 PM, Krzysztof Kozlowski wrote: > On 29/08/2023 15:58, Praveenkumar I wrote: >> IPQ5332 has UNIPHY for USB and PCIe which is similar to the UNIPHY >> present in IPQ4019. Few extra settings like clock, reset delay, mux >> selection and voltage regulator are required for IPQ5332. Hence >> repurposed the IPQ4019 PHY driver for IPQ5332 UNIPHY. Few more Qualcomm >> SoCs are also having the UNIPHY which can use the same driver for both >> USB and PCIe PHY. >> >> Praveenkumar I (9): >> dt-bindings: phy: qcom,uniphy: Rename ipq4019 usb PHY to UNIPHY >> phy: qcom: uniphy: Rename ipq4019 USB phy driver to UNIPHY driver >> phy: qcom: uniphy: Update UNIPHY driver to be a common driver >> dt-bindings: phy: qcom,uniphy: Add ipq5332 USB3 SS UNIPHY >> dt-bindings: usb: dwc3: Update IPQ5332 compatible >> arm64: dts: qcom: ipq5332: Add USB3 related nodes >> arm64: dts: qcom: ipq5332: Enable USB SS UNIPHY > DTS does not go before drivers. DTS should be sent separately or as the > last patches. If you stuff it in the middle, means your patchset has > dependencies which it cannot have. Thus it is broken. Sorry, I ordered it wrongly. Will correct in the next patches. - Praveenkumar > > Best regards, > Krzysztof >
On Thu, 31 Aug 2023 at 15:13, Praveenkumar I <quic_ipkumar@quicinc.com> wrote: > > > On 8/29/2023 8:15 PM, Dmitry Baryshkov wrote: > > On Tue, 29 Aug 2023 at 17:00, Praveenkumar I <quic_ipkumar@quicinc.com> wrote: > > This patch adds ipq5332 USB SS UNIPHY support. > > First, please read to Documentation/process/submitting-patches.rst, > then rewrite the commit message. > > Next, I tend to say that this driver doesn't have a lot in common with > the ipq4019 driver you have modified. Please consider adding new > driver for ipq5332, then we can see whether it makes sense to fold > ipq4019 to use new infrastructure. > > Sure, will add new driver for IPQ5332 USB3 PHY. Thanks a lot for the review. No HTML mail please. Ever. And use proper quotation. Thank you. > > -- > Thanks, > Praveenkumar > > Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> > --- > This patch depends on the below series which adds support for USB2 in > IPQ5332 > https://lore.kernel.org/all/cover.1692699472.git.quic_varada@quicinc.com/ > > drivers/phy/qualcomm/phy-qcom-uniphy.c | 37 ++++++++++++++++++++++++++ > 1 file changed, 37 insertions(+) > > diff --git a/drivers/phy/qualcomm/phy-qcom-uniphy.c b/drivers/phy/qualcomm/phy-qcom-uniphy.c > index eb71588f5417..91487e68bb6e 100644 > --- a/drivers/phy/qualcomm/phy-qcom-uniphy.c > +++ b/drivers/phy/qualcomm/phy-qcom-uniphy.c > @@ -26,6 +26,10 @@ > #include <linux/regulator/consumer.h> > #include <linux/reset.h> > > +#define PCIE_USB_COMBO_PHY_CFG_MISC1 0x214 > +#define PCIE_USB_COMBO_PHY_CFG_RX_AFE_2 0x7C4 > +#define PCIE_USB_COMBO_PHY_CFG_RX_DLF_DEMUX_2 0x7E8 > + > struct uniphy_init_tbl { > unsigned int offset; > unsigned int val; > @@ -37,6 +41,12 @@ struct uniphy_init_tbl { > .val = v, \ > } > > +static const struct uniphy_init_tbl ipq5332_usb_ssphy_init_tbl[] = { > + UNIPHY_INIT_CFG(PCIE_USB_COMBO_PHY_CFG_RX_AFE_2, 0x1076), > + UNIPHY_INIT_CFG(PCIE_USB_COMBO_PHY_CFG_RX_DLF_DEMUX_2, 0x3142), > + UNIPHY_INIT_CFG(PCIE_USB_COMBO_PHY_CFG_MISC1, 0x3), > +}; > + > struct uniphy_cfg { > const struct uniphy_init_tbl *init_seq; > int num_init_seq; > @@ -83,6 +93,32 @@ static const struct uniphy_cfg ipq4019_usb_hsphy_cfg = { > .reset_udelay = 10000, > }; > > +static const char * const ipq5332_usb_ssphy_clk_l[] = { > + "phy_ahb", "phy_cfg_ahb", "pipe", > +}; > + > +static const char * const ipq5332_usb_ssphy_reset_l[] = { > + "por_rst", > +}; > + > +static const char * const ipq5332_usb_ssphy_vreg_l[] = { > + "vdda-phy", > +}; > + > +static const struct uniphy_cfg ipq5332_usb_ssphy_cfg = { > + .init_seq = ipq5332_usb_ssphy_init_tbl, > + .num_init_seq = ARRAY_SIZE(ipq5332_usb_ssphy_init_tbl), > + .clk_list = ipq5332_usb_ssphy_clk_l, > + .num_clks = ARRAY_SIZE(ipq5332_usb_ssphy_clk_l), > + .reset_list = ipq5332_usb_ssphy_reset_l, > + .num_resets = ARRAY_SIZE(ipq5332_usb_ssphy_reset_l), > + .vreg_list = ipq5332_usb_ssphy_vreg_l, > + .num_vregs = ARRAY_SIZE(ipq5332_usb_ssphy_vreg_l), > + .pipe_clk_rate = 250000000, > + .reset_udelay = 1, > + .autoload_udelay = 35, > +}; > + > static int phy_mux_sel(struct phy *phy) > { > struct qcom_uniphy *uniphy = phy_get_drvdata(phy); > @@ -396,6 +432,7 @@ static int qcom_uniphy_probe(struct platform_device *pdev) > static const struct of_device_id qcom_uniphy_of_match[] = { > { .compatible = "qcom,usb-hs-ipq4019-phy", .data = &ipq4019_usb_hsphy_cfg}, > { .compatible = "qcom,usb-ss-ipq4019-phy", .data = &ipq4019_usb_ssphy_cfg}, > + { .compatible = "qcom,ipq5332-usb-ssphy", .data = &ipq5332_usb_ssphy_cfg}, > { }, > }; > MODULE_DEVICE_TABLE(of, qcom_uniphy_of_match); > -- > 2.34.1 >
On 8/29/2023 10:25 PM, Krzysztof Kozlowski wrote: > On 29/08/2023 15:58, Praveenkumar I wrote: >> UNIPHY / Combo PHY used on various qualcomm SoC's are very similar to >> ipq4019 PHY. Hence renaming this driver to uniphy driver and can be >> used for other SoC's which are having the similar UNIPHY. >> >> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> >> --- >> MAINTAINERS | 7 ++++--- >> drivers/phy/qualcomm/Kconfig | 7 ++++--- >> drivers/phy/qualcomm/Makefile | 2 +- >> .../qualcomm/{phy-qcom-ipq4019-usb.c => phy-qcom-uniphy.c} | 0 >> 4 files changed, 9 insertions(+), 7 deletions(-) >> rename drivers/phy/qualcomm/{phy-qcom-ipq4019-usb.c => phy-qcom-uniphy.c} (100%) >> >> diff --git a/MAINTAINERS b/MAINTAINERS >> index ff1f273b4f36..7f4553c1a69a 100644 >> --- a/MAINTAINERS >> +++ b/MAINTAINERS >> @@ -17774,13 +17774,14 @@ F: Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml >> F: drivers/mailbox/qcom-ipcc.c >> F: include/dt-bindings/mailbox/qcom-ipcc.h >> >> -QUALCOMM IPQ4019 USB PHY DRIVER >> +QUALCOMM UNIPHY DRIVER >> M: Robert Marko <robert.marko@sartura.hr> >> M: Luka Perkov <luka.perkov@sartura.hr> >> +M: Praveenkumar I <quic_ipkumar@quicinc.com> >> L: linux-arm-msm@vger.kernel.org >> S: Maintained >> -F: Documentation/devicetree/bindings/phy/qcom-usb-ipq4019-phy.yaml >> -F: drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c >> +F: Documentation/devicetree/bindings/phy/qcom,uniphy.yaml > You broke the path in your previous commit, but anyway this will go away. > >> +F: drivers/phy/qualcomm/phy-qcom-uniphy.c >> >> QUALCOMM IPQ4019 VQMMC REGULATOR DRIVER >> M: Robert Marko <robert.marko@sartura.hr> >> diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig >> index d891058b7c39..e6981bc212b3 100644 >> --- a/drivers/phy/qualcomm/Kconfig >> +++ b/drivers/phy/qualcomm/Kconfig >> @@ -28,12 +28,13 @@ config PHY_QCOM_EDP >> Enable this driver to support the Qualcomm eDP PHY found in various >> Qualcomm chipsets. >> >> -config PHY_QCOM_IPQ4019_USB >> - tristate "Qualcomm IPQ4019 USB PHY driver" >> +config PHY_QCOM_UNIPHY >> + tristate "Qualcomm UNIPHY driver" >> depends on OF && (ARCH_QCOM || COMPILE_TEST) >> select GENERIC_PHY >> help >> - Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s. >> + Enable this driver to support the Qualcomm UNIPHY found in various >> + Qualcomm chipsets. > I don't quite get why this is renamed, either. Just because you re-use > it? Re-usage is not affected with old name... Understood. As suggested by Dmitry Baryshkov, will add new driver for Qualcomm IPQ5332 USB Gen3 PHY driver. - Praveenkumar > > Best regards, > Krzysztof >