Message ID | 20230827032803.934819-1-dmitry.baryshkov@linaro.org |
---|---|
Headers | show |
Series | cpufreq: qcom-nvmem: support apq8064 cpufreq scaling | expand |
On 27.08.2023 05:27, Dmitry Baryshkov wrote: > This is a split of APQ8064 cpufreq series, as requested by Viresh. This > series includes only opp and cpufreq parts, with the DT and soc parts > being split to a separate patchset. > > Each core has independent power and frequency control. Additionally the > L2 cache is scaled to follow the CPU frequencies (failure to do so > results in strange semi-random crashes). > > Core voltage is controlled through the SAW2 devices, one for each core. > The L2 has two regulators, vdd-mem and vdd-dig. > No changelog? Konrad
On Mon, 28 Aug 2023 at 12:43, Konrad Dybcio <konrad.dybcio@linaro.org> wrote: > > On 27.08.2023 05:27, Dmitry Baryshkov wrote: > > This is a split of APQ8064 cpufreq series, as requested by Viresh. This > > series includes only opp and cpufreq parts, with the DT and soc parts > > being split to a separate patchset. > > > > Each core has independent power and frequency control. Additionally the > > L2 cache is scaled to follow the CPU frequencies (failure to do so > > results in strange semi-random crashes). > > > > Core voltage is controlled through the SAW2 devices, one for each core. > > The L2 has two regulators, vdd-mem and vdd-dig. > > > No changelog? Missed it while performing the split. Changes since v3: - Unrolled loops in krait_l2_config_regulators() (Konrad)
On 27.08.2023 05:28, Dmitry Baryshkov wrote: > APQ8064 can scale core voltage according to the frequency needs. Rather > than reusing the A/B format multiplexer, use a simple fuse parsing > function and configure required regulator. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > drivers/cpufreq/qcom-cpufreq-nvmem.c | 49 ++++++++++++++++++++++++++-- > 1 file changed, 47 insertions(+), 2 deletions(-) > > diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c > index 81c080b854fe..35e2610c9526 100644 > --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c > +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c > @@ -26,6 +26,7 @@ > #include <linux/platform_device.h> > #include <linux/pm_domain.h> > #include <linux/pm_opp.h> > +#include <linux/regulator/consumer.h> > #include <linux/slab.h> > #include <linux/soc/qcom/smem.h> > > @@ -39,6 +40,7 @@ struct qcom_cpufreq_match_data { > char **pvs_name, > struct qcom_cpufreq_drv *drv); > const char **genpd_names; > + const char * const *regulator_names; > }; > > struct qcom_cpufreq_drv { > @@ -203,6 +205,34 @@ static int qcom_cpufreq_krait_name_version(struct device *cpu_dev, > return ret; > } > > +static int qcom_cpufreq_apq8064_name_version(struct device *cpu_dev, > + struct nvmem_cell *speedbin_nvmem, > + char **pvs_name, > + struct qcom_cpufreq_drv *drv) > +{ > + int speed = 0, pvs = 0; > + u8 *speedbin; > + size_t len; > + int ret = 0; Unused, just return 0 > + > + speedbin = nvmem_cell_read(speedbin_nvmem, &len); > + if (IS_ERR(speedbin)) > + return PTR_ERR(speedbin); > + > + if (len != 4) > + return -EINVAL; > + > + get_krait_bin_format_a(cpu_dev, &speed, &pvs, speedbin); > + > + snprintf(*pvs_name, sizeof("speedXX-pvsXX"), "speed%d-pvs%d", > + speed, pvs); speed and pvs are both one hex digit long at best (see masking in get_krait_bin_format_a) Konrad
On 27.08.2023 05:27, Dmitry Baryshkov wrote: > Scaling the frequencies on some of Qualcomm Krait platforms (e.g. > APQ8064) also requires scaling of the L2 cache frequency. As the > l2-cache device node is places under /cpus/ path, it is not created by > default by the OF code. Create corresponding device here. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > drivers/cpufreq/qcom-cpufreq-nvmem.c | 21 +++++++++++++++++++++ > 1 file changed, 21 insertions(+) > > diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c > index 84d7033e5efe..f4c196ba4432 100644 > --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c > +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c > @@ -22,6 +22,7 @@ > #include <linux/module.h> > #include <linux/nvmem-consumer.h> > #include <linux/of.h> > +#include <linux/of_platform.h> > #include <linux/platform_device.h> > #include <linux/pm_domain.h> > #include <linux/pm_opp.h> > @@ -377,6 +378,7 @@ static int __init qcom_cpufreq_init(void) > { > struct device_node *np = of_find_node_by_path("/"); > const struct of_device_id *match; > + unsigned int cpu; > int ret; > > if (!np) > @@ -387,6 +389,25 @@ static int __init qcom_cpufreq_init(void) > if (!match) > return -ENODEV; > > + for_each_possible_cpu(cpu) { > + struct device *dev = get_cpu_device(cpu); > + struct device_node *cache; > + struct platform_device *pdev; Aaaalmost reverse-Christmas-tree :D > + > + cache = of_find_next_cache_node(dev->of_node); > + if (!cache) > + continue; > + > + if (of_device_is_compatible(cache, "qcom,krait-l2-cache")) { > + pdev = of_platform_device_create(cache, NULL, NULL); > + if (IS_ERR(pdev)) > + pr_err("%s: %pe, failed to create L2 cache node\n", __func__, pdev); The return value should be null-checked instead > + /* the error is not fatal */ "This error"? Konrad
On 28/08/2023 14:04, Konrad Dybcio wrote: > On 27.08.2023 05:28, Dmitry Baryshkov wrote: >> APQ8064 can scale core voltage according to the frequency needs. Rather >> than reusing the A/B format multiplexer, use a simple fuse parsing >> function and configure required regulator. >> >> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >> --- >> drivers/cpufreq/qcom-cpufreq-nvmem.c | 49 ++++++++++++++++++++++++++-- >> 1 file changed, 47 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c >> index 81c080b854fe..35e2610c9526 100644 >> --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c >> +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c >> @@ -26,6 +26,7 @@ >> #include <linux/platform_device.h> >> #include <linux/pm_domain.h> >> #include <linux/pm_opp.h> >> +#include <linux/regulator/consumer.h> >> #include <linux/slab.h> >> #include <linux/soc/qcom/smem.h> >> >> @@ -39,6 +40,7 @@ struct qcom_cpufreq_match_data { >> char **pvs_name, >> struct qcom_cpufreq_drv *drv); >> const char **genpd_names; >> + const char * const *regulator_names; >> }; >> >> struct qcom_cpufreq_drv { >> @@ -203,6 +205,34 @@ static int qcom_cpufreq_krait_name_version(struct device *cpu_dev, >> return ret; >> } >> >> +static int qcom_cpufreq_apq8064_name_version(struct device *cpu_dev, >> + struct nvmem_cell *speedbin_nvmem, >> + char **pvs_name, >> + struct qcom_cpufreq_drv *drv) >> +{ >> + int speed = 0, pvs = 0; >> + u8 *speedbin; >> + size_t len; >> + int ret = 0; > Unused, just return 0 > >> + >> + speedbin = nvmem_cell_read(speedbin_nvmem, &len); >> + if (IS_ERR(speedbin)) >> + return PTR_ERR(speedbin); >> + >> + if (len != 4) >> + return -EINVAL; >> + >> + get_krait_bin_format_a(cpu_dev, &speed, &pvs, speedbin); >> + >> + snprintf(*pvs_name, sizeof("speedXX-pvsXX"), "speed%d-pvs%d", >> + speed, pvs); > speed and pvs are both one hex digit long at best (see masking in > get_krait_bin_format_a) One hex translates to two decimal digits (0xf = 15). > > Konrad