| Message ID | 20230618132235.728641-1-niravkumar.l.rabara@intel.com |
|---|---|
| Headers | show |
| Series | Add support for Agilex5 SoCFPGA platform | expand |
On 18/06/2023 15:22, niravkumar.l.rabara@intel.com wrote: > From: Niravkumar L Rabara <niravkumar.l.rabara@intel.com> > > Add the initial device tree files for Intel's Agilex5 SoCFPGA platform. > > Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@intel.com> > Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com> > --- > arch/arm64/boot/dts/intel/Makefile | 3 + > .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 641 ++++++++++++++++++ > .../boot/dts/intel/socfpga_agilex5_socdk.dts | 184 +++++ > .../dts/intel/socfpga_agilex5_socdk_nand.dts | 131 ++++ > .../dts/intel/socfpga_agilex5_socdk_swvp.dts | 248 +++++++ > 5 files changed, 1207 insertions(+) > create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi > create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts > create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts > create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_swvp.dts > > diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile > index c2a723838344..bb74a7e30e58 100644 > --- a/arch/arm64/boot/dts/intel/Makefile > +++ b/arch/arm64/boot/dts/intel/Makefile > @@ -2,5 +2,8 @@ > dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \ > socfpga_agilex_socdk.dtb \ > socfpga_agilex_socdk_nand.dtb \ > + socfpga_agilex5_socdk.dtb \ > + socfpga_agilex5_socdk_nand.dtb \ > + socfpga_agilex5_socdk_swvp.dtb \ > socfpga_n5x_socdk.dtb > dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb > diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi > new file mode 100644 > index 000000000000..9454d88d6457 > --- /dev/null > +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi > @@ -0,0 +1,641 @@ > +// SPDX-License-Identifier: GPL-2.0 Drop indent before license. > +/* > + * Copyright (C) 2023, Intel Corporation > + */ > + > +/dts-v1/; > +#include <dt-bindings/reset/altr,rst-mgr-agilex5.h> > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/interrupt-controller/irq.h> > +#include <dt-bindings/clock/agilex5-clock.h> > + > +/ { > + compatible = "intel,socfpga-agilex"; > + #address-cells = <2>; > + #size-cells = <2>; > + > + reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + service_reserved: svcbuffer@0 { > + compatible = "shared-dma-pool"; > + reg = <0x0 0x80000000 0x0 0x2000000>; > + alignment = <0x1000>; > + no-map; > + }; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu0: cpu@0 { > + compatible = "arm,cortex-a55"; > + device_type = "cpu"; > + enable-method = "psci"; > + reg = <0x0>; > + }; > + > + cpu1: cpu@1 { > + compatible = "arm,cortex-a55"; > + device_type = "cpu"; > + enable-method = "psci"; > + reg = <0x100>; > + }; > + > + cpu2: cpu@2 { > + compatible = "arm,cortex-a76"; > + device_type = "cpu"; > + enable-method = "psci"; > + reg = <0x200>; > + }; > + > + cpu3: cpu@3 { > + compatible = "arm,cortex-a76"; > + device_type = "cpu"; > + enable-method = "psci"; > + reg = <0x300>; > + }; > + }; > + > + psci { > + compatible = "arm,psci-0.2"; > + method = "smc"; > + }; > + > + intc: interrupt-controller@1d000000 { > + compatible = "arm,gic-v3", "arm,cortex-a15-gic"; reg is always after compatible. Then ranges, if applicable. > + #interrupt-cells = <3>; > + #address-cells = <2>; > + #size-cells =<2>; > + interrupt-controller; > + #redistributor-regions = <1>; > + label = "GIC"; It does not look like you tested the DTS against bindings. Please run `make dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst or https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/ for instructions). > + status = "okay"; Drop, you don't need status. > + ranges; > + redistributor-stride = <0x0 0x20000>; > + reg = <0x0 0x1d000000 0 0x10000>, > + <0x0 0x1d060000 0 0x100000>; > + > + its: msi-controller@1d040000 { > + compatible = "arm,gic-v3-its"; > + reg = <0x0 0x1d040000 0x0 0x20000>; > + label = "ITS"; > + msi-controller; > + status = "okay"; Drop Anyway, entire node should be in soc. You clearly did not test it with dtbs W=1. Neither with dtbs_check. > + }; > + }; > + > + /* Clock tree 5 main sources*/ > + clocks { > + cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + }; > + > + cb_intosc_ls_clk: cb-intosc-ls-clk { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + }; > + > + f2s_free_clk: f2s-free-clk { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + }; > + > + osc1: osc1 { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + }; > + > + qspi_clk: qspi-clk { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <200000000>; > + }; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupt-parent = <&intc>; > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; > + }; > + > + usbphy0: usbphy { > + #phy-cells = <0>; > + compatible = "usb-nop-xceiv"; > + }; > + > + soc { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "simple-bus"; > + device_type = "soc"; > + interrupt-parent = <&intc>; > + ranges = <0 0 0 0xffffffff>; > + > + clkmgr: clock-controller@10d10000 { > + compatible = "intel,agilex5-clkmgr"; > + reg = <0x10d10000 0x1000>; > + #clock-cells = <1>; > + }; > + > + stmmac_axi_setup: stmmac-axi-config { > + snps,wr_osr_lmt = <31>; > + snps,rd_osr_lmt = <31>; > + snps,blen = <0 0 0 32 16 8 4>; > + }; > + > + mtl_rx_setup: rx-queues-config { These two nodes do not belong to SoC. Soc is for MMIO-based nodes. > + snps,rx-queues-to-use = <8>; > + snps,rx-sched-sp; > + queue0 { > + snps,dcb-algorithm; > + snps,map-to-dma-channel = <0x0>; > + }; > + queue1 { > + snps,dcb-algorithm; > + snps,map-to-dma-channel = <0x1>; > + }; > + queue2 { > + snps,dcb-algorithm; > + snps,map-to-dma-channel = <0x2>; > + }; > + queue3 { > + snps,dcb-algorithm; > + snps,map-to-dma-channel = <0x3>; > + }; > + queue4 { > + snps,dcb-algorithm; > + snps,map-to-dma-channel = <0x4>; > + }; > + queue5 { > + snps,dcb-algorithm; > + snps,map-to-dma-channel = <0x5>; > + }; > + queue6 { > + snps,dcb-algorithm; > + snps,map-to-dma-channel = <0x6>; > + }; > + queue7 { > + snps,dcb-algorithm; > + snps,map-to-dma-channel = <0x7>; > + }; > + }; > + > + mtl_tx_setup: tx-queues-config { This as well > + snps,tx-queues-to-use = <8>; > + snps,tx-sched-wrr; > + queue0 { > + snps,weight = <0x09>; > + snps,dcb-algorithm; > + }; > + queue1 { > + snps,weight = <0x0A>; > + snps,dcb-algorithm; > + }; > + queue2 { > + snps,weight = <0x0B>; > + snps,dcb-algorithm; > + }; > + queue3 { > + snps,weight = <0x0C>; > + snps,dcb-algorithm; > + }; > + queue4 { > + snps,weight = <0x0D>; > + snps,dcb-algorithm; > + }; > + queue5 { > + snps,weight = <0x0E>; > + snps,dcb-algorithm; > + }; > + queue6 { > + snps,weight = <0x0F>; > + snps,dcb-algorithm; > + }; > + queue7 { > + snps,weight = <0x10>; > + snps,dcb-algorithm; > + }; > + }; > + > + gmac0: ethernet@10810000 { > + compatible = "altr,socfpga-stmmac-a10-s10", > + "snps,dwxgmac-2.10", > + "snps,dwxgmac"; You have broken alignment. > + reg = <0x10810000 0x3500>; > + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, In multiple places. Really. > + <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "macirq", > + "macirq_tx0", This is ugly. > + "macirq_tx1", > + "macirq_tx2", > + "macirq_tx3", > + "macirq_tx4", > + "macirq_tx5", > + "macirq_tx6", > + "macirq_tx7", > + "macirq_rx0", > + "macirq_rx1", > + "macirq_rx2", > + "macirq_rx3", > + "macirq_rx4", > + "macirq_rx5", > + "macirq_rx6", > + "macirq_rx7"; > + mac-address = [00 00 00 00 00 00]; Drop, it's SoC file. > + resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; > + reset-names = "stmmaceth", "stmmaceth-ocp"; > + tx-fifo-depth = <32768>; > + rx-fifo-depth = <16384>; > + snps,multicast-filter-bins = <64>; > + snps,perfect-filter-entries = <64>; > + snps,axi-config = <&stmmac_axi_setup>; > + snps,mtl-rx-config = <&mtl_rx_setup>; > + snps,mtl-tx-config = <&mtl_tx_setup>; > + snps,pbl = <32>; > + snps,pblx8; > + snps,multi-irq-en; > + snps,tso; > + altr,sysmgr-syscon = <&sysmgr 0x44 0>; > + altr,smtg-hub; > + snps,rx-vlan-offload; > + clocks = <&clkmgr AGILEX5_EMAC0_CLK>, <&clkmgr AGILEX5_EMAC_PTP_CLK>; > + clock-names = "stmmaceth", "ptp_ref"; > + status = "disabled"; > + }; > + > + i2c0: i2c@10c02800 { > + #address-cells = <1>; > + #size-cells = <0>; compatible first, reg second. > + compatible = "snps,designware-i2c"; > + reg = <0x10c02800 0x100>; > + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; > + resets = <&rst I2C0_RESET>; > + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; > + status = "disabled"; > + }; > + > + i2c1: i2c@10c02900 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "snps,designware-i2c"; > + reg = <0x10c02900 0x100>; > + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; > + resets = <&rst I2C1_RESET>; > + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; > + status = "disabled"; > + }; > + > + i2c2: i2c@10c02a00 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "snps,designware-i2c"; > + reg = <0x10c02a00 0x100>; > + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; > + resets = <&rst I2C2_RESET>; > + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; > + status = "disabled"; > + }; > + > + i2c3: i2c@10c02b00 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "snps,designware-i2c"; > + reg = <0x10c02b00 0x100>; > + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; > + resets = <&rst I2C3_RESET>; > + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; > + status = "disabled"; > + }; > + > + i2c4: i2c@10c02c00 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "snps,designware-i2c"; > + reg = <0x10c02c00 0x100>; > + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; > + resets = <&rst I2C4_RESET>; > + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; > + status = "disabled"; > + }; > + > + i3c0: i3c@10da0000 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "snps,dw-i3c-master-1.00a"; > + reg = <0x10da0000 0x1000>; > + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; > + resets = <&rst I3C0_RESET>; > + clocks = <&clkmgr AGILEX5_L4_MP_CLK>; > + status = "disabled"; > + }; > + > + i3c1: i3c@10da1000 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "snps,dw-i3c-master-1.00a"; > + reg = <0x10da1000 0x1000>; > + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; > + resets = <&rst I3C1_RESET>; > + clocks = <&clkmgr AGILEX5_L4_MP_CLK>; > + status = "disabled"; > + }; > + > + gpio1: gpio@10C03300 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "snps,dw-apb-gpio"; > + reg = <0x10C03300 0x100>; > + resets = <&rst GPIO1_RESET>; > + status = "disabled"; > + > + portb: gpio-controller@0 { > + compatible = "snps,dw-apb-gpio-port"; > + gpio-controller; > + #gpio-cells = <2>; > + snps,nr-gpios = <24>; > + reg = <0>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; > + > + mmc: mmc0@10808000 { It does not look like you tested the DTS against bindings. Please run `make dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst or https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/ for instructions). Sorry, but your DTS lacks any basic (internal!) review and basic tests with automated tools. .. > + spi0: spi@10da4000 { > + compatible = "snps,dw-apb-ssi"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x10da4000 0x1000>; > + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; > + resets = <&rst SPIM0_RESET>; > + reset-names = "spi"; > + reg-io-width = <4>; > + num-cs = <4>; > + clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>; > + dmas = <&dmac0 2>, <&dmac0 3>; > + dma-names ="tx", "rx"; > + > + status = "disabled"; > + > + flash: m25p128@0 { It's getting worse... > + status = "okay"; and worse > + compatible = "st,m25p80"; > + spi-max-frequency = <25000000>; > + m25p,fast-read; > + reg = <0>; > + > + #address-cells = <1>; > + #size-cells = <1>; > + > + partition@0 { > + label = "spi_flash_part0"; > + reg = <0x0 0x100000>; and less conforming to style > + }; > + }; > + ... and less. ... > + > + chosen { > + stdout-path = "serial0:115200n8"; > + bootargs = "console=uart8250,mmio32,0x10c02000,115200n8 \ > + root=/dev/ram0 rw initrd=0x10000000 init=/sbin/init \ > + ramdisk_size=10000000 earlycon=uart8250,mmio32,0x10c02000,115200n8 \ > + panic=-1 nosmp rootfstype=ext3"; NAK. Drop entire bootags. > + }; > + > + leds { > + compatible = "gpio-leds"; > + hps0 { No, srsly? So all our cleanups for few years mean nothing? Best regards, Krzysztof
>On 18/06/2023 15:22, niravkumar.l.rabara@intel.com wrote: >> From: Niravkumar L Rabara <niravkumar.l.rabara@intel.com> >> >> Add the initial device tree files for Intel's Agilex5 SoCFPGA platform. >> >> Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@intel.com> >> Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com> >> --- >> arch/arm64/boot/dts/intel/Makefile | 3 + >> .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 641 >> ++++++++++++++++++ .../boot/dts/intel/socfpga_agilex5_socdk.dts | >> 184 +++++ .../dts/intel/socfpga_agilex5_socdk_nand.dts | 131 ++++ >> .../dts/intel/socfpga_agilex5_socdk_swvp.dts | 248 +++++++ >> 5 files changed, 1207 insertions(+) >> create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi >> create mode 100644 >> arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts >> create mode 100644 >> arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts >> create mode 100644 >> arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_swvp.dts >> >> diff --git a/arch/arm64/boot/dts/intel/Makefile >> b/arch/arm64/boot/dts/intel/Makefile >> index c2a723838344..bb74a7e30e58 100644 >> --- a/arch/arm64/boot/dts/intel/Makefile >> +++ b/arch/arm64/boot/dts/intel/Makefile >> @@ -2,5 +2,8 @@ >> dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \ >> socfpga_agilex_socdk.dtb \ >> socfpga_agilex_socdk_nand.dtb \ >> + socfpga_agilex5_socdk.dtb \ >> + socfpga_agilex5_socdk_nand.dtb \ >> + socfpga_agilex5_socdk_swvp.dtb \ >> socfpga_n5x_socdk.dtb >> dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb diff --git >> a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi >> b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi >> new file mode 100644 >> index 000000000000..9454d88d6457 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi >> @@ -0,0 +1,641 @@ >> +// SPDX-License-Identifier: GPL-2.0 > >Drop indent before license. > >> +/* >> + * Copyright (C) 2023, Intel Corporation */ >> + >> +/dts-v1/; >> +#include <dt-bindings/reset/altr,rst-mgr-agilex5.h> >> +#include <dt-bindings/gpio/gpio.h> >> +#include <dt-bindings/interrupt-controller/arm-gic.h> >> +#include <dt-bindings/interrupt-controller/irq.h> >> +#include <dt-bindings/clock/agilex5-clock.h> >> + >> +/ { >> + compatible = "intel,socfpga-agilex"; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + >> + reserved-memory { >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + >> + service_reserved: svcbuffer@0 { >> + compatible = "shared-dma-pool"; >> + reg = <0x0 0x80000000 0x0 0x2000000>; >> + alignment = <0x1000>; >> + no-map; >> + }; >> + }; >> + >> + cpus { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + cpu0: cpu@0 { >> + compatible = "arm,cortex-a55"; >> + device_type = "cpu"; >> + enable-method = "psci"; >> + reg = <0x0>; >> + }; >> + >> + cpu1: cpu@1 { >> + compatible = "arm,cortex-a55"; >> + device_type = "cpu"; >> + enable-method = "psci"; >> + reg = <0x100>; >> + }; >> + >> + cpu2: cpu@2 { >> + compatible = "arm,cortex-a76"; >> + device_type = "cpu"; >> + enable-method = "psci"; >> + reg = <0x200>; >> + }; >> + >> + cpu3: cpu@3 { >> + compatible = "arm,cortex-a76"; >> + device_type = "cpu"; >> + enable-method = "psci"; >> + reg = <0x300>; >> + }; >> + }; >> + >> + psci { >> + compatible = "arm,psci-0.2"; >> + method = "smc"; >> + }; >> + >> + intc: interrupt-controller@1d000000 { >> + compatible = "arm,gic-v3", "arm,cortex-a15-gic"; > >reg is always after compatible. Then ranges, if applicable. > >> + #interrupt-cells = <3>; >> + #address-cells = <2>; >> + #size-cells =<2>; >> + interrupt-controller; >> + #redistributor-regions = <1>; >> + label = "GIC"; > >It does not look like you tested the DTS against bindings. Please run `make dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst or https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/ >for instructions). > >> + status = "okay"; > >Drop, you don't need status. > >> + ranges; >> + redistributor-stride = <0x0 0x20000>; >> + reg = <0x0 0x1d000000 0 0x10000>, >> + <0x0 0x1d060000 0 0x100000>; >> + >> + its: msi-controller@1d040000 { >> + compatible = "arm,gic-v3-its"; >> + reg = <0x0 0x1d040000 0x0 0x20000>; >> + label = "ITS"; >> + msi-controller; >> + status = "okay"; > >Drop > >Anyway, entire node should be in soc. You clearly did not test it with dtbs W=1. Neither with dtbs_check. > > >> + }; >> + }; >> + >> + /* Clock tree 5 main sources*/ >> + clocks { >> + cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { >> + #clock-cells = <0>; >> + compatible = "fixed-clock"; >> + }; >> + >> + cb_intosc_ls_clk: cb-intosc-ls-clk { >> + #clock-cells = <0>; >> + compatible = "fixed-clock"; >> + }; >> + >> + f2s_free_clk: f2s-free-clk { >> + #clock-cells = <0>; >> + compatible = "fixed-clock"; >> + }; >> + >> + osc1: osc1 { >> + #clock-cells = <0>; >> + compatible = "fixed-clock"; >> + }; >> + >> + qspi_clk: qspi-clk { >> + #clock-cells = <0>; >> + compatible = "fixed-clock"; >> + clock-frequency = <200000000>; >> + }; >> + }; >> + >> + timer { >> + compatible = "arm,armv8-timer"; >> + interrupt-parent = <&intc>; >> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, >> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, >> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, >> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; >> + }; >> + >> + usbphy0: usbphy { >> + #phy-cells = <0>; >> + compatible = "usb-nop-xceiv"; >> + }; >> + >> + soc { >> + #address-cells = <1>; >> + #size-cells = <1>; >> + compatible = "simple-bus"; >> + device_type = "soc"; >> + interrupt-parent = <&intc>; >> + ranges = <0 0 0 0xffffffff>; >> + >> + clkmgr: clock-controller@10d10000 { >> + compatible = "intel,agilex5-clkmgr"; >> + reg = <0x10d10000 0x1000>; >> + #clock-cells = <1>; >> + }; >> + >> + stmmac_axi_setup: stmmac-axi-config { >> + snps,wr_osr_lmt = <31>; >> + snps,rd_osr_lmt = <31>; >> + snps,blen = <0 0 0 32 16 8 4>; >> + }; >> + >> + mtl_rx_setup: rx-queues-config { > >These two nodes do not belong to SoC. Soc is for MMIO-based nodes. > > >> + snps,rx-queues-to-use = <8>; >> + snps,rx-sched-sp; >> + queue0 { >> + snps,dcb-algorithm; >> + snps,map-to-dma-channel = <0x0>; >> + }; >> + queue1 { >> + snps,dcb-algorithm; >> + snps,map-to-dma-channel = <0x1>; >> + }; >> + queue2 { >> + snps,dcb-algorithm; >> + snps,map-to-dma-channel = <0x2>; >> + }; >> + queue3 { >> + snps,dcb-algorithm; >> + snps,map-to-dma-channel = <0x3>; >> + }; >> + queue4 { >> + snps,dcb-algorithm; >> + snps,map-to-dma-channel = <0x4>; >> + }; >> + queue5 { >> + snps,dcb-algorithm; >> + snps,map-to-dma-channel = <0x5>; >> + }; >> + queue6 { >> + snps,dcb-algorithm; >> + snps,map-to-dma-channel = <0x6>; >> + }; >> + queue7 { >> + snps,dcb-algorithm; >> + snps,map-to-dma-channel = <0x7>; >> + }; >> + }; >> + >> + mtl_tx_setup: tx-queues-config { > >This as well > >> + snps,tx-queues-to-use = <8>; >> + snps,tx-sched-wrr; >> + queue0 { >> + snps,weight = <0x09>; >> + snps,dcb-algorithm; >> + }; >> + queue1 { >> + snps,weight = <0x0A>; >> + snps,dcb-algorithm; >> + }; >> + queue2 { >> + snps,weight = <0x0B>; >> + snps,dcb-algorithm; >> + }; >> + queue3 { >> + snps,weight = <0x0C>; >> + snps,dcb-algorithm; >> + }; >> + queue4 { >> + snps,weight = <0x0D>; >> + snps,dcb-algorithm; >> + }; >> + queue5 { >> + snps,weight = <0x0E>; >> + snps,dcb-algorithm; >> + }; >> + queue6 { >> + snps,weight = <0x0F>; >> + snps,dcb-algorithm; >> + }; >> + queue7 { >> + snps,weight = <0x10>; >> + snps,dcb-algorithm; >> + }; >> + }; >> + >> + gmac0: ethernet@10810000 { >> + compatible = "altr,socfpga-stmmac-a10-s10", >> + "snps,dwxgmac-2.10", >> + "snps,dwxgmac"; > >You have broken alignment. > >> + reg = <0x10810000 0x3500>; >> + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, > >In multiple places. Really. > >> + <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-names = "macirq", >> + "macirq_tx0", > >This is ugly. > >> + "macirq_tx1", >> + "macirq_tx2", >> + "macirq_tx3", >> + "macirq_tx4", >> + "macirq_tx5", >> + "macirq_tx6", >> + "macirq_tx7", >> + "macirq_rx0", >> + "macirq_rx1", >> + "macirq_rx2", >> + "macirq_rx3", >> + "macirq_rx4", >> + "macirq_rx5", >> + "macirq_rx6", >> + "macirq_rx7"; >> + mac-address = [00 00 00 00 00 00]; > >Drop, it's SoC file. Will remove these nodes, ethernet related changes will be submitted in separate patch later. > >> + resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; >> + reset-names = "stmmaceth", "stmmaceth-ocp"; >> + tx-fifo-depth = <32768>; >> + rx-fifo-depth = <16384>; >> + snps,multicast-filter-bins = <64>; >> + snps,perfect-filter-entries = <64>; >> + snps,axi-config = <&stmmac_axi_setup>; >> + snps,mtl-rx-config = <&mtl_rx_setup>; >> + snps,mtl-tx-config = <&mtl_tx_setup>; >> + snps,pbl = <32>; >> + snps,pblx8; >> + snps,multi-irq-en; >> + snps,tso; >> + altr,sysmgr-syscon = <&sysmgr 0x44 0>; >> + altr,smtg-hub; >> + snps,rx-vlan-offload; >> + clocks = <&clkmgr AGILEX5_EMAC0_CLK>, <&clkmgr AGILEX5_EMAC_PTP_CLK>; >> + clock-names = "stmmaceth", "ptp_ref"; >> + status = "disabled"; >> + }; >> + >> + i2c0: i2c@10c02800 { >> + #address-cells = <1>; >> + #size-cells = <0>; > >compatible first, reg second. > >> + compatible = "snps,designware-i2c"; >> + reg = <0x10c02800 0x100>; >> + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; >> + resets = <&rst I2C0_RESET>; >> + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; >> + status = "disabled"; >> + }; >> + >> + i2c1: i2c@10c02900 { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + compatible = "snps,designware-i2c"; >> + reg = <0x10c02900 0x100>; >> + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; >> + resets = <&rst I2C1_RESET>; >> + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; >> + status = "disabled"; >> + }; >> + >> + i2c2: i2c@10c02a00 { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + compatible = "snps,designware-i2c"; >> + reg = <0x10c02a00 0x100>; >> + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; >> + resets = <&rst I2C2_RESET>; >> + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; >> + status = "disabled"; >> + }; >> + >> + i2c3: i2c@10c02b00 { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + compatible = "snps,designware-i2c"; >> + reg = <0x10c02b00 0x100>; >> + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; >> + resets = <&rst I2C3_RESET>; >> + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; >> + status = "disabled"; >> + }; >> + >> + i2c4: i2c@10c02c00 { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + compatible = "snps,designware-i2c"; >> + reg = <0x10c02c00 0x100>; >> + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; >> + resets = <&rst I2C4_RESET>; >> + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; >> + status = "disabled"; >> + }; >> + >> + i3c0: i3c@10da0000 { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + compatible = "snps,dw-i3c-master-1.00a"; >> + reg = <0x10da0000 0x1000>; >> + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; >> + resets = <&rst I3C0_RESET>; >> + clocks = <&clkmgr AGILEX5_L4_MP_CLK>; >> + status = "disabled"; >> + }; >> + >> + i3c1: i3c@10da1000 { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + compatible = "snps,dw-i3c-master-1.00a"; >> + reg = <0x10da1000 0x1000>; >> + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; >> + resets = <&rst I3C1_RESET>; >> + clocks = <&clkmgr AGILEX5_L4_MP_CLK>; >> + status = "disabled"; >> + }; >> + >> + gpio1: gpio@10C03300 { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + compatible = "snps,dw-apb-gpio"; >> + reg = <0x10C03300 0x100>; >> + resets = <&rst GPIO1_RESET>; >> + status = "disabled"; >> + >> + portb: gpio-controller@0 { >> + compatible = "snps,dw-apb-gpio-port"; >> + gpio-controller; >> + #gpio-cells = <2>; >> + snps,nr-gpios = <24>; >> + reg = <0>; >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; >> + }; >> + }; >> + >> + mmc: mmc0@10808000 { > >It does not look like you tested the DTS against bindings. Please run `make dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst or https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/ >for instructions). > >Sorry, but your DTS lacks any basic (internal!) review and basic tests with automated tools. > >.. > >> + spi0: spi@10da4000 { >> + compatible = "snps,dw-apb-ssi"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + reg = <0x10da4000 0x1000>; >> + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; >> + resets = <&rst SPIM0_RESET>; >> + reset-names = "spi"; >> + reg-io-width = <4>; >> + num-cs = <4>; >> + clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>; >> + dmas = <&dmac0 2>, <&dmac0 3>; >> + dma-names ="tx", "rx"; >> + >> + status = "disabled"; >> + >> + flash: m25p128@0 { > >It's getting worse... > >> + status = "okay"; > >and worse > >> + compatible = "st,m25p80"; >> + spi-max-frequency = <25000000>; >> + m25p,fast-read; >> + reg = <0>; >> + >> + #address-cells = <1>; >> + #size-cells = <1>; >> + >> + partition@0 { >> + label = "spi_flash_part0"; >> + reg = <0x0 0x100000>; > >and less conforming to style > >> + }; >> + }; >> + > >... and less. >... > >> + >> + chosen { >> + stdout-path = "serial0:115200n8"; >> + bootargs = "console=uart8250,mmio32,0x10c02000,115200n8 \ >> + root=/dev/ram0 rw initrd=0x10000000 init=/sbin/init \ >> + ramdisk_size=10000000 earlycon=uart8250,mmio32,0x10c02000,115200n8 \ >> + panic=-1 nosmp rootfstype=ext3"; > >NAK. Drop entire bootags. > >> + }; >> + >> + leds { >> + compatible = "gpio-leds"; >> + hps0 { > >No, srsly? So all our cleanups for few years mean nothing? > Will fix all the review comments in v2 patch. Thanks, Nirav
On 6/18/23 08:22, niravkumar.l.rabara@intel.com wrote: > From: Niravkumar L Rabara <niravkumar.l.rabara@intel.com> > > The clock manager driver for Agilex5 is very similar to the Agilex Then why create a whole new driver? Surely there's alot of re-use you can do? > platform. This patch makes the necessary changes for the driver to > differentiate between the Agilex and the Agilex5 platforms. > > Signed-off-by: Teh Wen Ping <wen.ping.teh@intel.com> > Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com> > --- > drivers/clk/socfpga/Kconfig | 4 +- > drivers/clk/socfpga/Makefile | 2 +- > drivers/clk/socfpga/clk-agilex5.c | 843 ++++++++++++++++++++++++++++ > drivers/clk/socfpga/clk-pll-s10.c | 48 ++ > drivers/clk/socfpga/stratix10-clk.h | 2 + > 5 files changed, 896 insertions(+), 3 deletions(-) > create mode 100644 drivers/clk/socfpga/clk-agilex5.c > > diff --git a/drivers/clk/socfpga/Kconfig b/drivers/clk/socfpga/Kconfig > index 0cf16b894efb..e82c0cda3245 100644 > --- a/drivers/clk/socfpga/Kconfig > +++ b/drivers/clk/socfpga/Kconfig > @@ -4,7 +4,7 @@ config CLK_INTEL_SOCFPGA > default ARCH_INTEL_SOCFPGA > help > Support for the clock controllers present on Intel SoCFPGA and eASIC > - devices like Aria, Cyclone, Stratix 10, Agilex and N5X eASIC. > + devices like Aria, Cyclone, Stratix 10, Agilex, N5X eASIC and Agilex5. > > if CLK_INTEL_SOCFPGA > > @@ -13,7 +13,7 @@ config CLK_INTEL_SOCFPGA32 > default ARM && ARCH_INTEL_SOCFPGA > > config CLK_INTEL_SOCFPGA64 > - bool "Intel Stratix / Agilex / N5X clock controller support" if COMPILE_TEST && (!ARM64 || !ARCH_INTEL_SOCFPGA) > + bool "Intel Stratix / Agilex / N5X clock / Agilex5 controller support" if COMPILE_TEST && (!ARM64 || !ARCH_INTEL_SOCFPGA) > default ARM64 && ARCH_INTEL_SOCFPGA > > endif # CLK_INTEL_SOCFPGA > diff --git a/drivers/clk/socfpga/Makefile b/drivers/clk/socfpga/Makefile > index e8dfce339c91..a1ea2b988eaf 100644 > --- a/drivers/clk/socfpga/Makefile > +++ b/drivers/clk/socfpga/Makefile > @@ -3,4 +3,4 @@ obj-$(CONFIG_CLK_INTEL_SOCFPGA32) += clk.o clk-gate.o clk-pll.o clk-periph.o \ > clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o > obj-$(CONFIG_CLK_INTEL_SOCFPGA64) += clk-s10.o \ > clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o \ > - clk-agilex.o > + clk-agilex.o clk-agilex5.o > diff --git a/drivers/clk/socfpga/clk-agilex5.c b/drivers/clk/socfpga/clk-agilex5.c > new file mode 100644 > index 000000000000..2d597176a98d > --- /dev/null > +++ b/drivers/clk/socfpga/clk-agilex5.c > @@ -0,0 +1,843 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2022, Intel Corporation It's 2023 now! > + */ > +#include <linux/slab.h> > +#include <linux/clk-provider.h> > +#include <linux/of_device.h> > +#include <linux/of_address.h> > +#include <linux/platform_device.h> > + > +#include <dt-bindings/clock/agilex5-clock.h> > + > +#include "stratix10-clk.h" > + > +static const struct clk_parent_data pll_mux[] = { > + { > + .fw_name = "osc1", > + .name = "osc1", > + }, > + { > + .fw_name = "cb-intosc-hs-div2-clk", > + .name = "cb-intosc-hs-div2-clk", > + }, > + { > + .fw_name = "f2s-free-clk", > + .name = "f2s-free-clk", > + }, > +}; > + > +static const struct clk_parent_data boot_mux[] = { > + { > + .fw_name = "osc1", > + .name = "osc1", > + }, > + { > + .fw_name = "cb-intosc-hs-div2-clk", > + .name = "cb-intosc-hs-div2-clk", > + }, > +}; > + > +static const struct clk_parent_data core0_free_mux[] = { > + { > + .fw_name = "main_pll_c1", > + .name = "main_pll_c1", > + }, > + { > + .fw_name = "peri_pll_c0", > + .name = "peri_pll_c0", > + }, > + { > + .fw_name = "osc1", > + .name = "osc1", > + }, > + { > + .fw_name = "cb-intosc-hs-div2-clk", > + .name = "cb-intosc-hs-div2-clk", > + }, > + { > + .fw_name = "f2s-free-clk", > + .name = "f2s-free-clk", > + }, > +}; > + > +static const struct clk_parent_data core1_free_mux[] = { > + { > + .fw_name = "main_pll_c1", > + .name = "main_pll_c1", > + }, > + { > + .fw_name = "peri_pll_c0", > + .name = "peri_pll_c0", > + }, > + { > + .fw_name = "osc1", > + .name = "osc1", > + }, > + { > + .fw_name = "cb-intosc-hs-div2-clk", > + .name = "cb-intosc-hs-div2-clk", > + }, > + { > + .fw_name = "f2s-free-clk", > + .name = "f2s-free-clk", > + }, > +}; > + > +static const struct clk_parent_data core2_free_mux[] = { > + { > + .fw_name = "main_pll_c0", > + .name = "main_pll_c0", > + }, > + { > + .fw_name = "osc1", > + .name = "osc1", > + }, > + { > + .fw_name = "cb-intosc-hs-div2-clk", > + .name = "cb-intosc-hs-div2-clk", > + }, > + { > + .fw_name = "f2s-free-clk", > + .name = "f2s-free-clk", > + }, > +}; > + > +static const struct clk_parent_data core3_free_mux[] = { > + { > + .fw_name = "main_pll_c0", > + .name = "main_pll_c0", > + }, > + { > + .fw_name = "osc1", > + .name = "osc1", > + }, > + { > + .fw_name = "cb-intosc-hs-div2-clk", > + .name = "cb-intosc-hs-div2-clk", > + }, > + { > + .fw_name = "f2s-free-clk", > + .name = "f2s-free-clk", > + }, > +}; > + > +static const struct clk_parent_data dsu_free_mux[] = { > + { > + .fw_name = "main_pll_c2", > + .name = "main_pll_c2", > + }, > + { > + .fw_name = "peri_pll_c0", > + .name = "peri_pll_c0", > + }, > + { > + .fw_name = "osc1", > + .name = "osc1", > + }, > + { > + .fw_name = "cb-intosc-hs-div2-clk", > + .name = "cb-intosc-hs-div2-clk", > + }, > + { > + .fw_name = "f2s-free-clk", > + .name = "f2s-free-clk", > + }, > +}; > + > +static const struct clk_parent_data noc_free_mux[] = { > + { > + .fw_name = "main_pll_c3", > + .name = "main_pll_c3", > + }, > + { > + .fw_name = "peri_pll_c1", > + .name = "peri_pll_c1", > + }, > + { > + .fw_name = "osc1", > + .name = "osc1", > + }, > + { > + .fw_name = "cb-intosc-hs-div2-clk", > + .name = "cb-intosc-hs-div2-clk", > + }, > + { > + .fw_name = "f2s-free-clk", > + .name = "f2s-free-clk", > + }, > +}; > + > +static const struct clk_parent_data emaca_free_mux[] = { > + { > + .fw_name = "main_pll_c1", > + .name = "main_pll_c1", > + }, > + { > + .fw_name = "peri_pll_c3", > + .name = "peri_pll_c3", > + }, > + { > + .fw_name = "osc1", > + .name = "osc1", > + }, > + { > + .fw_name = "cb-intosc-hs-div2-clk", > + .name = "cb-intosc-hs-div2-clk", > + }, > + { > + .fw_name = "f2s-free-clk", > + .name = "f2s-free-clk", > + }, > +}; > + > +static const struct clk_parent_data emacb_free_mux[] = { > + { > + .fw_name = "main_pll_c1", > + .name = "main_pll_c1", > + }, > + { > + .fw_name = "peri_pll_c3", > + .name = "peri_pll_c3", > + }, > + { > + .fw_name = "osc1", > + .name = "osc1", > + }, > + { > + .fw_name = "cb-intosc-hs-div2-clk", > + .name = "cb-intosc-hs-div2-clk", > + }, > + { > + .fw_name = "f2s-free-clk", > + .name = "f2s-free-clk", > + }, > +}; > + > +static const struct clk_parent_data emac_ptp_free_mux[] = { > + { > + .fw_name = "main_pll_c1", > + .name = "main_pll_c1", > + }, > + { > + .fw_name = "peri_pll_c3", > + .name = "peri_pll_c3", > + }, > + { > + .fw_name = "osc1", > + .name = "osc1", > + }, > + { > + .fw_name = "cb-intosc-hs-div2-clk", > + .name = "cb-intosc-hs-div2-clk", > + }, > + { > + .fw_name = "f2s-free-clk", > + .name = "f2s-free-clk", > + }, > +}; > + > +static const struct clk_parent_data gpio_db_free_mux[] = { > + { > + .fw_name = "main_pll_c3", > + .name = "main_pll_c3", > + }, > + { > + .fw_name = "peri_pll_c1", > + .name = "peri_pll_c1", > + }, > + { > + .fw_name = "osc1", > + .name = "osc1", > + }, > + { > + .fw_name = "cb-intosc-hs-div2-clk", > + .name = "cb-intosc-hs-div2-clk", > + }, > + { > + .fw_name = "f2s-free-clk", > + .name = "f2s-free-clk", > + }, > +}; > + > +static const struct clk_parent_data psi_ref_free_mux[] = { > + { > + .fw_name = "main_pll_c1", > + .name = "main_pll_c1", > + }, > + { > + .fw_name = "peri_pll_c3", > + .name = "peri_pll_c3", > + }, > + { > + .fw_name = "osc1", > + .name = "osc1", > + }, > + { > + .fw_name = "cb-intosc-hs-div2-clk", > + .name = "cb-intosc-hs-div2-clk", > + }, > + { > + .fw_name = "f2s-free-clk", > + .name = "f2s-free-clk", > + }, > +}; > + > +static const struct clk_parent_data usb31_free_mux[] = { > + { > + .fw_name = "main_pll_c3", > + .name = "main_pll_c3", > + }, > + { > + .fw_name = "peri_pll_c2", > + .name = "peri_pll_c2", > + }, > + { > + .fw_name = "osc1", > + .name = "osc1", > + }, > + { > + .fw_name = "cb-intosc-hs-div2-clk", > + .name = "cb-intosc-hs-div2-clk", > + }, > + { > + .fw_name = "f2s-free-clk", > + .name = "f2s-free-clk", > + }, > +}; > + > +static const struct clk_parent_data s2f_usr0_free_mux[] = { > + { > + .fw_name = "main_pll_c1", > + .name = "main_pll_c1", > + }, > + { > + .fw_name = "peri_pll_c3", > + .name = "peri_pll_c3", > + }, > + { > + .fw_name = "osc1", > + .name = "osc1", > + }, > + { > + .fw_name = "cb-intosc-hs-div2-clk", > + .name = "cb-intosc-hs-div2-clk", > + }, > + { > + .fw_name = "f2s-free-clk", > + .name = "f2s-free-clk", > + }, > +}; > + > +static const struct clk_parent_data s2f_usr1_free_mux[] = { > + { > + .fw_name = "main_pll_c1", > + .name = "main_pll_c1", > + }, > + { > + .fw_name = "peri_pll_c3", > + .name = "peri_pll_c3", > + }, > + { > + .fw_name = "osc1", > + .name = "osc1", > + }, > + { > + .fw_name = "cb-intosc-hs-div2-clk", > + .name = "cb-intosc-hs-div2-clk", > + }, > + { > + .fw_name = "f2s-free-clk", > + .name = "f2s-free-clk", > + }, > +}; > + > +static const struct clk_parent_data core0_mux[] = { > + { > + .fw_name = "core0_free_clk", > + .name = "core0_free_clk", > + }, > + { > + .fw_name = "boot_clk", > + .name = "boot_clk", > + }, > +}; > + > +static const struct clk_parent_data core1_mux[] = { > + { > + .fw_name = "core1_free_clk", > + .name = "core1_free_clk", > + }, > + { > + .fw_name = "boot_clk", > + .name = "boot_clk", > + }, > +}; > + > +static const struct clk_parent_data core2_mux[] = { > + { > + .fw_name = "core2_free_clk", > + .name = "core2_free_clk", > + }, > + { > + .fw_name = "boot_clk", > + .name = "boot_clk", > + }, > +}; > + > +static const struct clk_parent_data core3_mux[] = { > + { > + .fw_name = "core3_free_clk", > + .name = "core3_free_clk", > + }, > + { > + .fw_name = "boot_clk", > + .name = "boot_clk", > + }, > +}; > + > +static const struct clk_parent_data dsu_mux[] = { > + { > + .fw_name = "dsu_free_clk", > + .name = "dsu_free_clk", > + }, > + { > + .fw_name = "boot_clk", > + .name = "boot_clk", > + }, > +}; > + > +static const struct clk_parent_data emac_mux[] = { > + { > + .fw_name = "emaca_free_clk", > + .name = "emaca_free_clk", > + }, > + { > + .fw_name = "emacb_free_clk", > + .name = "emacb_free_clk", > + }, > + { > + .fw_name = "boot_clk", > + .name = "boot_clk", > + }, > +}; > + > +static const struct clk_parent_data noc_mux[] = { > + { > + .fw_name = "noc_free_clk", > + .name = "noc_free_clk", > + }, > + { > + .fw_name = "boot_clk", > + .name = "boot_clk", > + }, > +}; > + > +static const struct clk_parent_data s2f_user0_mux[] = { > + { > + .fw_name = "s2f_user0_free_clk", > + .name = "s2f_user0_free_clk", > + }, > + { > + .fw_name = "boot_clk", > + .name = "boot_clk", > + }, > +}; > + > +static const struct clk_parent_data s2f_user1_mux[] = { > + { > + .fw_name = "s2f_user1_free_clk", > + .name = "s2f_user1_free_clk", > + }, > + { > + .fw_name = "boot_clk", > + .name = "boot_clk", > + }, > +}; > + > +static const struct clk_parent_data psi_mux[] = { > + { > + .fw_name = "psi_ref_free_clk", > + .name = "psi_ref_free_clk", > + }, > + { > + .fw_name = "boot_clk", > + .name = "boot_clk", > + }, > +}; > + > +static const struct clk_parent_data gpio_db_mux[] = { > + { > + .fw_name = "gpio_db_free_clk", > + .name = "gpio_db_free_clk", > + }, > + { > + .fw_name = "boot_clk", > + .name = "boot_clk", > + }, > +}; > + > +static const struct clk_parent_data emac_ptp_mux[] = { > + { > + .fw_name = "emac_ptp_free_clk", > + .name = "emac_ptp_free_clk", > + }, > + { > + .fw_name = "boot_clk", > + .name = "boot_clk", > + }, > +}; > + > +static const struct clk_parent_data usb31_mux[] = { > + { > + .fw_name = "usb31_free_clk", > + .name = "usb31_free_clk", > + }, > + { > + .fw_name = "boot_clk", > + .name = "boot_clk", > + }, > +}; > + > +/* > + * TODO - Clocks in AO (always on) controller Remove your TODO, so did you do it already? > + * 2 main PLLs only > + */ > +static const struct stratix10_pll_clock agilex5_pll_clks[] = { > + { AGILEX5_BOOT_CLK, "boot_clk", boot_mux, ARRAY_SIZE(boot_mux), 0, > + 0x0 }, > + { AGILEX5_MAIN_PLL_CLK, "main_pll", pll_mux, ARRAY_SIZE(pll_mux), 0, > + 0x48 }, > + { AGILEX5_PERIPH_PLL_CLK, "periph_pll", pll_mux, ARRAY_SIZE(pll_mux), 0, > + 0x9C }, > +}; > + > +static const struct stratix10_perip_c_clock agilex5_main_perip_c_clks[] = { > + { AGILEX5_MAIN_PLL_C0_CLK, "main_pll_c0", "main_pll", NULL, 1, 0, > + 0x5C }, > + { AGILEX5_MAIN_PLL_C1_CLK, "main_pll_c1", "main_pll", NULL, 1, 0, > + 0x60 }, > + { AGILEX5_MAIN_PLL_C2_CLK, "main_pll_c2", "main_pll", NULL, 1, 0, > + 0x64 }, > + { AGILEX5_MAIN_PLL_C3_CLK, "main_pll_c3", "main_pll", NULL, 1, 0, > + 0x68 }, > + { AGILEX5_PERIPH_PLL_C0_CLK, "peri_pll_c0", "periph_pll", NULL, 1, 0, > + 0xB0 }, > + { AGILEX5_PERIPH_PLL_C1_CLK, "peri_pll_c1", "periph_pll", NULL, 1, 0, > + 0xB4 }, > + { AGILEX5_PERIPH_PLL_C2_CLK, "peri_pll_c2", "periph_pll", NULL, 1, 0, > + 0xB8 }, > + { AGILEX5_PERIPH_PLL_C3_CLK, "peri_pll_c3", "periph_pll", NULL, 1, 0, > + 0xBC }, > +}; > + > +/* Non-SW clock-gated enabled clocks */ > +static const struct stratix10_perip_cnt_clock agilex5_main_perip_cnt_clks[] = { > + { AGILEX5_CORE0_FREE_CLK, "core0_free_clk", NULL, core0_free_mux, > + ARRAY_SIZE(core0_free_mux), 0, 0x0104, 0, 0, 0}, > + { AGILEX5_CORE1_FREE_CLK, "core1_free_clk", NULL, core1_free_mux, > + ARRAY_SIZE(core1_free_mux), 0, 0x0104, 0, 0, 0}, > + { AGILEX5_CORE2_FREE_CLK, "core2_free_clk", NULL, core2_free_mux, > + ARRAY_SIZE(core2_free_mux), 0, 0x010C, 0, 0, 0}, > + { AGILEX5_CORE3_FREE_CLK, "core3_free_clk", NULL, core3_free_mux, > + ARRAY_SIZE(core3_free_mux), 0, 0x0110, 0, 0, 0}, > + { AGILEX5_DSU_FREE_CLK, "dsu_free_clk", NULL, dsu_free_mux, > + ARRAY_SIZE(dsu_free_mux), 0, 0x0100, 0, 0, 0}, > + { AGILEX5_NOC_FREE_CLK, "noc_free_clk", NULL, noc_free_mux, > + ARRAY_SIZE(noc_free_mux), 0, 0x40, 0, 0, 0 }, > + { AGILEX5_EMAC_A_FREE_CLK, "emaca_free_clk", NULL, emaca_free_mux, > + ARRAY_SIZE(emaca_free_mux), 0, 0xD4, 0, 0x88, 0 }, > + { AGILEX5_EMAC_B_FREE_CLK, "emacb_free_clk", NULL, emacb_free_mux, > + ARRAY_SIZE(emacb_free_mux), 0, 0xD8, 0, 0x88, 1 }, > + { AGILEX5_EMAC_PTP_FREE_CLK, "emac_ptp_free_clk", NULL, > + emac_ptp_free_mux, ARRAY_SIZE(emac_ptp_free_mux), 0, 0xDC, 0, 0x88, > + 2 }, > + { AGILEX5_GPIO_DB_FREE_CLK, "gpio_db_free_clk", NULL, gpio_db_free_mux, > + ARRAY_SIZE(gpio_db_free_mux), 0, 0xE0, 0, 0x88, 3 }, > + { AGILEX5_S2F_USER0_FREE_CLK, "s2f_user0_free_clk", NULL, > + s2f_usr0_free_mux, ARRAY_SIZE(s2f_usr0_free_mux), 0, 0xE8, 0, 0x30, > + 2 }, > + { AGILEX5_S2F_USER1_FREE_CLK, "s2f_user1_free_clk", NULL, > + s2f_usr1_free_mux, ARRAY_SIZE(s2f_usr1_free_mux), 0, 0xEC, 0, 0x88, > + 5 }, > + { AGILEX5_PSI_REF_FREE_CLK, "psi_ref_free_clk", NULL, psi_ref_free_mux, > + ARRAY_SIZE(psi_ref_free_mux), 0, 0xF0, 0, 0x88, 6 }, > + { AGILEX5_USB31_FREE_CLK, "usb31_free_clk", NULL, usb31_free_mux, > + ARRAY_SIZE(usb31_free_mux), 0, 0xF8, 0, 0x88, 7}, > +}; > + > +/* SW Clock gate enabled clocks */ > +static const struct stratix10_gate_clock agilex5_gate_clks[] = { > + /* Main PLL0 Begin */ > + /* MPU clocks */ > + { AGILEX5_CORE0_CLK, "core0_clk", NULL, core0_mux, > + ARRAY_SIZE(core0_mux), 0, 0x24, 8, 0, 0, 0, 0x30, 5, 0 }, > + { AGILEX5_CORE1_CLK, "core1_clk", NULL, core1_mux, > + ARRAY_SIZE(core1_mux), 0, 0x24, 9, 0, 0, 0, 0x30, 5, 0 }, > + { AGILEX5_CORE2_CLK, "core2_clk", NULL, core2_mux, > + ARRAY_SIZE(core2_mux), 0, 0x24, 10, 0, 0, 0, 0x30, 6, 0 }, > + { AGILEX5_CORE3_CLK, "core3_clk", NULL, core3_mux, > + ARRAY_SIZE(core3_mux), 0, 0x24, 11, 0, 0, 0, 0x30, 7, 0 }, > + { AGILEX5_MPU_CLK, "dsu_clk", NULL, dsu_mux, ARRAY_SIZE(dsu_mux), 0, 0, > + 0, 0, 0, 0, 0x34, 4, 0 }, > + { AGILEX5_MPU_PERIPH_CLK, "mpu_periph_clk", NULL, dsu_mux, > + ARRAY_SIZE(dsu_mux), 0, 0, 0, 0x44, 20, 2, 0x34, 4, 0 }, > + { AGILEX5_MPU_CCU_CLK, "mpu_ccu_clk", NULL, dsu_mux, > + ARRAY_SIZE(dsu_mux), 0, 0, 0, 0x44, 18, 2, 0x34, 4, 0 }, > + > + /* l4 main clk has no divider now */ > + { AGILEX5_L4_MAIN_CLK, "l4_main_clk", NULL, noc_mux, > + ARRAY_SIZE(noc_mux), 0, 0x24, 1, 0, 0, 0, 0, 0, 0 }, > + { AGILEX5_L4_MP_CLK, "l4_mp_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, > + 0x24, 2, 0x44, 4, 2, 0x30, 1, 0 }, > + { AGILEX5_L4_SYS_FREE_CLK, "l4_sys_free_clk", NULL, noc_mux, > + ARRAY_SIZE(noc_mux), 0, 0, 0, 0x44, 2, 2, 0x30, 1, 0 }, > + { AGILEX5_L4_SP_CLK, "l4_sp_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), > + CLK_IS_CRITICAL, 0x24, 3, 0x44, 6, 2, 0x30, 1, 0 }, > + > + /* Core sight clocks*/ > + { AGILEX5_CS_AT_CLK, "cs_at_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, > + 0x24, 4, 0x44, 24, 2, 0x30, 1, 0 }, > + { AGILEX5_CS_TRACE_CLK, "cs_trace_clk", NULL, noc_mux, > + ARRAY_SIZE(noc_mux), 0, 0x24, 4, 0x44, 26, 2, 0x30, 1, 0 }, > + { AGILEX5_CS_PDBG_CLK, "cs_pdbg_clk", "cs_at_clk", NULL, 1, 0, 0x24, 4, > + 0x44, 28, 1, 0, 0, 0 }, > + /* Main PLL0 End */ > + > + /* Main Peripheral PLL1 Begin */ > + { AGILEX5_EMAC0_CLK, "emac0_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), > + 0, 0x7C, 0, 0, 0, 0, 0x94, 26, 0 }, > + { AGILEX5_EMAC1_CLK, "emac1_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), > + 0, 0x7C, 1, 0, 0, 0, 0x94, 27, 0 }, > + { AGILEX5_EMAC2_CLK, "emac2_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), > + 0, 0x7C, 2, 0, 0, 0, 0x94, 28, 0 }, > + { AGILEX5_EMAC_PTP_CLK, "emac_ptp_clk", NULL, emac_ptp_mux, > + ARRAY_SIZE(emac_ptp_mux), 0, 0x7C, 3, 0, 0, 0, 0x88, 2, 0 }, > + { AGILEX5_GPIO_DB_CLK, "gpio_db_clk", NULL, gpio_db_mux, > + ARRAY_SIZE(gpio_db_mux), 0, 0x7C, 4, 0x98, 0, 16, 0x88, 3, 0 }, > + /* Main Peripheral PLL1 End */ > + > + /* Peripheral clocks */ > + { AGILEX5_S2F_USER0_CLK, "s2f_user0_clk", NULL, s2f_user0_mux, > + ARRAY_SIZE(s2f_user0_mux), 0, 0x24, 6, 0, 0, 0, 0x30, 2, 0 }, > + { AGILEX5_S2F_USER1_CLK, "s2f_user1_clk", NULL, s2f_user1_mux, > + ARRAY_SIZE(s2f_user1_mux), 0, 0x7C, 6, 0, 0, 0, 0x88, 5, 0 }, > + { AGILEX5_PSI_REF_CLK, "psi_ref_clk", NULL, psi_mux, > + ARRAY_SIZE(psi_mux), 0, 0x7C, 7, 0, 0, 0, 0x88, 6, 0 }, > + { AGILEX5_USB31_SUSPEND_CLK, "usb31_suspend_clk", NULL, usb31_mux, > + ARRAY_SIZE(usb31_mux), 0, 0x7C, 25, 0, 0, 0, 0x88, 7, 0 }, > + { AGILEX5_USB31_BUS_CLK_EARLY, "usb31_bus_clk_early", "l4_main_clk", > + NULL, 1, 0, 0x7C, 25, 0, 0, 0, 0, 0, 0 }, > + { AGILEX5_USB2OTG_HCLK, "usb2otg_hclk", "l4_mp_clk", NULL, 1, 0, 0x7C, > + 8, 0, 0, 0, 0, 0, 0 }, > + { AGILEX5_SPIM_0_CLK, "spim_0_clk", "l4_mp_clk", NULL, 1, 0, 0x7C, 9, > + 0, 0, 0, 0, 0, 0 }, > + { AGILEX5_SPIM_1_CLK, "spim_1_clk", "l4_mp_clk", NULL, 1, 0, 0x7C, 11, > + 0, 0, 0, 0, 0, 0 }, > + { AGILEX5_SPIS_0_CLK, "spis_0_clk", "l4_sp_clk", NULL, 1, 0, 0x7C, 12, > + 0, 0, 0, 0, 0, 0 }, > + { AGILEX5_SPIS_1_CLK, "spis_1_clk", "l4_sp_clk", NULL, 1, 0, 0x7C, 13, > + 0, 0, 0, 0, 0, 0 }, > + { AGILEX5_DMA_CORE_CLK, "dma_core_clk", "l4_mp_clk", NULL, 1, 0, 0x7C, > + 14, 0, 0, 0, 0, 0, 0 }, > + { AGILEX5_DMA_HS_CLK, "dma_hs_clk", "l4_mp_clk", NULL, 1, 0, 0x7C, 14, > + 0, 0, 0, 0, 0, 0 }, > + { AGILEX5_I3C_0_CORE_CLK, "i3c_0_core_clk", "l4_mp_clk", NULL, 1, 0, > + 0x7C, 18, 0, 0, 0, 0, 0, 0 }, > + { AGILEX5_I3C_1_CORE_CLK, "i3c_1_core_clk", "l4_mp_clk", NULL, 1, 0, > + 0x7C, 19, 0, 0, 0, 0, 0, 0 }, > + { AGILEX5_I2C_0_PCLK, "i2c_0_pclk", "l4_sp_clk", NULL, 1, 0, 0x7C, 15, > + 0, 0, 0, 0, 0, 0 }, > + { AGILEX5_I2C_1_PCLK, "i2c_1_pclk", "l4_sp_clk", NULL, 1, 0, 0x7C, 16, > + 0, 0, 0, 0, 0, 0 }, > + { AGILEX5_I2C_EMAC0_PCLK, "i2c_emac0_pclk", "l4_sp_clk", NULL, 1, 0, > + 0x7C, 17, 0, 0, 0, 0, 0, 0 }, > + { AGILEX5_I2C_EMAC1_PCLK, "i2c_emac1_pclk", "l4_sp_clk", NULL, 1, 0, > + 0x7C, 22, 0, 0, 0, 0, 0, 0 }, > + { AGILEX5_I2C_EMAC2_PCLK, "i2c_emac2_pclk", "l4_sp_clk", NULL, 1, 0, > + 0x7C, 27, 0, 0, 0, 0, 0, 0 }, > + { AGILEX5_UART_0_PCLK, "uart_0_pclk", "l4_sp_clk", NULL, 1, 0, 0x7C, 20, > + 0, 0, 0, 0, 0, 0 }, > + { AGILEX5_UART_1_PCLK, "uart_1_pclk", "l4_sp_clk", NULL, 1, 0, 0x7C, 21, > + 0, 0, 0, 0, 0, 0 }, > + { AGILEX5_SPTIMER_0_PCLK, "sptimer_0_pclk", "l4_sp_clk", NULL, 1, 0, > + 0x7C, 23, 0, 0, 0, 0, 0, 0 }, > + { AGILEX5_SPTIMER_1_PCLK, "sptimer_1_pclk", "l4_sp_clk", NULL, 1, 0, > + 0x7C, 24, 0, 0, 0, 0, 0, 0 }, > + > + /*NAND, SD/MMC and SoftPHY overall clocking*/ > + { AGILEX5_DFI_CLK, "dfi_clk", "l4_mp_clk", NULL, 1, 0, 0, 0, 0x44, 16, > + 2, 0, 0, 0 }, > + { AGILEX5_NAND_NF_CLK, "nand_nf_clk", "dfi_clk", NULL, 1, 0, 0x7C, 10, > + 0, 0, 0, 0, 0, 0 }, > + { AGILEX5_NAND_BCH_CLK, "nand_bch_clk", "l4_mp_clk", NULL, 1, 0, 0x7C, > + 10, 0, 0, 0, 0, 0, 0 }, > + { AGILEX5_SDMMC_SDPHY_REG_CLK, "sdmmc_sdphy_reg_clk", "l4_mp_clk", NULL, > + 1, 0, 0x7C, 5, 0, 0, 0, 0, 0, 0 }, > + { AGILEX5_SDMCLK, "sdmclk", "dfi_clk", NULL, 1, 0, 0x7C, 5, 0, 0, 0, 0, > + 0, 0 }, > + { AGILEX5_SOFTPHY_REG_PCLK, "softphy_reg_pclk", "l4_mp_clk", NULL, 1, 0, > + 0x7C, 26, 0, 0, 0, 0, 0, 0 }, > + { AGILEX5_SOFTPHY_PHY_CLK, "softphy_phy_clk", "l4_mp_clk", NULL, 1, 0, > + 0x7C, 26, 0x44, 16, 2, 0, 0, 0 }, > + { AGILEX5_SOFTPHY_CTRL_CLK, "softphy_ctrl_clk", "dfi_clk", NULL, 1, 0, > + 0x7C, 26, 0, 0, 0, 0, 0, 0 }, > +}; > + As far as I can tell, there are very little differences between this and Agilex! Please reuse! > +static int > +agilex5_clk_register_c_perip(const struct stratix10_perip_c_clock *clks, > + int nums, struct stratix10_clock_data *data) > +{ > + struct clk_hw *hw_clk; > + void __iomem *base = data->base; > + int i; > + > + for (i = 0; i < nums; i++) { > + hw_clk = s10_register_periph(&clks[i], base); > + if (IS_ERR(hw_clk)) { > + pr_err("%s: failed to register clock %s\n", __func__, > + clks[i].name); > + continue; > + } > + data->clk_data.hws[clks[i].id] = hw_clk; > + } > + return 0; > +} > + > +static int > +agilex5_clk_register_cnt_perip(const struct stratix10_perip_cnt_clock *clks, > + int nums, struct stratix10_clock_data *data) > +{ > + struct clk_hw *hw_clk; > + void __iomem *base = data->base; > + int i; > + > + for (i = 0; i < nums; i++) { > + hw_clk = s10_register_cnt_periph(&clks[i], base); > + if (IS_ERR(hw_clk)) { > + pr_err("%s: failed to register clock %s\n", __func__, > + clks[i].name); > + continue; > + } > + data->clk_data.hws[clks[i].id] = hw_clk; > + } > + > + return 0; > +} > + > +static int agilex5_clk_register_gate(const struct stratix10_gate_clock *clks, > + int nums, > + struct stratix10_clock_data *data) > +{ > + struct clk_hw *hw_clk; > + void __iomem *base = data->base; > + int i; > + > + for (i = 0; i < nums; i++) { > + hw_clk = agilex_register_gate(&clks[i], base); > + if (IS_ERR(hw_clk)) { > + pr_err("%s: failed to register clock %s\n", __func__, > + clks[i].name); > + continue; > + } > + data->clk_data.hws[clks[i].id] = hw_clk; > + } > + > + return 0; > +} > + > +static int agilex5_clk_register_pll(const struct stratix10_pll_clock *clks, > + int nums, struct stratix10_clock_data *data) > +{ > + struct clk_hw *hw_clk; > + void __iomem *base = data->base; > + int i; > + > + for (i = 0; i < nums; i++) { > + hw_clk = agilex5_register_pll(&clks[i], base); > + if (IS_ERR(hw_clk)) { > + pr_err("%s: failed to register clock %s\n", __func__, > + clks[i].name); > + continue; > + } > + data->clk_data.hws[clks[i].id] = hw_clk; > + } > + > + return 0; > +} > + > +static int agilex5_clkmgr_init(struct platform_device *pdev) > +{ > + struct device_node *np = pdev->dev.of_node; > + struct device *dev = &pdev->dev; > + struct stratix10_clock_data *clk_data; > + struct resource *res; > + void __iomem *base; > + int i, num_clks; > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + base = devm_ioremap_resource(dev, res); > + if (IS_ERR(base)) > + return PTR_ERR(base); > + > + num_clks = AGILEX5_NUM_CLKS; > + > + clk_data = devm_kzalloc(dev, > + struct_size(clk_data, clk_data.hws, num_clks), > + GFP_KERNEL); > + if (!clk_data) > + return -ENOMEM; > + > + for (i = 0; i < num_clks; i++) > + clk_data->clk_data.hws[i] = ERR_PTR(-ENOENT); > + > + clk_data->base = base; > + clk_data->clk_data.num = num_clks; > + > + agilex5_clk_register_pll(agilex5_pll_clks, ARRAY_SIZE(agilex5_pll_clks), > + clk_data); > + > + agilex5_clk_register_c_perip(agilex5_main_perip_c_clks, > + ARRAY_SIZE(agilex5_main_perip_c_clks), > + clk_data); > + > + agilex5_clk_register_cnt_perip(agilex5_main_perip_cnt_clks, > + ARRAY_SIZE(agilex5_main_perip_cnt_clks), > + clk_data); > + > + agilex5_clk_register_gate(agilex5_gate_clks, > + ARRAY_SIZE(agilex5_gate_clks), clk_data); > + > + of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data->clk_data); > + return 0; > +} > + > +static int agilex5_clkmgr_probe(struct platform_device *pdev) > +{ > + int (*probe_func)(struct platform_device *init_func); > + > + probe_func = of_device_get_match_data(&pdev->dev); > + if (!probe_func) > + return -ENODEV; > + return probe_func(pdev); > +} > + > +static const struct of_device_id agilex5_clkmgr_match_table[] = { > + { .compatible = "intel,agilex5-clkmgr", .data = agilex5_clkmgr_init }, > + {} > +}; > + > +static struct platform_driver agilex5_clkmgr_driver = { > + .probe = agilex5_clkmgr_probe, > + .driver = { > + .name = "agilex5-clkmgr", > + .suppress_bind_attrs = true, > + .of_match_table = agilex5_clkmgr_match_table, > + }, > +}; > + > +static int __init agilex5_clk_init(void) > +{ > + return platform_driver_register(&agilex5_clkmgr_driver); > +} > +core_initcall(agilex5_clk_init); > diff --git a/drivers/clk/socfpga/clk-pll-s10.c b/drivers/clk/socfpga/clk-pll-s10.c > index 1d82737befd3..e3367d34bc55 100644 > --- a/drivers/clk/socfpga/clk-pll-s10.c > +++ b/drivers/clk/socfpga/clk-pll-s10.c > @@ -175,6 +175,14 @@ static const struct clk_ops agilex_clk_pll_ops = { > .prepare = clk_pll_prepare, > }; > > +/* TODO need to fix, Agilex5 SM requires change */ > +static const struct clk_ops agilex5_clk_pll_ops = { > + /* TODO This may require a custom Agilex5 implementation */ > + .recalc_rate = agilex_clk_pll_recalc_rate, > + .get_parent = clk_pll_get_parent, > + .prepare = clk_pll_prepare, > +}; > + > static const struct clk_ops clk_pll_ops = { > .recalc_rate = clk_pll_recalc_rate, > .get_parent = clk_pll_get_parent, > @@ -304,3 +312,43 @@ struct clk_hw *n5x_register_pll(const struct stratix10_pll_clock *clks, > } > return hw_clk; > } > + > +struct clk_hw *agilex5_register_pll(const struct stratix10_pll_clock *clks, > + void __iomem *reg) > +{ > + struct clk_hw *hw_clk; > + struct socfpga_pll *pll_clk; > + struct clk_init_data init; > + const char *name = clks->name; > + int ret; > + > + pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL); > + if (WARN_ON(!pll_clk)) > + return NULL; > + > + pll_clk->hw.reg = reg + clks->offset; > + > + if (streq(name, SOCFPGA_BOOT_CLK)) > + init.ops = &clk_boot_ops; > + else > + init.ops = &agilex5_clk_pll_ops; > + > + init.name = name; > + init.flags = clks->flags; > + > + init.num_parents = clks->num_parents; > + init.parent_names = NULL; > + init.parent_data = clks->parent_data; > + pll_clk->hw.hw.init = &init; > + > + pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER; > + hw_clk = &pll_clk->hw.hw; > + > + ret = clk_hw_register(NULL, hw_clk); > + if (ret) { > + kfree(pll_clk); > + return ERR_PTR(ret); > + } > + return hw_clk; > +} Both functions are identical to Agilex, so why the need to recreate? > + > diff --git a/drivers/clk/socfpga/stratix10-clk.h b/drivers/clk/socfpga/stratix10-clk.h > index 75234e0783e1..468e0f0ab4ab 100644 > --- a/drivers/clk/socfpga/stratix10-clk.h > +++ b/drivers/clk/socfpga/stratix10-clk.h > @@ -77,6 +77,8 @@ struct clk_hw *agilex_register_pll(const struct stratix10_pll_clock *clks, > void __iomem *reg); > struct clk_hw *n5x_register_pll(const struct stratix10_pll_clock *clks, > void __iomem *reg); > +struct clk_hw *agilex5_register_pll(const struct stratix10_pll_clock *clks, > + void __iomem *reg); > struct clk_hw *s10_register_periph(const struct stratix10_perip_c_clock *clks, > void __iomem *reg); > struct clk_hw *n5x_register_periph(const struct n5x_perip_c_clock *clks, I'd like for you to send this whole patchset for my internal review before you send out a V2! Dinh
From: Niravkumar L Rabara <niravkumar.l.rabara@intel.com> This patch set introduce the changes required for Agilx5 platform. patch [1/4] - Introduced compatible string for Agilex5 board patch [2/4] - Add reset and clock header and yaml file. patch [3/4] - Add clock driver for Agilex5 platform. This patch depends on patch 2. patch [4/4] - Add device tree files, socfpga_agilex5_socdk_swvp.dts is used for Virtual Platform (SIMICS) and socfpga_agilex5_socdk_nand.dts is used for NAND Flash based board. This patch depends on patch 3. Niravkumar L Rabara (4): dt-bindings: intel: Add Intel Agilex5 compatible dt-bindings: clock: Add Intel Agilex5 clocks and resets clk: socfpga: agilex5: Add clock driver for Agilex5 platform arm64: dts: agilex5: Add initial support for Intel's Agilex5 SoCFPGA .../bindings/arm/intel,socfpga.yaml | 1 + .../bindings/clock/intel,agilex5.yaml | 42 + arch/arm64/boot/dts/intel/Makefile | 3 + .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 641 +++++++++++++ .../boot/dts/intel/socfpga_agilex5_socdk.dts | 184 ++++ .../dts/intel/socfpga_agilex5_socdk_nand.dts | 131 +++ .../dts/intel/socfpga_agilex5_socdk_swvp.dts | 248 ++++++ drivers/clk/socfpga/Kconfig | 4 +- drivers/clk/socfpga/Makefile | 2 +- drivers/clk/socfpga/clk-agilex5.c | 843 ++++++++++++++++++ drivers/clk/socfpga/clk-pll-s10.c | 48 + drivers/clk/socfpga/stratix10-clk.h | 2 + include/dt-bindings/clock/agilex5-clock.h | 100 +++ .../dt-bindings/reset/altr,rst-mgr-agilex5.h | 79 ++ 14 files changed, 2325 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/intel,agilex5.yaml create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_swvp.dts create mode 100644 drivers/clk/socfpga/clk-agilex5.c create mode 100644 include/dt-bindings/clock/agilex5-clock.h create mode 100644 include/dt-bindings/reset/altr,rst-mgr-agilex5.h