Message ID | 20230613125852.211636-1-xingyu.wu@starfivetech.com |
---|---|
Headers | show |
Series | Add PLL clocks driver and syscon for StarFive JH7110 SoC | expand |
On Tue, Jun 13, 2023 at 08:58:52PM +0800, Xingyu Wu wrote: > Modify the SYSCRG node to add PLL clocks input from > PLL clocks driver. > > Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Cheers, Conor.
On Tue, Jun 13, 2023 at 08:58:51PM +0800, Xingyu Wu wrote: > From: William Qiu <william.qiu@starfivetech.com> > > Add stg_syscon/sys_syscon/aon_syscon/PLL nodes for JH7110 Soc. > > Co-developed-by: Xingyu Wu <xingyu.wu@starfivetech.com> > Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> > Signed-off-by: William Qiu <william.qiu@starfivetech.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Thanks, Conor.