| Message ID | 20221230153554.105856-1-robert.foss@linaro.org |
|---|---|
| Headers | show |
| Series | Enable Display for SM8350 | expand |
On 30/12/2022 16:35, Robert Foss wrote: > Use two interconnect cells in order to optionally > support a path tag. > > Signed-off-by: Robert Foss <robert.foss@linaro.org> > Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8350.dtsi | 28 ++++++++++++++-------------- > 1 file changed, 14 insertions(+), 14 deletions(-) > I think you need to rebase to include: https://lore.kernel.org/all/167233461761.1099840.5517525898039031248.b4-ty@kernel.org/ On which tree/revision did you base this? Best regards, Krzysztof
On 30/12/2022 16:35, Robert Foss wrote: > The mmxc power-domain-name is not required, and is not > used by either earlier or later SoC versions (sm8250 / sm8450). > > Signed-off-by: Robert Foss <robert.foss@linaro.org> > Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> > --- Please, do not mix fixes, cleanups and new features. This delays applying of fixes for many, many days without a need and causes a lot of duplicated work... This SHOULD be merged long time ago so I won't waste time on such stuff. But because it was always waiting for rest of patches it was never merged... Best regards, Krzysztof
On Fri, 30 Dec 2022 at 17:12, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > > On 30/12/2022 16:35, Robert Foss wrote: > > Use two interconnect cells in order to optionally > > support a path tag. > > > > Signed-off-by: Robert Foss <robert.foss@linaro.org> > > Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> > > --- > > arch/arm64/boot/dts/qcom/sm8350.dtsi | 28 ++++++++++++++-------------- > > 1 file changed, 14 insertions(+), 14 deletions(-) > > > > I think you need to rebase to include: > https://lore.kernel.org/all/167233461761.1099840.5517525898039031248.b4-ty@kernel.org/ Ah, I see. Functionally I seemed to do fine without those commits. > > On which tree/revision did you base this? msm/drm-msm-display-for-6.2 > > Best regards, > Krzysztof >
On 02/01/2023 18:10, Robert Foss wrote: > On Fri, 30 Dec 2022 at 17:12, Krzysztof Kozlowski > <krzysztof.kozlowski@linaro.org> wrote: >> >> On 30/12/2022 16:35, Robert Foss wrote: >>> Use two interconnect cells in order to optionally >>> support a path tag. >>> >>> Signed-off-by: Robert Foss <robert.foss@linaro.org> >>> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> >>> --- >>> arch/arm64/boot/dts/qcom/sm8350.dtsi | 28 ++++++++++++++-------------- >>> 1 file changed, 14 insertions(+), 14 deletions(-) >>> >> >> I think you need to rebase to include: >> https://lore.kernel.org/all/167233461761.1099840.5517525898039031248.b4-ty@kernel.org/ > > Ah, I see. Functionally I seemed to do fine without those commits. > >> >> On which tree/revision did you base this? > > msm/drm-msm-display-for-6.2 Then it is not a proper base for DTS changes - you will miss quite some commits. The DTS patches should be based on Bjorn's SoC tree or linux-next (although the latter sometimes can lead to conflicts). Best regards, Krzysztof
On Tue, 3 Jan 2023 at 08:59, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > > On 02/01/2023 18:10, Robert Foss wrote: > > On Fri, 30 Dec 2022 at 17:12, Krzysztof Kozlowski > > <krzysztof.kozlowski@linaro.org> wrote: > >> > >> On 30/12/2022 16:35, Robert Foss wrote: > >>> Use two interconnect cells in order to optionally > >>> support a path tag. > >>> > >>> Signed-off-by: Robert Foss <robert.foss@linaro.org> > >>> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> > >>> --- > >>> arch/arm64/boot/dts/qcom/sm8350.dtsi | 28 ++++++++++++++-------------- > >>> 1 file changed, 14 insertions(+), 14 deletions(-) > >>> > >> > >> I think you need to rebase to include: > >> https://lore.kernel.org/all/167233461761.1099840.5517525898039031248.b4-ty@kernel.org/ > > > > Ah, I see. Functionally I seemed to do fine without those commits. > > > >> > >> On which tree/revision did you base this? > > > > msm/drm-msm-display-for-6.2 > > Then it is not a proper base for DTS changes - you will miss quite some > commits. The DTS patches should be based on Bjorn's SoC tree or > linux-next (although the latter sometimes can lead to conflicts). Alright, then in that case this series needs to be split into 3 parts. The dts fixes, remaining dts changes & the remainder of code. Is this what you'd like to see? > > > Best regards, > Krzysztof >
On 03/01/2023 10:24, Robert Foss wrote: >>>> On which tree/revision did you base this? >>> >>> msm/drm-msm-display-for-6.2 >> >> Then it is not a proper base for DTS changes - you will miss quite some >> commits. The DTS patches should be based on Bjorn's SoC tree or >> linux-next (although the latter sometimes can lead to conflicts). > > Alright, then in that case this series needs to be split into 3 parts. > > The dts fixes, remaining dts changes & the remainder of code. The split of any fixes (or unrelated cleanups) is good idea anyway. However code can go with DTS - just base on linux-next. If you do not want to base on linux-next then splitting code from DTS is indeed one more good way to send it. > > Is this what you'd like to see? Best regards, Krzysztof
On 30/12/2022 17:35, Robert Foss wrote: > Add compatibles string, "qcom,sm8350-dpu", for the display processing unit > used on Qualcomm SM8350 platform. > > Signed-off-by: Robert Foss <robert.foss@linaro.org> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + > 1 file changed, 1 insertion(+) Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
On Fri, 30 Dec 2022 16:35:43 +0100, Robert Foss wrote: > Dependencies: > https://lore.kernel.org/all/20221102231309.583587-1-dmitry.baryshkov@linaro.org/ > https://lore.kernel.org/all/20221024164225.3236654-1-dmitry.baryshkov@linaro.org/ > https://lore.kernel.org/all/20221104130324.1024242-5-dmitry.baryshkov@linaro.org/ > > Branch: > https://git.linaro.org/people/robert.foss/linux.git/log/?h=sm8350_dsi_v4 > > [...] Applied, thanks! [01/11] dt-bindings: display: msm: Add qcom,sm8350-dpu binding https://gitlab.freedesktop.org/lumag/msm/-/commit/7a0c3d0025de [02/11] dt-bindings: display: msm: Add qcom,sm8350-mdss binding https://gitlab.freedesktop.org/lumag/msm/-/commit/ddcf30003b92 [03/11] drm/msm/dpu: Add SM8350 to hw catalog https://gitlab.freedesktop.org/lumag/msm/-/commit/0a72f23f6ef8 [04/11] drm/msm/dpu: Add support for SM8350 https://gitlab.freedesktop.org/lumag/msm/-/commit/a596a6078586 [05/11] drm/msm: Add support for SM8350 https://gitlab.freedesktop.org/lumag/msm/-/commit/3d6287e64cbd Best regards,
On 12/30/2022 7:35 AM, Robert Foss wrote: > Add GPIO line names as described by the sm8350-hdk schematic. > > Signed-off-by: Robert Foss <robert.foss@linaro.org> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Tested-by: Jessica Zhang <quic_jesszhan@quicinc.com> #SM8350 (HDK) > --- > arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 205 ++++++++++++++++++++++++ > 1 file changed, 205 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts > index 0fcf5bd88fc7..e6deb08c6da0 100644 > --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts > +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts > @@ -233,6 +233,211 @@ &slpi { > > &tlmm { > gpio-reserved-ranges = <52 8>; > + > + gpio-line-names = > + "APPS_I2C_SDA", /* GPIO_0 */ > + "APPS_I2C_SCL", > + "FSA_INT_N", > + "USER_LED3_EN", > + "SMBUS_SDA_1P8", > + "SMBUS_SCL_1P8", > + "2M2_3P3_EN", > + "ALERT_DUAL_M2_N", > + "EXP_UART_CTS", > + "EXP_UART_RFR", > + "EXP_UART_TX", /* GPIO_10 */ > + "EXP_UART_RX", > + "NC", > + "NC", > + "RCM_MARKER1", > + "WSA0_EN", > + "CAM1_RESET_N", > + "CAM0_RESET_N", > + "DEBUG_UART_TX", > + "DEBUG_UART_RX", > + "TS_I2C_SDA", /* GPIO_20 */ > + "TS_I2C_SCL", > + "TS_RESET_N", > + "TS_INT_N", > + "DISP0_RESET_N", > + "DISP1_RESET_N", > + "ETH_RESET", > + "RCM_MARKER2", > + "CAM_DC_MIPI_MUX_EN", > + "CAM_DC_MIPI_MUX_SEL", > + "AFC_PHY_TA_D_PLUS", /* GPIO_30 */ > + "AFC_PHY_TA_D_MINUS", > + "PM8008_1_IRQ", > + "PM8008_1_RESET_N", > + "PM8008_2_IRQ", > + "PM8008_2_RESET_N", > + "CAM_DC_I3C_SDA", > + "CAM_DC_I3C_SCL", > + "FP_INT_N", > + "FP_WUHB_INT_N", > + "SMB_SPMI_DATA", /* GPIO_40 */ > + "SMB_SPMI_CLK", > + "USB_HUB_RESET", > + "FORCE_USB_BOOT", > + "LRF_IRQ", > + "NC", > + "IMU2_INT", > + "HDMI_3P3_EN", > + "HDMI_RSTN", > + "HDMI_1P2_EN", > + "HDMI_INT", /* GPIO_50 */ > + "USB1_ID", > + "FP_SPI_MISO", > + "FP_SPI_MOSI", > + "FP_SPI_CLK", > + "FP_SPI_CS_N", > + "NFC_ESE_SPI_MISO", > + "NFC_ESE_SPI_MOSI", > + "NFC_ESE_SPI_CLK", > + "NFC_ESE_SPI_CS", > + "NFC_I2C_SDA", /* GPIO_60 */ > + "NFC_I2C_SCLC", > + "NFC_EN", > + "NFC_CLK_REQ", > + "HST_WLAN_EN", > + "HST_BT_EN", > + "HST_SW_CTRL", > + "NC", > + "HST_BT_UART_CTS", > + "HST_BT_UART_RFR", > + "HST_BT_UART_TX", /* GPIO_70 */ > + "HST_BT_UART_RX", > + "CAM_DC_SPI0_MISO", > + "CAM_DC_SPI0_MOSI", > + "CAM_DC_SPI0_CLK", > + "CAM_DC_SPI0_CS_N", > + "CAM_DC_SPI1_MISO", > + "CAM_DC_SPI1_MOSI", > + "CAM_DC_SPI1_CLK", > + "CAM_DC_SPI1_CS_N", > + "HALL_INT_N", /* GPIO_80 */ > + "USB_PHY_PS", > + "MDP_VSYNC_P", > + "MDP_VSYNC_S", > + "ETH_3P3_EN", > + "RADAR_INT", > + "NFC_DWL_REQ", > + "SM_GPIO_87", > + "WCD_RESET_N", > + "ALSP_INT_N", > + "PRESS_INT", /* GPIO_90 */ > + "SAR_INT_N", > + "SD_CARD_DET_N", > + "NC", > + "PCIE0_RESET_N", > + "PCIE0_CLK_REQ_N", > + "PCIE0_WAKE_N", > + "PCIE1_RESET_N", > + "PCIE1_CLK_REQ_N", > + "PCIE1_WAKE_N", > + "CAM_MCLK0", /* GPIO_100 */ > + "CAM_MCLK1", > + "CAM_MCLK2", > + "CAM_MCLK3", > + "CAM_MCLK4", > + "CAM_MCLK5", > + "CAM2_RESET_N", > + "CCI_I2C0_SDA", > + "CCI_I2C0_SCL", > + "CCI_I2C1_SDA", > + "CCI_I2C1_SCL", /* GPIO_110 */ > + "CCI_I2C2_SDA", > + "CCI_I2C2_SCL", > + "CCI_I2C3_SDA", > + "CCI_I2C3_SCL", > + "CAM5_RESET_N", > + "CAM4_RESET_N", > + "CAM3_RESET_N", > + "IMU1_INT", > + "MAG_INT_N", > + "MI2S2_I2S_SCK", /* GPIO_120 */ > + "MI2S2_I2S_DAT0", > + "MI2S2_I2S_WS", > + "HIFI_DAC_I2S_MCLK", > + "MI2S2_I2S_DAT1", > + "HIFI_DAC_I2S_SCK", > + "HIFI_DAC_I2S_DAT0", > + "NC", > + "HIFI_DAC_I2S_WS", > + "HST_BT_WLAN_SLIMBUS_CLK", > + "HST_BT_WLAN_SLIMBUS_DAT0", /* GPIO_130 */ > + "BT_LED_EN", > + "WLAN_LED_EN", > + "NC", > + "NC", > + "NC", > + "UIM2_PRESENT", > + "NC", > + "NC", > + "NC", > + "UIM1_PRESENT", /* GPIO_140 */ > + "NC", > + "SM_RFFE0_DATA", > + "NC", > + "SM_RFFE1_DATA", > + "SM_MSS_GRFC4", > + "SM_MSS_GRFC5", > + "SM_MSS_GRFC6", > + "SM_MSS_GRFC7", > + "SM_RFFE4_CLK", > + "SM_RFFE4_DATA", /* GPIO_150 */ > + "WLAN_COEX_UART1_RX", > + "WLAN_COEX_UART1_TX", > + "HST_SW_CTRL", > + "DSI0_STATUS", > + "DSI1_STATUS", > + "APPS_PBL_BOOT_SPEED_1", > + "APPS_BOOT_FROM_ROM", > + "APPS_PBL_BOOT_SPEED_0", > + "QLINK0_REQ", > + "QLINK0_EN", /* GPIO_160 */ > + "QLINK0_WMSS_RESET_N", > + "NC", > + "NC", > + "NC", > + "NC", > + "NC", > + "NC", > + "WCD_SWR_TX_CLK", > + "WCD_SWR_TX_DATA0", > + "WCD_SWR_TX_DATA1", /* GPIO_170 */ > + "WCD_SWR_RX_CLK", > + "WCD_SWR_RX_DATA0", > + "WCD_SWR_RX_DATA1", > + "DMIC01_CLK", > + "DMIC01_DATA", > + "DMIC23_CLK", > + "DMIC23_DATA", > + "WSA_SWR_CLK", > + "WSA_SWR_DATA", > + "DMIC45_CLK", /* GPIO_180 */ > + "DMIC45_DATA", > + "WCD_SWR_TX_DATA2", > + "SENSOR_I3C_SDA", > + "SENSOR_I3C_SCL", > + "CAM_OIS0_I3C_SDA", > + "CAM_OIS0_I3C_SCL", > + "IMU_SPI_MISO", > + "IMU_SPI_MOSI", > + "IMU_SPI_CLK", > + "IMU_SPI_CS_N", /* GPIO_190 */ > + "MAG_I2C_SDA", > + "MAG_I2C_SCL", > + "SENSOR_I2C_SDA", > + "SENSOR_I2C_SCL", > + "RADAR_SPI_MISO", > + "RADAR_SPI_MOSI", > + "RADAR_SPI_CLK", > + "RADAR_SPI_CS_N", > + "HST_BLE_UART_TX", > + "HST_BLE_UART_RX", /* GPIO_200 */ > + "HST_WLAN_UART_TX", > + "HST_WLAN_UART_RX"; > }; > > &uart2 { > -- > 2.34.1 >
On 12/30/2022 7:35 AM, Robert Foss wrote: > The sm8350-hdk ships with the LT9611 UXC DSI/HDMI bridge chip. > > In order to toggle the board to enable the HDMI output, > switch #7 & #8 on the rightmost multi-switch package have > to be toggled to On. > > Signed-off-by: Robert Foss <robert.foss@linaro.org> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Tested-by: Jessica Zhang <quic_jesszhan@quicinc.com> #SM8350 (HDK) > --- > arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 105 ++++++++++++++++++++++++ > 1 file changed, 105 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts > index 1961f941ff83..6b21897c92dc 100644 > --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts > +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts > @@ -20,6 +20,17 @@ chosen { > stdout-path = "serial0:115200n8"; > }; > > + hdmi-connector { > + compatible = "hdmi-connector"; > + type = "a"; > + > + port { > + hdmi_con: endpoint { > + remote-endpoint = <<9611_out>; > + }; > + }; > + }; > + > vph_pwr: vph-pwr-regulator { > compatible = "regulator-fixed"; > regulator-name = "vph_pwr"; > @@ -29,6 +40,31 @@ vph_pwr: vph-pwr-regulator { > regulator-always-on; > regulator-boot-on; > }; > + > + lt9611_1v2: lt9611-1v2-regulator { > + compatible = "regulator-fixed"; > + regulator-name = "LT9611_1V2"; > + > + vin-supply = <&vph_pwr>; > + regulator-min-microvolt = <1200000>; > + regulator-max-microvolt = <1200000>; > + gpio = <&tlmm 49 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + regulator-boot-on; > + }; > + > + lt9611_3v3: lt9611-3v3-regulator { > + compatible = "regulator-fixed"; > + regulator-name = "LT9611_3V3"; > + > + vin-supply = <&vreg_bob>; > + gpio = <&tlmm 47 GPIO_ACTIVE_HIGH>; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + enable-active-high; > + regulator-boot-on; > + regulator-always-on; > + }; > }; > > &adsp { > @@ -220,6 +256,15 @@ &dispcc { > &mdss_dsi0 { > vdda-supply = <&vreg_l6b_1p2>; > status = "okay"; > + > + ports { > + port@1 { > + endpoint { > + remote-endpoint = <<9611_a>; > + data-lanes = <0 1 2 3>; > + }; > + }; > + }; > }; > > &mdss_dsi0_phy { > @@ -231,6 +276,46 @@ &gpi_dma1 { > status = "okay"; > }; > > +&i2c15 { > + clock-frequency = <400000>; > + status = "okay"; > + > + lt9611_codec: hdmi-bridge@2b { > + compatible = "lontium,lt9611uxc"; > + reg = <0x2b>; > + > + interrupts-extended = <&tlmm 50 IRQ_TYPE_EDGE_FALLING>; > + reset-gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>; > + > + vdd-supply = <<9611_1v2>; > + vcc-supply = <<9611_3v3>; > + > + pinctrl-names = "default"; > + pinctrl-0 = <<9611_state>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + > + lt9611_a: endpoint { > + remote-endpoint = <&dsi0_out>; > + }; > + }; > + > + port@2 { > + reg = <2>; > + > + lt9611_out: endpoint { > + remote-endpoint = <&hdmi_con>; > + }; > + }; > + }; > + }; > +}; > + > &mdss { > status = "okay"; > }; > @@ -248,6 +333,10 @@ &qupv3_id_0 { > status = "okay"; > }; > > +&qupv3_id_2 { > + status = "okay"; > +}; > + > &slpi { > status = "okay"; > firmware-name = "qcom/sm8350/slpi.mbn"; > @@ -544,4 +633,20 @@ usb_hub_enabled_state: usb-hub-enabled-state { > drive-strength = <2>; > output-low; > }; > + > + lt9611_state: lt9611-state { > + rst { > + pins = "gpio48"; > + function = "normal"; > + > + output-high; > + input-disable; > + }; > + > + irq { > + pins = "gpio50"; > + function = "gpio"; > + bias-disable; > + }; > + }; > }; > -- > 2.34.1 >
On 12/30/2022 7:35 AM, Robert Foss wrote: > Enable the display subsystem and the dsi0 output for > the sm8350-hdk board. > > Signed-off-by: Robert Foss <robert.foss@linaro.org> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Tested-by: Jessica Zhang <quic_jesszhan@quicinc.com> #SM8350 (HDK) > --- > arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts > index e6deb08c6da0..1961f941ff83 100644 > --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts > +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts > @@ -213,10 +213,32 @@ &cdsp { > firmware-name = "qcom/sm8350/cdsp.mbn"; > }; > > +&dispcc { > + status = "okay"; > +}; > + > +&mdss_dsi0 { > + vdda-supply = <&vreg_l6b_1p2>; > + status = "okay"; > +}; > + > +&mdss_dsi0_phy { > + vdds-supply = <&vreg_l5b_0p88>; > + status = "okay"; > +}; > + > &gpi_dma1 { > status = "okay"; > }; > > +&mdss { > + status = "okay"; > +}; > + > +&mdss_mdp { > + status = "okay"; > +}; > + > &mpss { > status = "okay"; > firmware-name = "qcom/sm8350/modem.mbn"; > -- > 2.34.1 >
On 12/30/2022 7:35 AM, Robert Foss wrote: > Add mdss, mdss_mdp, dsi0, dsi0_phy nodes. With these > nodes the display subsystem is configured to support > one DSI output. > > Signed-off-by: Robert Foss <robert.foss@linaro.org> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Tested-by: Jessica Zhang <quic_jesszhan@quicinc.com> #SM8350 (HDK) > --- > arch/arm64/boot/dts/qcom/sm8350.dtsi | 297 ++++++++++++++++++++++++++- > 1 file changed, 293 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi > index bdefbbb2e38f..a80c0bf6d7fd 100644 > --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi > @@ -3,6 +3,7 @@ > * Copyright (c) 2020, Linaro Limited > */ > > +#include <dt-bindings/interconnect/qcom,sm8350.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/clock/qcom,dispcc-sm8350.h> > #include <dt-bindings/clock/qcom,gcc-sm8350.h> > @@ -2535,14 +2536,302 @@ usb_2_dwc3: usb@a800000 { > }; > }; > > + mdss: display-subsystem@ae00000 { > + compatible = "qcom,sm8350-mdss"; > + reg = <0 0x0ae00000 0 0x1000>; > + reg-names = "mdss"; > + > + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, > + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; > + interconnect-names = "mdp0-mem", "mdp1-mem"; > + > + power-domains = <&dispcc MDSS_GDSC>; > + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; > + > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>, > + <&gcc GCC_DISP_SF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>; > + clock-names = "iface", "bus", "nrt_bus", "core"; > + > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-controller; > + #interrupt-cells = <1>; > + > + iommus = <&apps_smmu 0x820 0x402>; > + > + status = "disabled"; > + > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + dpu_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + /* TODO: opp-200000000 should work with > + * &rpmhpd_opp_low_svs, but one some of > + * sm8350_hdk boards reboot using this > + * opp. > + */ > + opp-200000000 { > + opp-hz = /bits/ 64 <200000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-300000000 { > + opp-hz = /bits/ 64 <300000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-345000000 { > + opp-hz = /bits/ 64 <345000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-460000000 { > + opp-hz = /bits/ 64 <460000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > + > + mdss_mdp: display-controller@ae01000 { > + compatible = "qcom,sm8350-dpu"; > + reg = <0 0x0ae01000 0 0x8f000>, > + <0 0x0aeb0000 0 0x2008>; > + reg-names = "mdp", "vbif"; > + > + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, > + <&gcc GCC_DISP_SF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>, > + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + clock-names = "bus", > + "nrt_bus", > + "iface", > + "lut", > + "core", > + "vsync"; > + > + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + assigned-clock-rates = <19200000>; > + > + operating-points-v2 = <&dpu_opp_table>; > + power-domains = <&rpmhpd SM8350_MMCX>; > + > + interrupt-parent = <&mdss>; > + interrupts = <0>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dpu_intf1_out: endpoint { > + remote-endpoint = <&dsi0_in>; > + }; > + }; > + }; > + }; > + > + mdss_dsi0: dsi@ae94000 { > + compatible = "qcom,mdss-dsi-ctrl"; > + reg = <0 0x0ae94000 0 0x400>; > + reg-names = "dsi_ctrl"; > + > + interrupt-parent = <&mdss>; > + interrupts = <4>; > + > + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, > + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, > + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, > + <&dispcc DISP_CC_MDSS_ESC0_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>; > + clock-names = "byte", > + "byte_intf", > + "pixel", > + "core", > + "iface", > + "bus"; > + > + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, > + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; > + assigned-clock-parents = <&mdss_dsi0_phy 0>, > + <&mdss_dsi0_phy 1>; > + > + operating-points-v2 = <&dsi0_opp_table>; > + power-domains = <&rpmhpd SM8350_MMCX>; > + > + phys = <&mdss_dsi0_phy>; > + > + status = "disabled"; > + > + dsi0_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + /* TODO: opp-187500000 should work with > + * &rpmhpd_opp_low_svs, but one some of > + * sm8350_hdk boards reboot using this > + * opp. > + */ > + opp-187500000 { > + opp-hz = /bits/ 64 <187500000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-300000000 { > + opp-hz = /bits/ 64 <300000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-358000000 { > + opp-hz = /bits/ 64 <358000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + }; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dsi0_in: endpoint { > + remote-endpoint = <&dpu_intf1_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + dsi0_out: endpoint { > + }; > + }; > + }; > + }; > + > + mdss_dsi0_phy: phy@ae94400 { > + compatible = "qcom,dsi-phy-5nm-8350"; > + reg = <0 0x0ae94400 0 0x200>, > + <0 0x0ae94600 0 0x280>, > + <0 0x0ae94900 0 0x260>; > + reg-names = "dsi_phy", > + "dsi_phy_lane", > + "dsi_pll"; > + > + #clock-cells = <1>; > + #phy-cells = <0>; > + > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "iface", "ref"; > + > + status = "disabled"; > + }; > + > + mdss_dsi1: dsi@ae96000 { > + compatible = "qcom,mdss-dsi-ctrl"; > + reg = <0 0x0ae96000 0 0x400>; > + reg-names = "dsi_ctrl"; > + > + interrupt-parent = <&mdss>; > + interrupts = <4>; > + > + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, > + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, > + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, > + <&dispcc DISP_CC_MDSS_ESC1_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>; > + clock-names = "byte", > + "byte_intf", > + "pixel", > + "core", > + "iface", > + "bus"; > + > + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, > + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; > + assigned-clock-parents = <&mdss_dsi1_phy 0>, > + <&mdss_dsi1_phy 1>; > + > + operating-points-v2 = <&dsi1_opp_table>; > + power-domains = <&rpmhpd SM8350_MMCX>; > + > + phys = <&mdss_dsi1_phy>; > + > + status = "disabled"; > + > + dsi1_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + /* TODO: opp-187500000 should work with > + * &rpmhpd_opp_low_svs, but one some of > + * sm8350_hdk boards reboot using this > + * opp. > + */ > + opp-187500000 { > + opp-hz = /bits/ 64 <187500000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-300000000 { > + opp-hz = /bits/ 64 <300000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-358000000 { > + opp-hz = /bits/ 64 <358000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + }; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dsi1_in: endpoint { > + }; > + }; > + > + port@1 { > + reg = <1>; > + dsi1_out: endpoint { > + }; > + }; > + }; > + }; > + > + mdss_dsi1_phy: phy@ae96400 { > + compatible = "qcom,dsi-phy-5nm-8350"; > + reg = <0 0x0ae96400 0 0x200>, > + <0 0x0ae96600 0 0x280>, > + <0 0x0ae96900 0 0x260>; > + reg-names = "dsi_phy", > + "dsi_phy_lane", > + "dsi_pll"; > + > + #clock-cells = <1>; > + #phy-cells = <0>; > + > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "iface", "ref"; > + > + status = "disabled"; > + }; > + }; > + > dispcc: clock-controller@af00000 { > compatible = "qcom,sm8350-dispcc"; > reg = <0 0x0af00000 0 0x10000>; > clocks = <&rpmhcc RPMH_CXO_CLK>, > - <0>, > - <0>, > - <0>, > - <0>, > + <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>, > + <0>, <0>, > <0>, > <0>; > clock-names = "bi_tcxo", > -- > 2.34.1 >