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[00/11] clk: qcom: update MSM8974 clock controller drivers

Message ID 20220928145958.376288-1-dmitry.baryshkov@linaro.org
Headers show
Series clk: qcom: update MSM8974 clock controller drivers | expand

Message

Dmitry Baryshkov Sept. 28, 2022, 2:59 p.m. UTC 
Modernize drivers for global and multimedia clock controllers on the
MSM8974 platform. Switch them to using parent_hws/parent_data, use
clocks through the DT links rather than fetching them from the system
clocks list, update schema and platform DT files.

Dmitry Baryshkov (11):
  dt-bindings: clock: split qcom,gcc-msm8974,-msm8226 to the separate
    file
  dt-bindings: clocks: qcom,mmcc: define clocks/clock-names for MSM8974
  clk: qcom: gcc-msm8974: use ARRAY_SIZE instead of specifying
    num_parents
  clk: qcom: gcc-msm8974: move clock parent tables down
  clk: qcom: gcc-msm8974: use parent_hws/_data instead of parent_names
  clk: qcom: mmcc-msm8974: use ARRAY_SIZE instead of specifying
    num_parents
  clk: qcom: mmcc-msm8974: move clock parent tables down
  clk: qcom: mmcc-msm8974: use parent_hws/_data instead of parent_names
  ARM: dts: qcom: msm8974: add second DSI host and PHY
  ARM: dts: qcom: msm8974: add clocks and clock-names to gcc device
  ARM: dts: qcom: msm8974: add clocks and clock-names to mmcc device

 .../bindings/clock/qcom,gcc-msm8974.yaml      |  65 ++
 .../bindings/clock/qcom,gcc-other.yaml        |   9 +-
 .../devicetree/bindings/clock/qcom,mmcc.yaml  |  38 +
 arch/arm/boot/dts/qcom-msm8974.dtsi           | 106 +++
 drivers/clk/qcom/gcc-msm8974.c                | 682 ++++++++--------
 drivers/clk/qcom/mmcc-msm8974.c               | 736 +++++++++---------
 6 files changed, 932 insertions(+), 704 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-msm8974.yaml

Comments

Neil Armstrong Sept. 28, 2022, 3:22 p.m. UTC | #1 
On 28/09/2022 16:59, Dmitry Baryshkov wrote:
> Move clock parent tables down, after the PLL declrataions, so that we
typo:                                        s/declrataions/declarations/
> can use pll hw clock fields in the next commit.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>   drivers/clk/qcom/gcc-msm8974.c | 98 +++++++++++++++++-----------------
>   1 file changed, 49 insertions(+), 49 deletions(-)

<snip


> +static struct clk_pll gpll4 = {
> +	.l_reg = 0x1dc4,
> +	.m_reg = 0x1dc8,
> +	.n_reg = 0x1dcc,
> +	.config_reg = 0x1dd4,
> +	.mode_reg = 0x1dc0,
> +	.status_reg = 0x1ddc,
> +	.status_bit = 17,
> +	.clkr.hw.init = &(struct clk_init_data){
> +		.name = "gpll4",
> +		.parent_names = (const char *[]){ "xo" },
> +		.num_parents = 1,
> +		.ops = &clk_pll_ops,
> +	},
> +};
> +
> +static struct clk_regmap gpll4_vote = {
> +	.enable_reg = 0x1480,
> +	.enable_mask = BIT(4),
> +	.hw.init = &(struct clk_init_data){
> +		.name = "gpll4_vote",
> +		.parent_names = (const char *[]){ "gpll4" },
> +		.num_parents = 1,
> +		.ops = &clk_pll_vote_ops,
> +	},
> +};
> +

<snip>

>   
> -static struct clk_pll gpll4 = {
> -	.l_reg = 0x1dc4,
> -	.m_reg = 0x1dc8,
> -	.n_reg = 0x1dcc,
> -	.config_reg = 0x1dd4,
> -	.mode_reg = 0x1dc0,
> -	.status_reg = 0x1ddc,
> -	.status_bit = 17,
> -	.clkr.hw.init = &(struct clk_init_data){
> -		.name = "gpll4",
> -		.parent_names = (const char *[]){ "xo" },
> -		.num_parents = 1,
> -		.ops = &clk_pll_ops,
> -	},
> -};
> -
> -static struct clk_regmap gpll4_vote = {
> -	.enable_reg = 0x1480,
> -	.enable_mask = BIT(4),
> -	.hw.init = &(struct clk_init_data){
> -		.name = "gpll4_vote",
> -		.parent_names = (const char *[]){ "gpll4" },
> -		.num_parents = 1,
> -		.ops = &clk_pll_vote_ops,
> -	},
> -};

<snip>

nitpick: you're also moving pll4 up, it's worth adding it to commit message

Neil
Neil Armstrong Sept. 28, 2022, 3:23 p.m. UTC | #2 
On 28/09/2022 16:59, Dmitry Baryshkov wrote:
> Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
> adding/removing entries to/from parent_data easy and errorproof.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>   drivers/clk/qcom/gcc-msm8974.c | 110 ++++++++++++++++-----------------
>   1 file changed, 55 insertions(+), 55 deletions(-)
> 
> diff --git a/drivers/clk/qcom/gcc-msm8974.c b/drivers/clk/qcom/gcc-msm8974.c
> index bf305fa9e522..b847ce852ef8 100644
> --- a/drivers/clk/qcom/gcc-msm8974.c
> +++ b/drivers/clk/qcom/gcc-msm8974.c
> @@ -88,7 +88,7 @@ static struct clk_rcg2 config_noc_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "config_noc_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -100,7 +100,7 @@ static struct clk_rcg2 periph_noc_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "periph_noc_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -112,7 +112,7 @@ static struct clk_rcg2 system_noc_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "system_noc_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -185,7 +185,7 @@ static struct clk_rcg2 usb30_master_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "usb30_master_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -205,7 +205,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "blsp1_qup1_i2c_apps_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -230,7 +230,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "blsp1_qup1_spi_apps_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -243,7 +243,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "blsp1_qup2_i2c_apps_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -257,7 +257,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "blsp1_qup2_spi_apps_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -270,7 +270,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "blsp1_qup3_i2c_apps_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -284,7 +284,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "blsp1_qup3_spi_apps_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -297,7 +297,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "blsp1_qup4_i2c_apps_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -311,7 +311,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "blsp1_qup4_spi_apps_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -324,7 +324,7 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "blsp1_qup5_i2c_apps_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -338,7 +338,7 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "blsp1_qup5_spi_apps_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -351,7 +351,7 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "blsp1_qup6_i2c_apps_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -365,7 +365,7 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "blsp1_qup6_spi_apps_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -398,7 +398,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "blsp1_uart1_apps_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -412,7 +412,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "blsp1_uart2_apps_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -426,7 +426,7 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "blsp1_uart3_apps_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -440,7 +440,7 @@ static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "blsp1_uart4_apps_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -454,7 +454,7 @@ static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "blsp1_uart5_apps_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -468,7 +468,7 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "blsp1_uart6_apps_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -481,7 +481,7 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "blsp2_qup1_i2c_apps_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -495,7 +495,7 @@ static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "blsp2_qup1_spi_apps_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -508,7 +508,7 @@ static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "blsp2_qup2_i2c_apps_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -522,7 +522,7 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "blsp2_qup2_spi_apps_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -535,7 +535,7 @@ static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "blsp2_qup3_i2c_apps_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -549,7 +549,7 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "blsp2_qup3_spi_apps_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -562,7 +562,7 @@ static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "blsp2_qup4_i2c_apps_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -576,7 +576,7 @@ static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "blsp2_qup4_spi_apps_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -589,7 +589,7 @@ static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "blsp2_qup5_i2c_apps_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -603,7 +603,7 @@ static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "blsp2_qup5_spi_apps_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -616,7 +616,7 @@ static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "blsp2_qup6_i2c_apps_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -630,7 +630,7 @@ static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "blsp2_qup6_spi_apps_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -644,7 +644,7 @@ static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "blsp2_uart1_apps_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -658,7 +658,7 @@ static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "blsp2_uart2_apps_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -672,7 +672,7 @@ static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "blsp2_uart3_apps_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -686,7 +686,7 @@ static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "blsp2_uart4_apps_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -700,7 +700,7 @@ static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "blsp2_uart5_apps_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -714,7 +714,7 @@ static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "blsp2_uart6_apps_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -741,7 +741,7 @@ static struct clk_rcg2 ce1_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "ce1_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -762,7 +762,7 @@ static struct clk_rcg2 ce2_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "ce2_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -794,7 +794,7 @@ static struct clk_rcg2 gp1_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "gp1_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -808,7 +808,7 @@ static struct clk_rcg2 gp2_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "gp2_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -822,7 +822,7 @@ static struct clk_rcg2 gp3_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "gp3_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -840,7 +840,7 @@ static struct clk_rcg2 pdm2_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "pdm2_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -872,7 +872,7 @@ static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_pro[] = {
>   static struct clk_init_data sdcc1_apps_clk_src_init = {
>   	.name = "sdcc1_apps_clk_src",
>   	.parent_names = gcc_xo_gpll0,
> -	.num_parents = 2,
> +	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   	.ops = &clk_rcg2_floor_ops,
>   };
>   
> @@ -894,7 +894,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "sdcc2_apps_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_floor_ops,
>   	},
>   };
> @@ -908,7 +908,7 @@ static struct clk_rcg2 sdcc3_apps_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "sdcc3_apps_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_floor_ops,
>   	},
>   };
> @@ -922,7 +922,7 @@ static struct clk_rcg2 sdcc4_apps_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "sdcc4_apps_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_floor_ops,
>   	},
>   };
> @@ -941,7 +941,7 @@ static struct clk_rcg2 tsif_ref_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "tsif_ref_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -959,7 +959,7 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "usb30_mock_utmi_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -978,7 +978,7 @@ static struct clk_rcg2 usb_hs_system_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "usb_hs_system_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -1022,7 +1022,7 @@ static struct clk_rcg2 usb_hsic_io_cal_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "usb_hsic_io_cal_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 1,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };
> @@ -1041,7 +1041,7 @@ static struct clk_rcg2 usb_hsic_system_clk_src = {
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "usb_hsic_system_clk_src",
>   		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>   		.ops = &clk_rcg2_ops,
>   	},
>   };

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Neil Armstrong Sept. 28, 2022, 3:25 p.m. UTC | #3 
On 28/09/2022 16:59, Dmitry Baryshkov wrote:
> Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
> adding/removing entries to/from parent_data easy and errorproof.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>   drivers/clk/qcom/mmcc-msm8974.c | 74 ++++++++++++++++-----------------
>   1 file changed, 37 insertions(+), 37 deletions(-)
> 

<snip>

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Neil Armstrong Sept. 28, 2022, 3:26 p.m. UTC | #4 
On 28/09/2022 16:59, Dmitry Baryshkov wrote:
> Move clock parent tables down, after the PLL declrataions, so that we
Typo:                                        s/declrataions/declarations/
> can use pll hw clock fields in the next commit.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>   drivers/clk/qcom/mmcc-msm8974.c | 170 ++++++++++++++++----------------
>   1 file changed, 85 insertions(+), 85 deletions(-)
> 

<snip>

Otherwise looks good, with typo fixed:
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Krzysztof Kozlowski Sept. 28, 2022, 5:12 p.m. UTC | #5 
On 28/09/2022 16:59, Dmitry Baryshkov wrote:
> Add second DSI host and PHY available on the msm8974 platform.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  arch/arm/boot/dts/qcom-msm8974.dtsi | 78 +++++++++++++++++++++++++++++
>  1 file changed, 78 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
> index 7a9be0acf3f5..810a163ca14f 100644
> --- a/arch/arm/boot/dts/qcom-msm8974.dtsi
> +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
> @@ -1541,6 +1541,13 @@ mdp5_intf1_out: endpoint {
>  							remote-endpoint = <&dsi0_in>;
>  						};
>  					};
> +
> +					port@1 {
> +						reg = <1>;
> +						mdp5_intf2_out: endpoint {
> +							remote-endpoint = <&dsi1_in>;
> +						};
> +					};
>  				};
>  			};
>  
> @@ -1614,6 +1621,77 @@ dsi0_phy: dsi-phy@fd922a00 {
>  
>  				status = "disabled";
>  			};
> +
> +			dsi1: dsi@fd922e00 {
> +				compatible = "qcom,mdss-dsi-ctrl";
> +				reg = <0xfd922e00 0x1f8>;
> +				reg-names = "dsi_ctrl";
> +
> +				interrupt-parent = <&mdss>;
> +				interrupts = <4>;
> +
> +				assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
> +				assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
> +
> +				clocks = <&mmcc MDSS_MDP_CLK>,
> +					 <&mmcc MDSS_AHB_CLK>,
> +					 <&mmcc MDSS_AXI_CLK>,
> +					 <&mmcc MDSS_BYTE1_CLK>,
> +					 <&mmcc MDSS_PCLK1_CLK>,
> +					 <&mmcc MDSS_ESC1_CLK>,
> +					 <&mmcc MMSS_MISC_AHB_CLK>;
> +				clock-names = "mdp_core",
> +					      "iface",
> +					      "bus",
> +					      "byte",
> +					      "pixel",
> +					      "core",
> +					      "core_mmss";
> +
> +				phys = <&dsi1_phy>;
> +				phy-names = "dsi-phy";

I think this is being removed, isn't it?

> +
> +				status = "disabled";
> +
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				ports {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +
> +					port@0 {
> +						reg = <0>;
> +						dsi1_in: endpoint {
> +							remote-endpoint = <&mdp5_intf2_out>;
> +						};
> +					};
> +
> +					port@1 {
> +						reg = <1>;
> +						dsi1_out: endpoint {
> +						};
> +					};
> +				};
> +			};
> +
> +			dsi1_phy: dsi-phy@fd923000 {

And this you change into "phy"?


Best regards,
Krzysztof
Stephen Boyd Sept. 28, 2022, 8:53 p.m. UTC | #6 
Quoting Neil Armstrong (2022-09-28 08:23:14)
> On 28/09/2022 16:59, Dmitry Baryshkov wrote:
> > Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
> > adding/removing entries to/from parent_data easy and errorproof.
> > 
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> 
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>

Please trim replies so I don't have to scroll down to the bottom to find
out a single tag was added.