[v5,00/10] drivers/perf: CPU PMU driver for Apple M1

The M1 SoC embeds a per-CPU PMU that has a very different programming
interface compared to the architected PMUv3 that is normally present
on standard implementations.

This small series adds a driver for this HW by leveraging the arm_pmu
infrastructure, resulting in a rather simple driver.

Of course, we know next to nothing about the actual events this PMU
counts, aside from CPU cycles and instructions. Everything else is
undocumented (though as Dougall pointed out, someone could extract the
relevant information from a macOS install if they wanted -- I don't).
I'm looking at allowing the perf userspace tool to load the event
descriptions at runtime, which would probably help.

* From v4 [4]:
  - More DT binding tweaks
  - Collected RB from Rob
  - Rebased on 5.17-rc3

* From v3 [3]:
  - DT binding fixes
  - Typo fixes (and probably more added)
  - Rebased on 5.17-rc1

* From v2 [2]:
  - Reworked the way the FIQ virtual affinity is exposed (now coming
    from the DT instead of being internal to the irqchip driver)
  - Dropped the locking from the PMU driver after Mark's review
  - Required the exclude_guest flag to be set, as the PMU doesn't seem
    to be able to count guest events, at least by default
  - Dropped the counter-stop on interrupt and instead stop the whole
    PMU on interrupt
  - Dropped the kernel taint, as I couldn't find a good way to do that
    on first use
  - Collected RBs from Hector

* From v1 [1]:
  - Added a few comments clarifying the event mapping to counters
  - Spelling fixes
  - Collected Acks from Rob

[1] https://lore.kernel.org/r/20211113115429.4027571-1-maz@kernel.org
[2] https://lore.kernel.org/r/20211201134909.390490-1-maz@kernel.org
[3] https://lore.kernel.org/r/20211214182634.727330-1-maz@kernel.org
[4] https://lore.kernel.org/r/20220124201231.298961-1-maz@kernel.org

Marc Zyngier (10):
  dt-bindings: arm-pmu: Document Apple PMU compatible strings
  dt-bindings: apple,aic: Add CPU PMU per-cpu pseudo-interrupts
  dt-bindings: apple,aic: Add affinity description for per-cpu
    pseudo-interrupts
  irqchip/apple-aic: Parse FIQ affinities from device-tree
  irqchip/apple-aic: Wire PMU interrupts
  arm64: dts: apple: Add t8103 PMU interrupt affinities
  arm64: dts: apple: Add t8303 PMU nodes
  irqchip/apple-aic: Move PMU-specific registers to their own include
    file
  drivers/perf: arm_pmu: Handle 47 bit counters
  drivers/perf: Add Apple icestorm/firestorm CPU PMU driver

 .../devicetree/bindings/arm/pmu.yaml          |   2 +
 .../interrupt-controller/apple,aic.yaml       |  31 +
 arch/arm64/boot/dts/apple/t8103.dtsi          |  24 +
 arch/arm64/include/asm/apple_m1_pmu.h         |  64 ++
 drivers/irqchip/irq-apple-aic.c               |  94 ++-
 drivers/perf/Kconfig                          |   7 +
 drivers/perf/Makefile                         |   1 +
 drivers/perf/apple_m1_cpu_pmu.c               | 584 ++++++++++++++++++
 drivers/perf/arm_pmu.c                        |   2 +
 .../interrupt-controller/apple-aic.h          |   2 +
 include/linux/perf/arm_pmu.h                  |   2 +
 11 files changed, 791 insertions(+), 22 deletions(-)
 create mode 100644 arch/arm64/include/asm/apple_m1_pmu.h
 create mode 100644 drivers/perf/apple_m1_cpu_pmu.c

On Tue, 08 Feb 2022 18:55:54 +0000,
Marc Zyngier <maz@kernel.org> wrote:
> 
> The M1 SoC embeds a per-CPU PMU that has a very different programming
> interface compared to the architected PMUv3 that is normally present
> on standard implementations.
> 
> This small series adds a driver for this HW by leveraging the arm_pmu
> infrastructure, resulting in a rather simple driver.
> 
> Of course, we know next to nothing about the actual events this PMU
> counts, aside from CPU cycles and instructions. Everything else is
> undocumented (though as Dougall pointed out, someone could extract the
> relevant information from a macOS install if they wanted -- I don't).
> I'm looking at allowing the perf userspace tool to load the event
> descriptions at runtime, which would probably help.

[...]

FWIW, I have created two branches:

- [1] has the full series
- [2] has the irqchip/DT prefix of [1]

Both branches are stable, and I expect [2] to be used as a shared
branch between the irqchip and perf trees.

Thanks,

	M.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git/log/?h=hack/m1-pmu
[2] https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git/log/?h=irq/aic-pmu

On Mon, Mar 07, 2022 at 03:55:44PM +0000, Marc Zyngier wrote:
> On Tue, 08 Feb 2022 18:55:54 +0000,
> Marc Zyngier <maz@kernel.org> wrote:
> > 
> > The M1 SoC embeds a per-CPU PMU that has a very different programming
> > interface compared to the architected PMUv3 that is normally present
> > on standard implementations.
> > 
> > This small series adds a driver for this HW by leveraging the arm_pmu
> > infrastructure, resulting in a rather simple driver.
> > 
> > Of course, we know next to nothing about the actual events this PMU
> > counts, aside from CPU cycles and instructions. Everything else is
> > undocumented (though as Dougall pointed out, someone could extract the
> > relevant information from a macOS install if they wanted -- I don't).
> > I'm looking at allowing the perf userspace tool to load the event
> > descriptions at runtime, which would probably help.
> 
> [...]
> 
> FWIW, I have created two branches:
> 
> - [1] has the full series
> - [2] has the irqchip/DT prefix of [1]
> 
> Both branches are stable, and I expect [2] to be used as a shared
> branch between the irqchip and perf trees.

Cheers, I've picked this up in the arm64 tree (by pulling [2] and applying
the two extra patches from [1] on top) here:

https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git/log/?h=for-next/perf-m1

Will