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[v2,0/7] Add missing peripherals to Allwinner V3s/V3 device trees

Message ID 20210513233024.2076725-1-t.schramm@manjaro.org
Headers show
Series Add missing peripherals to Allwinner V3s/V3 device trees | expand

Message

Tobias Schramm May 13, 2021, 11:30 p.m. UTC
The Allwinner V3s/V3 SoCs feature quite a few peripherals that have good
driver support but yet are nowhere to be found in the SoCs dts.
This patchset adds the DMA controller, the relevant DMA properties for all
peripherals supporting DMA, the integrated analog codec and - for the
Allwinner V3 SoC - also the I2S interface.
I've included all of those changes in one patchset since they do all
depend on addition of the DMA controller.
All changes have been tested in a recent project of mine using a Sochip S3
(a rebranded Allwinner V3) and are confirmed working.

This is v2 of this patchset.

Cheers,
Tobias

Changelog:
  v2:
    - add v3/v3s specific compatible strings
    - fix v3s audio codec analog frontend compatible
    - fix an I2S -> I2C typo

Tobias Schramm (7):
  ARM: dts: sun8i: v3s: add DMA controller to v3s dts
  ARM: dts: sun8i: v3s: add DMA properties to peripherals supporting DMA
  ARM: dts: sun8i: v3s: add analog codec and frontend to v3s dts
  ASoC: dt-bindings: sun8i-a23-codec-analog: add compatible for
    Allwinner V3
  ARM: dts: sun8i: V3: add codec analog frontend to V3 dts
  dt-bindings: sound: sun4i-i2s: add Allwinner V3 I2S compatible
  ARM: dts: sun8i: V3: add I2S interface to V3 dts

 .../sound/allwinner,sun4i-a10-i2s.yaml        |  3 ++
 .../allwinner,sun8i-a23-codec-analog.yaml     |  9 +++--
 arch/arm/boot/dts/sun8i-v3.dtsi               | 31 +++++++++++++++
 arch/arm/boot/dts/sun8i-v3s.dtsi              | 39 +++++++++++++++++++
 4 files changed, 79 insertions(+), 3 deletions(-)

Comments

Andre Przywara May 14, 2021, 7:07 a.m. UTC | #1
On Fri, 14 May 2021 01:30:18 +0200
Tobias Schramm <t.schramm@manjaro.org> wrote:

> The Allwinner V3s and V3 feature a DMA controller.
> This commit adds it to the V3s dtsi.
> 
> Signed-off-by: Tobias Schramm <t.schramm@manjaro.org>

Address, interrupt and clocks/reset match the manual.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Cheers,
Andre

> ---
>  arch/arm/boot/dts/sun8i-v3s.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
> index eb4cb63fef13..f0296ab46137 100644
> --- a/arch/arm/boot/dts/sun8i-v3s.dtsi
> +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
> @@ -1,5 +1,6 @@
>  /*
>   * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
> + * Copyright (C) 2021 Tobias Schramm <t.schramm@manjaro.org>
>   *
>   * This file is dual-licensed: you can use it either under the terms
>   * of the GPL or the X11 license, at your option. Note that this dual
> @@ -172,6 +173,15 @@ nmi_intc: interrupt-controller@1c000d0 {
>  			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
>  		};
>  
> +		dma: dma-controller@1c02000 {
> +			compatible = "allwinner,sun8i-v3s-dma";
> +			reg = <0x01c02000 0x1000>;
> +			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_DMA>;
> +			resets = <&ccu RST_BUS_DMA>;
> +			#dma-cells = <1>;
> +		};
> +
>  		tcon0: lcd-controller@1c0c000 {
>  			compatible = "allwinner,sun8i-v3s-tcon";
>  			reg = <0x01c0c000 0x1000>;
Andre Przywara May 14, 2021, 7:07 a.m. UTC | #2
On Fri, 14 May 2021 01:30:19 +0200
Tobias Schramm <t.schramm@manjaro.org> wrote:

> This commit adds DMA properties to all peripherals supporting DMA on the
> Allwinner V3s, enabling accelerated data transfer to them.
> 
> Signed-off-by: Tobias Schramm <t.schramm@manjaro.org>

DMA channels match the manual.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Cheers,
Andre

> ---
>  arch/arm/boot/dts/sun8i-v3s.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
> index f0296ab46137..3eaa8703e2ac 100644
> --- a/arch/arm/boot/dts/sun8i-v3s.dtsi
> +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
> @@ -285,6 +285,8 @@ crypto@1c15000 {
>  			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>  			clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
>  			clock-names = "ahb", "mod";
> +			dmas = <&dma 16>, <&dma 16>;
> +			dma-names = "rx", "tx";
>  			resets = <&ccu RST_BUS_CE>;
>  			reset-names = "ahb";
>  		};
> @@ -446,6 +448,8 @@ uart0: serial@1c28000 {
>  			reg-shift = <2>;
>  			reg-io-width = <4>;
>  			clocks = <&ccu CLK_BUS_UART0>;
> +			dmas = <&dma 6>, <&dma 6>;
> +			dma-names = "rx", "tx";
>  			resets = <&ccu RST_BUS_UART0>;
>  			status = "disabled";
>  		};
> @@ -457,6 +461,8 @@ uart1: serial@1c28400 {
>  			reg-shift = <2>;
>  			reg-io-width = <4>;
>  			clocks = <&ccu CLK_BUS_UART1>;
> +			dmas = <&dma 7>, <&dma 7>;
> +			dma-names = "rx", "tx";
>  			resets = <&ccu RST_BUS_UART1>;
>  			status = "disabled";
>  		};
> @@ -468,6 +474,8 @@ uart2: serial@1c28800 {
>  			reg-shift = <2>;
>  			reg-io-width = <4>;
>  			clocks = <&ccu CLK_BUS_UART2>;
> +			dmas = <&dma 8>, <&dma 8>;
> +			dma-names = "rx", "tx";
>  			resets = <&ccu RST_BUS_UART2>;
>  			pinctrl-0 = <&uart2_pins>;
>  			pinctrl-names = "default";
> @@ -547,6 +555,8 @@ spi0: spi@1c68000 {
>  			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
>  			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
>  			clock-names = "ahb", "mod";
> +			dmas = <&dma 23>, <&dma 23>;
> +			dma-names = "rx", "tx";
>  			pinctrl-names = "default";
>  			pinctrl-0 = <&spi0_pins>;
>  			resets = <&ccu RST_BUS_SPI0>;