[v3,0/5] Add APCS support for SDX55

Hello,

This series adds APCS mailbox and clock support for SDX55. The APCS IP
in SDX55 provides IPC and clock functionalities. Hence, mailbox support
is added to the "qcom-apcs-ipc-mailbox" driver and a dedicated clock
driver "apcs-sdx55" is added.

Also, the clock to the APCS block is coming from 3 different sources:

1. Board XO
2. Fixed rate GPLL0
3. A7 PLL

First source is from crystal osc, second is from GCC and third one is a
separate clock source. Hence, a dedicated clk driver is added for the A7
PLL as well.

Apart from the mailbox support, another intention of this series is to add
the CPUFreq support to SDX55 platform. Since there is no dedicated hardware
IP in SDX55 to do CPUFreq duties, this platform makes use of the clock and
regulators directly via cpufreq-dt driver.

The trick here is attaching the power domain to cpudev. Usually the power
domains for the target device is attached in the bus driver or in the
dedicated device drivers. But in this case, there is no dedicated CPUFreq
driver nor a bus driver. After discussing with Viresh, I concluded that
A7 PLL driver might be the best place to do this!

But this decision is subject to discussion, hence added Ulf and Viresh to
this series.

Thanks,
Mani

Changes in v3:

* Incorporated review comments from Stephen for APCS clk driver and Rob for
  APCS DT binding

Changes in v2:

* Modified the max_register value as per the SDX55 IPC offset in mailbox
  driver.

Manivannan Sadhasivam (5):
  dt-bindings: mailbox: Add binding for SDX55 APCS
  mailbox: qcom: Add support for SDX55 APCS IPC
  dt-bindings: clock: Add Qualcomm A7 PLL binding
  clk: qcom: Add A7 PLL support
  clk: qcom: Add SDX55 APCS clock controller support

 .../devicetree/bindings/clock/qcom,a7pll.yaml |  51 ++++++
 .../mailbox/qcom,apcs-kpss-global.yaml        |  33 ++++
 drivers/clk/qcom/Kconfig                      |  17 ++
 drivers/clk/qcom/Makefile                     |   2 +
 drivers/clk/qcom/a7-pll.c                     | 100 ++++++++++++
 drivers/clk/qcom/apcs-sdx55.c                 | 149 ++++++++++++++++++
 drivers/mailbox/qcom-apcs-ipc-mailbox.c       |   7 +-
 7 files changed, 358 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,a7pll.yaml
 create mode 100644 drivers/clk/qcom/a7-pll.c
 create mode 100644 drivers/clk/qcom/apcs-sdx55.c

Quoting Manivannan Sadhasivam (2021-01-17 20:11:51)
> Changes in v2:
> 
> * Modified the max_register value as per the SDX55 IPC offset in mailbox
>   driver.
> 
> Manivannan Sadhasivam (5):
>   dt-bindings: mailbox: Add binding for SDX55 APCS
>   mailbox: qcom: Add support for SDX55 APCS IPC

I think I can apply the clk patches to clk tree without the mailbox
patches, right?

>   dt-bindings: clock: Add Qualcomm A7 PLL binding
>   clk: qcom: Add A7 PLL support
>   clk: qcom: Add SDX55 APCS clock controller support
>

Quoting Manivannan Sadhasivam (2021-01-17 20:11:55)
> Add support for PLL found in Qualcomm SDX55 platforms which is used to
> provide clock to the Cortex A7 CPU via a mux. This PLL can provide high
> frequency clock to the CPU above 1GHz as compared to the other sources
> like GPLL0.
> 
> In this driver, the power domain is attached to the cpudev. This is
> required for CPUFreq functionality and there seems to be no better place
> to do other than this driver (no dedicated CPUFreq driver).
> 
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---

Applied to clk-next

Quoting Manivannan Sadhasivam (2021-01-17 20:11:56)
> Add a driver for the SDX55 APCS clock controller. It is part of the APCS
> hardware block, which among other things implements also a combined mux
> and half integer divider functionality. The APCS clock controller has 3
> parent clocks:
> 
> 1. Board XO
> 2. Fixed rate GPLL0
> 3. A7 PLL
> 
> This is required for enabling CPU frequency scaling on SDX55-based
> platforms.
> 
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---

Applied to clk-next

On Mon, Feb 08, 2021 at 09:46:11AM -0800, Stephen Boyd wrote:
> Quoting Manivannan Sadhasivam (2021-01-17 20:11:51)
> > Changes in v2:
> > 
> > * Modified the max_register value as per the SDX55 IPC offset in mailbox
> >   driver.
> > 
> > Manivannan Sadhasivam (5):
> >   dt-bindings: mailbox: Add binding for SDX55 APCS
> >   mailbox: qcom: Add support for SDX55 APCS IPC
> 
> I think I can apply the clk patches to clk tree without the mailbox
> patches, right?
> 

Yes, you can. Thanks for applying!

Jassi: Can you please look into the mailbox patches?

Regards,
Mani

> >   dt-bindings: clock: Add Qualcomm A7 PLL binding
> >   clk: qcom: Add A7 PLL support
> >   clk: qcom: Add SDX55 APCS clock controller support
> >

On Mon, Feb 8, 2021 at 12:20 PM Manivannan Sadhasivam
<manivannan.sadhasivam@linaro.org> wrote:
>
> On Mon, Feb 08, 2021 at 09:46:11AM -0800, Stephen Boyd wrote:
> > Quoting Manivannan Sadhasivam (2021-01-17 20:11:51)
> > > Changes in v2:
> > >
> > > * Modified the max_register value as per the SDX55 IPC offset in mailbox
> > >   driver.
> > >
> > > Manivannan Sadhasivam (5):
> > >   dt-bindings: mailbox: Add binding for SDX55 APCS
> > >   mailbox: qcom: Add support for SDX55 APCS IPC
> >
> > I think I can apply the clk patches to clk tree without the mailbox
> > patches, right?
> >
>
> Yes, you can. Thanks for applying!
>
> Jassi: Can you please look into the mailbox patches?
>
They are compatible strings mostly... so assume it ok.

cheers!