[v5,00/16] dmaengine: dw-axi-dmac: support Intel KeemBay AxiDMA

The below patch series are to support AxiDMA running on Intel KeemBay SoC.
The base driver is dw-axi-dmac. This driver only support DMA memory copy
transfers. Code refactoring is needed so that additional features can be
supported.
The features added in this patch series are:
- Replacing Linked List with virtual descriptor management.
- Remove unrelated hw desc stuff from dma memory pool.
- Manage dma memory pool alloc/destroy based on channel activity.
- Support dmaengine device_sync() callback.
- Support dmaengine device_config().
- Support dmaengine device_prep_slave_sg().
- Support dmaengine device_prep_dma_cyclic().
- Support of_dma_controller_register().
- Support burst residue granularity.
- Support Intel KeemBay AxiDMA registers.
- Support Intel KeemBay AxiDMA device handshake.
- Support Intel KeemBay AxiDMA BYTE and HALFWORD device operation.
- Add constraint to Max segment size.
- Virtually split the linked-list

This patch series are tested on Intel KeemBay platform.

v5:
- Added comment to the Apb registers used by Intel KeemBay Soc.
- Renamed "hs_num" to "handshake_num".
- Conditional check for the compatible property and return error
  instead of printing warning.
- Added patch 16th to virtually split the linked-list as per
  request from ALSA team. 

v4:
- Fixed bot found errors running make_dt_binding_check.
- Added minItems: 1 to the YAML schemas DT binding.
- Updated "reg" field to the YAML schemas DT binding.

v3:
- Added additionalProperties: false to the YAML schemas DT binding.
- Reordered patch sequence for patch 10th, 11th and 12th so that
  DT binding come first, follow by adding Intel KeemBay SoC registers
  and update .compatible field.
- Checked txstate NULL condition.
- Created helper function dw_axi_dma_set_hw_desc() to handle common code.

v2:
- Rebased to v5.10-rc1 kernel.
- Added support for dmaengine device_config().
- Added support for dmaengine device_prep_slave_sg().
- Added support for dmaengine device_prep_dma_cyclic().
- Added support for of_dma_controller_register().
- Added support for burst residue granularity.
- Added support for Intel KeemBay AxiDMA registers.
- Added support for Intel KeemBay AxiDMA device handshake.
- Added support for Intel KeemBay AxiDMA BYTE and HALFWORD device operation.
- Added constraint to Max segment size.

v1:
- Initial version. Patch on top of dw-axi-dma driver. This version improve
  the descriptor management by replacing Linked List Item (LLI) with
  virtual descriptor management, only allocate hardware LLI memories from
  DMA memory pool, manage DMA memory pool alloc/destroy based on channel
  activity and to support device_sync callback.

Sia Jee Heng (16):
  dt-bindings: dma: Add YAML schemas for dw-axi-dmac
  dmaengine: dw-axi-dmac: simplify descriptor management
  dmaengine: dw-axi-dmac: move dma_pool_create() to
    alloc_chan_resources()
  dmaengine: dw-axi-dmac: Add device_synchronize() callback
  dmaengine: dw-axi-dmac: Add device_config operation
  dmaengine: dw-axi-dmac: Support device_prep_slave_sg
  dmaegine: dw-axi-dmac: Support device_prep_dma_cyclic()
  dmaengine: dw-axi-dmac: Support of_dma_controller_register()
  dmaengine: dw-axi-dmac: Support burst residue granularity
  dt-binding: dma: dw-axi-dmac: Add support for Intel KeemBay AxiDMA
  dmaengine: dw-axi-dmac: Add Intel KeemBay DMA register fields
  dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA support
  dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA handshake
  dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA BYTE and HALFWORD
    registers
  dmaengine: dw-axi-dmac: Set constraint to the Max segment size
  dmaengine: dw-axi-dmac: Virtually split the linked-list

 .../bindings/dma/snps,dw-axi-dmac.txt         |  39 -
 .../bindings/dma/snps,dw-axi-dmac.yaml        | 153 ++++
 .../dma/dw-axi-dmac/dw-axi-dmac-platform.c    | 710 +++++++++++++++---
 drivers/dma/dw-axi-dmac/dw-axi-dmac.h         |  34 +-
 4 files changed, 802 insertions(+), 134 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
 create mode 100644 Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml


base-commit: 4d02da974ea85a62074efedf354e82778f910d82

On Mon, Nov 23, 2020 at 10:34:52AM +0800, Sia Jee Heng wrote:
> AxiDMA driver exposed the dma_set_max_seg_size() to the DMAENGINE.
> It shall helps the DMA clients to create size-optimized linked-list
> for the controller.
> 
> However, there are certain situations where DMA client might not be
> abled to benefit from the dma_get_max_seg_size() if the segment size
> can't meet the nature of the DMA client's operation.
> 
> In the case of ALSA operation, ALSA application and driver expecting
> to run in a period of larger than 10ms regardless of the bit depth.
> With this large period, there is a strong request to split the linked-list
> in the AxiDMA driver.

I'm wondering why ASoC generic code can't use DMA channel and device
capabilities and prepare SG list with all limitations taken into account.

> -----Original Message-----
> From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Sent: 23 November 2020 6:23 PM
> To: Sia, Jee Heng <jee.heng.sia@intel.com>
> Cc: vkoul@kernel.org; Eugeniy.Paltsev@synopsys.com;
> robh+dt@kernel.org; dmaengine@vger.kernel.org; linux-
> kernel@vger.kernel.org; devicetree@vger.kernel.org
> Subject: Re: [PATCH v5 16/16] dmaengine: dw-axi-dmac: Virtually split
> the linked-list
> 
> On Mon, Nov 23, 2020 at 10:34:52AM +0800, Sia Jee Heng wrote:
> > AxiDMA driver exposed the dma_set_max_seg_size() to the
> DMAENGINE.
> > It shall helps the DMA clients to create size-optimized linked-list
> > for the controller.
> >
> > However, there are certain situations where DMA client might not be
> > abled to benefit from the dma_get_max_seg_size() if the segment
> size
> > can't meet the nature of the DMA client's operation.
> >
> > In the case of ALSA operation, ALSA application and driver expecting
> > to run in a period of larger than 10ms regardless of the bit depth.
> > With this large period, there is a strong request to split the
> > linked-list in the AxiDMA driver.
> 
> I'm wondering why ASoC generic code can't use DMA channel and
> device capabilities and prepare SG list with all limitations taken into
> account.
[>>] There is no further comment to split the linked-list in DMA, I assume we can proceed with this patch.
[>>] The RFC patch is submitted at below link and you are in the thread.
[>>] https://lore.kernel.org/alsa-devel/CO1PR11MB5026545F07968DBC5386CF45DACD0@CO1PR11MB5026.namprd11.prod.outlook.com/T/#u

> 
> 
> --
> With Best Regards,
> Andy Shevchenko
>