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[v2,0/7] J7200: Add PCIe DT nodes to Enable PCIe

Message ID 20201109170409.4498-1-kishon@ti.com
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Series J7200: Add PCIe DT nodes to Enable PCIe | expand

Message

Kishon Vijay Abraham I Nov. 9, 2020, 5:04 p.m. UTC 
Add DT binding documentation and device tree nodes to enable
PCIe in J7200.

Changes from v1:
*) Renamed "pcie-ctrl" to "syscon" DT node and expanded "syscon" DT
   sub-node
*) Fixed "cdns,max-outbound-regions" in EP mode and removed
   "cdns,max-outbound-regions" for RC mode.
*) Remove patches specific to J721E

V1 of the patch series can be found @:
http://lore.kernel.org/r/20201102101154.13598-1-kishon@ti.com

Kishon Vijay Abraham I (7):
  dt-bindings: mfd: ti,j721e-system-controller.yaml: Document "syscon"
  dt-bindings: PCI: Add host mode dt-bindings for TI's J7200 SoC
  dt-bindings: PCI: Add EP mode dt-bindings for TI's J7200 SoC
  arm64: dts: ti: k3-j7200-main: Add DT for WIZ and SERDES
  arm64: dts: ti: k3-j7200-main: Add PCIe device tree node
  arm64: dts: ti: k3-j7200-common-proc-board: Enable SERDES0
  arm64: dts: ti: k3-j7200-common-proc-board: Enable PCIe

 .../mfd/ti,j721e-system-controller.yaml       |  40 ++++++
 .../bindings/pci/ti,j721e-pci-ep.yaml         |  10 +-
 .../bindings/pci/ti,j721e-pci-host.yaml       |  16 ++-
 .../dts/ti/k3-j7200-common-proc-board.dts     |  38 ++++++
 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi     | 118 ++++++++++++++++++
 5 files changed, 217 insertions(+), 5 deletions(-)

Comments

Vignesh Raghavendra Nov. 12, 2020, 3:56 p.m. UTC | #1 
On 11/9/20 10:34 PM, Kishon Vijay Abraham I wrote:
> x2 lane PCIe slot in the common processor board is enabled and connected to
> j7200 SOM. Add PCIe DT node in common processor board to reflect the
> same.
> 
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---

Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>

>  .../boot/dts/ti/k3-j7200-common-proc-board.dts    | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> index 65a2e5aeb050..174a55a18522 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> @@ -6,6 +6,7 @@
>  /dts-v1/;
>  
>  #include "k3-j7200-som-p0.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
>  #include <dt-bindings/net/ti-dp83867.h>
>  #include <dt-bindings/mux/ti-serdes.h>
>  #include <dt-bindings/phy/phy.h>
> @@ -236,3 +237,17 @@
>  		resets = <&serdes_wiz0 3>;
>  	};
>  };
> +
> +&pcie1_rc {
> +	reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
> +	phys = <&serdes0_pcie_link>;
> +	phy-names = "pcie-phy";
> +	num-lanes = <2>;
> +};
> +
> +&pcie1_ep {
> +	phys = <&serdes0_pcie_link>;
> +	phy-names = "pcie-phy";
> +	num-lanes = <2>;
> +	status = "disabled";
> +};
>
Vignesh Raghavendra Nov. 12, 2020, 3:58 p.m. UTC | #2 
On 11/9/20 10:34 PM, Kishon Vijay Abraham I wrote:
> Add sub-nodes to SERDES0 DT node to represent SERDES0 is connected
> to PCIe and QSGMII (multi-link SERDES).
> 
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
>  .../dts/ti/k3-j7200-common-proc-board.dts     | 23 +++++++++++++++++++
>  1 file changed, 23 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> index ef03e7636b66..65a2e5aeb050 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> @@ -8,6 +8,7 @@
>  #include "k3-j7200-som-p0.dtsi"
>  #include <dt-bindings/net/ti-dp83867.h>
>  #include <dt-bindings/mux/ti-serdes.h>
> +#include <dt-bindings/phy/phy.h>
>  
>  / {
>  	chosen {
> @@ -213,3 +214,25 @@
>  	dr_mode = "otg";
>  	maximum-speed = "high-speed";
>  };
> +
> +&serdes_refclk {
> +	clock-frequency = <100000000>;
> +};

Since this is a reference clk from the board, should the entire node be
here instead of in k3-j7200-main.dtsi?

> +
> +&serdes0 {
> +	serdes0_pcie_link: phy@0 {
> +		reg = <0>;
> +		cdns,num-lanes = <2>;
> +		#phy-cells = <0>;
> +		cdns,phy-type = <PHY_TYPE_PCIE>;
> +		resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
> +	};
> +
> +	serdes0_qsgmii_link: phy@1 {
> +		reg = <2>;
> +		cdns,num-lanes = <1>;
> +		#phy-cells = <0>;
> +		cdns,phy-type = <PHY_TYPE_QSGMII>;
> +		resets = <&serdes_wiz0 3>;
> +	};
> +};
>
Vignesh Raghavendra Nov. 12, 2020, 4:05 p.m. UTC | #3 
On 11/9/20 10:34 PM, Kishon Vijay Abraham I wrote:
> Add PCIe device tree node (both RC and EP) for the single PCIe
> instance present in j7200.
> 

nit: s/j7200/J7200

> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---

Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>

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