| Message ID | 20200929141454.2312-1-thunder.leizhen@huawei.com |
|---|---|
| Headers | show |
| Series | add support for Hisilicon SD5203 SoC | expand |
Hi Zhen Lei, On 2020/9/29 22:14, Zhen Lei wrote: > From: Kefeng Wang <wangkefeng.wang@huawei.com> > > Enable support for the Hisilicon SD5203 SoC. The core is ARM926EJ-S. > > Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> > Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Thanks! Applied to the hisilicon arm32 SoC tree. Best Regards, Wei > --- > arch/arm/mach-hisi/Kconfig | 16 ++++++++++++++-- > 1 file changed, 14 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/mach-hisi/Kconfig b/arch/arm/mach-hisi/Kconfig > index 3b010fe7c0e9b48..2e980f834a6aa1b 100644 > --- a/arch/arm/mach-hisi/Kconfig > +++ b/arch/arm/mach-hisi/Kconfig > @@ -1,9 +1,9 @@ > # SPDX-License-Identifier: GPL-2.0-only > config ARCH_HISI > bool "Hisilicon SoC Support" > - depends on ARCH_MULTI_V7 > + depends on ARCH_MULTI_V7 || ARCH_MULTI_V5 > select ARM_AMBA > - select ARM_GIC > + select ARM_GIC if ARCH_MULTI_V7 > select ARM_TIMER_SP804 > select POWER_RESET > select POWER_RESET_HISI > @@ -15,6 +15,7 @@ menu "Hisilicon platform type" > > config ARCH_HI3xxx > bool "Hisilicon Hi36xx family" > + depends on ARCH_MULTI_V7 > select CACHE_L2X0 > select HAVE_ARM_SCU if SMP > select HAVE_ARM_TWD if SMP > @@ -25,6 +26,7 @@ config ARCH_HI3xxx > > config ARCH_HIP01 > bool "Hisilicon HIP01 family" > + depends on ARCH_MULTI_V7 > select HAVE_ARM_SCU if SMP > select HAVE_ARM_TWD if SMP > select ARM_GLOBAL_TIMER > @@ -33,6 +35,7 @@ config ARCH_HIP01 > > config ARCH_HIP04 > bool "Hisilicon HiP04 Cortex A15 family" > + depends on ARCH_MULTI_V7 > select ARM_ERRATA_798181 if SMP > select HAVE_ARM_ARCH_TIMER > select MCPM if SMP > @@ -43,6 +46,7 @@ config ARCH_HIP04 > > config ARCH_HIX5HD2 > bool "Hisilicon X5HD2 family" > + depends on ARCH_MULTI_V7 > select CACHE_L2X0 > select HAVE_ARM_SCU if SMP > select HAVE_ARM_TWD if SMP > @@ -50,6 +54,14 @@ config ARCH_HIX5HD2 > select PINCTRL_SINGLE > help > Support for Hisilicon HIX5HD2 SoC family > + > +config ARCH_SD5203 > + bool "Hisilicon SD5203 family" > + depends on ARCH_MULTI_V5 > + select DW_APB_ICTL > + help > + Support for Hisilicon SD5203 SoC family > + > endmenu > > endif >
Hi Zhen Lei, On 2020/9/29 22:14, Zhen Lei wrote: > From: Kefeng Wang <wangkefeng.wang@huawei.com> > > Add support of early console for SD5203. > > Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> > Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Thanks! Applied to the hisilicon arm32 SoC tree. Best Regards, Wei > --- > arch/arm/Kconfig.debug | 11 ++++++++++- > 1 file changed, 10 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug > index 80000a66a4e3549..d27a7764c3bfb46 100644 > --- a/arch/arm/Kconfig.debug > +++ b/arch/arm/Kconfig.debug > @@ -1086,6 +1086,14 @@ choice > on SA-11x0 UART ports. The kernel will check for the first > enabled UART in a sequence 3-1-2. > > + config DEBUG_SD5203_UART > + bool "Hisilicon SD5203 Debug UART" > + depends on ARCH_SD5203 > + select DEBUG_UART_8250 > + help > + Say Y here if you want kernel low-level debugging support > + on SD5203 UART. > + > config DEBUG_SOCFPGA_UART0 > depends on ARCH_SOCFPGA > bool "Use SOCFPGA UART0 for low-level debug" > @@ -1639,6 +1647,7 @@ config DEBUG_UART_PHYS > default 0x11006000 if DEBUG_MT6589_UART0 > default 0x11009000 if DEBUG_MT8135_UART3 > default 0x16000000 if DEBUG_INTEGRATOR > + default 0x1600d000 if DEBUG_SD5203_UART > default 0x18000300 if DEBUG_BCM_5301X > default 0x18000400 if DEBUG_BCM_HR2 > default 0x18010000 if DEBUG_SIRFATLAS7_UART0 > @@ -1841,7 +1850,7 @@ config DEBUG_UART_VIRT > default 0xfec60000 if DEBUG_SIRFPRIMA2_UART1 > default 0xfec90000 if DEBUG_RK32_UART2 > default 0xfed0c000 if DEBUG_DAVINCI_DA8XX_UART1 > - default 0xfed0d000 if DEBUG_DAVINCI_DA8XX_UART2 > + default 0xfed0d000 if DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_SD5203_UART > default 0xfed60000 if DEBUG_RK29_UART0 > default 0xfed64000 if DEBUG_RK29_UART1 || DEBUG_RK3X_UART2 > default 0xfed68000 if DEBUG_RK29_UART2 || DEBUG_RK3X_UART3 >
Hi Zhen Lei, On 2020/9/29 22:14, Zhen Lei wrote: > From: Kefeng Wang <wangkefeng.wang@huawei.com> > > Add sd5203.dts for Hisilicon SD5203 SoC platform. > > Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> > Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Thanks! Applied to the hisilicon arm32 dt tree. Best Regards, Wei > --- > arch/arm/boot/dts/Makefile | 2 + > arch/arm/boot/dts/sd5203.dts | 96 ++++++++++++++++++++++++++++++++++++++++++++ > 2 files changed, 98 insertions(+) > create mode 100644 arch/arm/boot/dts/sd5203.dts > > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile > index 4572db3fa5ae302..1d1262df5c55907 100644 > --- a/arch/arm/boot/dts/Makefile > +++ b/arch/arm/boot/dts/Makefile > @@ -357,6 +357,8 @@ dtb-$(CONFIG_ARCH_MPS2) += \ > mps2-an399.dtb > dtb-$(CONFIG_ARCH_MOXART) += \ > moxart-uc7112lx.dtb > +dtb-$(CONFIG_ARCH_SD5203) += \ > + sd5203.dtb > dtb-$(CONFIG_SOC_IMX1) += \ > imx1-ads.dtb \ > imx1-apf9328.dtb > diff --git a/arch/arm/boot/dts/sd5203.dts b/arch/arm/boot/dts/sd5203.dts > new file mode 100644 > index 000000000000000..3cc9a23910be62e > --- /dev/null > +++ b/arch/arm/boot/dts/sd5203.dts > @@ -0,0 +1,96 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (c) 2020 Hisilicon Limited. > + * > + * DTS file for Hisilicon SD5203 Board > + */ > + > +/dts-v1/; > + > +/ { > + model = "Hisilicon SD5203"; > + compatible = "H836ASDJ", "hisilicon,sd5203"; > + interrupt-parent = <&vic>; > + #address-cells = <1>; > + #size-cells = <1>; > + > + chosen { > + bootargs="console=ttyS0,9600 earlycon=uart8250,mmio32,0x1600d000"; > + }; > + > + aliases { > + serial0 = &uart0; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu0 { > + device_type = "cpu"; > + compatible = "arm,arm926ej-s"; > + reg = <0x0>; > + }; > + }; > + > + memory@30000000 { > + device_type = "memory"; > + reg = <0x30000000 0x8000000>; > + }; > + > + soc { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "simple-bus"; > + ranges; > + > + vic: interrupt-controller@10130000 { > + compatible = "snps,dw-apb-ictl"; > + reg = <0x10130000 0x1000>; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > + > + refclk125mhz: refclk125mhz { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <125000000>; > + }; > + > + timer0: timer@16002000 { > + compatible = "arm,sp804", "arm,primecell"; > + reg = <0x16002000 0x1000>; > + interrupts = <4>; > + clocks = <&refclk125mhz>; > + clock-names = "apb_pclk"; > + }; > + > + timer1: timer@16003000 { > + compatible = "arm,sp804", "arm,primecell"; > + reg = <0x16003000 0x1000>; > + interrupts = <5>; > + clocks = <&refclk125mhz>; > + clock-names = "apb_pclk"; > + }; > + > + uart0: serial@1600d000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x1600d000 0x1000>; > + bus_id = "uart0"; > + clocks = <&refclk125mhz>; > + clock-names = "baudclk", "apb_pclk"; > + reg-shift = <2>; > + interrupts = <17>; > + }; > + > + uart1: serial@1600c000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x1600c000 0x1000>; > + clocks = <&refclk125mhz>; > + clock-names = "baudclk", "apb_pclk"; > + reg-shift = <2>; > + interrupts = <16>; > + status = "disabled"; > + }; > + }; > +}; >
Hi Zhen Lei, On 2020/9/29 22:14, Zhen Lei wrote: > The DT binding for Hisilicon system controllers requires to have a > "syscon" compatible string. > > Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Thanks! Applied to the hisilicon arm32 dt tree. Best Regards, Wei > --- > arch/arm/boot/dts/hi3620.dtsi | 2 +- > arch/arm/boot/dts/hip04.dtsi | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi > index 355175b25fd6220..f683440ee5694b4 100644 > --- a/arch/arm/boot/dts/hi3620.dtsi > +++ b/arch/arm/boot/dts/hi3620.dtsi > @@ -89,7 +89,7 @@ > }; > > sysctrl: system-controller@802000 { > - compatible = "hisilicon,sysctrl"; > + compatible = "hisilicon,sysctrl", "syscon"; > #address-cells = <1>; > #size-cells = <1>; > ranges = <0 0x802000 0x1000>; > diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi > index f5871b1d1ec452c..555bc6b6720fc94 100644 > --- a/arch/arm/boot/dts/hip04.dtsi > +++ b/arch/arm/boot/dts/hip04.dtsi > @@ -213,7 +213,7 @@ > }; > > sysctrl: sysctrl { > - compatible = "hisilicon,sysctrl"; > + compatible = "hisilicon,sysctrl", "syscon"; > reg = <0x3e00000 0x00100000>; > }; > >
v4 --> v5: 1. Drop the descriptions of the common properties, such as "reg". 2. Add "additionalProperties: false" or "additionalProperties: type: object" for each new yaml file. 3. Group three Hi6220 domain controller into one yaml file, see Patch 15 4. Remove the prefix "hisilicon," of each yaml file, all of them are under hisilicon directory, no need to duplicated it. 5. move four controllers into syscon.yaml, because they have no specific properties, see Patch 1-2. 6. Add the name of the board which based on sd5203, see Patch 5 and 8. 7. Add Patch 9, all controller should contain "syscon" compatible string. 8. Add property "ranges" and update the example, see Patch 16. 9. Romove the labels in all examples. 10. other trival fixes are not mentioned. Please review Patch 1-9 first, other patches are not urgent and each of them is independent. v3 --> v4: 1. remove unexpected "\ No newline at end of file" of each new file. 2. discard the subdirectory "hi3620" and "hipxx", all files in the two directories are moved to the parent directory. 3. add two spaces for the below cases: - items: - const: hisilicon,sysctrl. //add two spaces 4. only list the compatible of boards in hisilicon.yaml, that is: 1) a compatible of one board 2) a compatible of one board + a compatible of one SoC 5. other trival fixes are not mentioned. v2 --> v3: 1. Convert hisilicon.txt to hisilicon.yaml. Because there are many kinds of Hisilicon controllers in it, so split each of them into a separate file first. Then I convert all of them to DT schema format, and also convert the other files in directory "../bindings/arm/hisilicon/". 2. Add Patch 1: remove a unused compatible name in hip01-ca9x2.dts This error is detected by hisilicon.yaml. The merge window of 5.10 is narrow now, so please review Patch 1-7 first. v1 --> v2: 1. add binding for SD5203 SoC, Patch 1 2. select DW_APB_ICTL instead of HISILICON_SD5203_VIC in Patch 2. Meanwhile, change the compatible of interrupt-controller to "snps,dw-apb-ictl" in Patch 4. 3. Fix the errors detected by dtbs_check. For example: add "reg" for cpu node, use lowercase a-f to describe address, add "baudclk" for "snps,dw-apb-uart". v1: Add SD5203 SoC config option and devicetree file, also enable its debug UART. Kefeng Wang (3): ARM: hisi: add support for SD5203 SoC ARM: debug: add UART early console support for SD5203 ARM: dts: add SD5203 dts Zhen Lei (14): dt-bindings: mfd: syscon: add some compatible strings for Hisilicon dt-bindings: arm: hisilicon: delete the descriptions of HiP05/HiP06 controllers dt-bindings: arm: hisilicon: split the dt-bindings of each controller into a separate file dt-bindings: arm: hisilicon: convert Hisilicon board/soc bindings to json-schema dt-bindings: arm: hisilicon: add binding for SD5203 SoC ARM: dts: hisilicon: fix ststem controller compatible node dt-bindings: arm: hisilicon: convert system controller bindings to json-schema dt-bindings: arm: hisilicon: convert hisilicon,cpuctrl bindings to json-schema dt-bindings: arm: hisilicon: convert hisilicon,pctrl bindings to json-schema dt-bindings: arm: hisilicon: convert hisilicon,hip04-fabric bindings to json-schema dt-bindings: arm: hisilicon: convert hisilicon,hip04-bootwrapper bindings to json-schema dt-bindings: arm: hisilicon: convert Hi6220 domain controller bindings to json-schema dt-bindings: arm: hisilicon: convert hisilicon,hi3798cv200-perictrl bindings to json-schema dt-bindings: arm: hisilicon: convert LPC controller bindings to json-schema .../bindings/arm/hisilicon/controller/cpuctrl.yaml | 29 ++ .../hisilicon/controller/hi3798cv200-perictrl.yaml | 64 +++++ .../hisilicon/controller/hi6220-domain-ctrl.yaml | 64 +++++ .../hisilicon/controller/hip04-bootwrapper.yaml | 34 +++ .../arm/hisilicon/controller/hip04-fabric.yaml | 27 ++ .../bindings/arm/hisilicon/controller/pctrl.yaml | 34 +++ .../bindings/arm/hisilicon/controller/sysctrl.yaml | 110 +++++++ .../bindings/arm/hisilicon/hi3519-sysctrl.txt | 14 - .../arm/hisilicon/hisilicon-low-pin-count.txt | 33 --- .../bindings/arm/hisilicon/hisilicon.txt | 319 --------------------- .../bindings/arm/hisilicon/hisilicon.yaml | 67 +++++ .../bindings/arm/hisilicon/low-pin-count.yaml | 61 ++++ Documentation/devicetree/bindings/mfd/syscon.yaml | 5 +- arch/arm/Kconfig.debug | 11 +- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/hi3620.dtsi | 2 +- arch/arm/boot/dts/hip04.dtsi | 2 +- arch/arm/boot/dts/sd5203.dts | 96 +++++++ arch/arm/mach-hisi/Kconfig | 16 +- 19 files changed, 618 insertions(+), 372 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/cpuctrl.yaml create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hi3798cv200-perictrl.yaml create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hi6220-domain-ctrl.yaml create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hip04-bootwrapper.yaml create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hip04-fabric.yaml create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/pctrl.yaml create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/sysctrl.yaml delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/low-pin-count.yaml create mode 100644 arch/arm/boot/dts/sd5203.dts