| Message ID | 20200918080024.13639-1-Zhiqiang.Hou@nxp.com |
|---|---|
| Headers | show |
| Series | PCI: dwc: Add the multiple PF support for DWC and Layerscape | expand |
On Fri, Sep 18, 2020 at 04:00:12PM +0800, Zhiqiang Hou wrote: > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > Add the PCIe EP multiple PF support for DWC and Layerscape, and use > a list to manage the PFs of each PCIe controller; add the doorbell > MSIX function for DWC; and refactor the Layerscape EP driver due to > some difference in Layercape platforms PCIe integration. > > Rebased this series against pci/dwc branch of git tree: > https://git.kernel.org/pub/scm/linux/kernel/git/lpieralisi/pci.git I have merged the series on top of the current pci/dwc branch, tentatively for v5.10, thanks. Lorenzo > > Hou Zhiqiang (1): > misc: pci_endpoint_test: Add driver data for Layerscape PCIe > controllers > > Xiaowei Bao (11): > PCI: designware-ep: Add multiple PFs support for DWC > PCI: designware-ep: Add the doorbell mode of MSI-X in EP mode > PCI: designware-ep: Move the function of getting MSI capability > forward > PCI: designware-ep: Modify MSI and MSIX CAP way of finding > dt-bindings: pci: layerscape-pci: Add compatible strings for ls1088a > and ls2088a > PCI: layerscape: Fix some format issue of the code > PCI: layerscape: Modify the way of getting capability with different > PEX > PCI: layerscape: Modify the MSIX to the doorbell mode > PCI: layerscape: Add EP mode support for ls1088a and ls2088a > arm64: dts: layerscape: Add PCIe EP node for ls1088a > misc: pci_endpoint_test: Add LS1088a in pci_device_id table > > .../bindings/pci/layerscape-pci.txt | 2 + > .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 31 +++ > drivers/misc/pci_endpoint_test.c | 8 +- > .../pci/controller/dwc/pci-layerscape-ep.c | 100 +++++-- > .../pci/controller/dwc/pcie-designware-ep.c | 245 ++++++++++++++---- > drivers/pci/controller/dwc/pcie-designware.c | 59 +++-- > drivers/pci/controller/dwc/pcie-designware.h | 48 +++- > 7 files changed, 397 insertions(+), 96 deletions(-) > > -- > 2.17.1 >
On Fri, Sep 18, 2020 at 04:00:22PM +0800, Zhiqiang Hou wrote: > From: Xiaowei Bao <xiaowei.bao@nxp.com> > > Add PCIe EP node for ls1088a to support EP mode. > > Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > Reviewed-by: Andrew Murray <andrew.murray@arm.com> > --- > V8: > - s/pcie_ep/pcie-ep. > > .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 31 +++++++++++++++++++ > 1 file changed, 31 insertions(+) Dropped this patch. dts files updates should be sent via arm-soc along with platform support. Thanks, Lorenzo > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi > index 169f4742ae3b..f21dd143ab6d 100644 > --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi > @@ -499,6 +499,17 @@ > status = "disabled"; > }; > > + pcie-ep@3400000 { > + compatible = "fsl,ls1088a-pcie-ep","fsl,ls-pcie-ep"; > + reg = <0x00 0x03400000 0x0 0x00100000 > + 0x20 0x00000000 0x8 0x00000000>; > + reg-names = "regs", "addr_space"; > + num-ib-windows = <24>; > + num-ob-windows = <128>; > + max-functions = /bits/ 8 <2>; > + status = "disabled"; > + }; > + > pcie@3500000 { > compatible = "fsl,ls1088a-pcie"; > reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ > @@ -525,6 +536,16 @@ > status = "disabled"; > }; > > + pcie-ep@3500000 { > + compatible = "fsl,ls1088a-pcie-ep","fsl,ls-pcie-ep"; > + reg = <0x00 0x03500000 0x0 0x00100000 > + 0x28 0x00000000 0x8 0x00000000>; > + reg-names = "regs", "addr_space"; > + num-ib-windows = <6>; > + num-ob-windows = <8>; > + status = "disabled"; > + }; > + > pcie@3600000 { > compatible = "fsl,ls1088a-pcie"; > reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ > @@ -551,6 +572,16 @@ > status = "disabled"; > }; > > + pcie-ep@3600000 { > + compatible = "fsl,ls1088a-pcie-ep","fsl,ls-pcie-ep"; > + reg = <0x00 0x03600000 0x0 0x00100000 > + 0x30 0x00000000 0x8 0x00000000>; > + reg-names = "regs", "addr_space"; > + num-ib-windows = <6>; > + num-ob-windows = <8>; > + status = "disabled"; > + }; > + > smmu: iommu@5000000 { > compatible = "arm,mmu-500"; > reg = <0 0x5000000 0 0x800000>; > -- > 2.17.1 >
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Add the PCIe EP multiple PF support for DWC and Layerscape, and use a list to manage the PFs of each PCIe controller; add the doorbell MSIX function for DWC; and refactor the Layerscape EP driver due to some difference in Layercape platforms PCIe integration. Rebased this series against pci/dwc branch of git tree: https://git.kernel.org/pub/scm/linux/kernel/git/lpieralisi/pci.git Hou Zhiqiang (1): misc: pci_endpoint_test: Add driver data for Layerscape PCIe controllers Xiaowei Bao (11): PCI: designware-ep: Add multiple PFs support for DWC PCI: designware-ep: Add the doorbell mode of MSI-X in EP mode PCI: designware-ep: Move the function of getting MSI capability forward PCI: designware-ep: Modify MSI and MSIX CAP way of finding dt-bindings: pci: layerscape-pci: Add compatible strings for ls1088a and ls2088a PCI: layerscape: Fix some format issue of the code PCI: layerscape: Modify the way of getting capability with different PEX PCI: layerscape: Modify the MSIX to the doorbell mode PCI: layerscape: Add EP mode support for ls1088a and ls2088a arm64: dts: layerscape: Add PCIe EP node for ls1088a misc: pci_endpoint_test: Add LS1088a in pci_device_id table .../bindings/pci/layerscape-pci.txt | 2 + .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 31 +++ drivers/misc/pci_endpoint_test.c | 8 +- .../pci/controller/dwc/pci-layerscape-ep.c | 100 +++++-- .../pci/controller/dwc/pcie-designware-ep.c | 245 ++++++++++++++---- drivers/pci/controller/dwc/pcie-designware.c | 59 +++-- drivers/pci/controller/dwc/pcie-designware.h | 48 +++- 7 files changed, 397 insertions(+), 96 deletions(-)