| Message ID | 20200812140217.24251-1-prabhakar.mahadev-lad.rj@bp.renesas.com |
|---|---|
| Headers | show |
| Series | r8a774e1 add support for DU, HDMI and LVDS | expand |
Hi Prabhakar, Thank you for the patch. On Wed, Aug 12, 2020 at 03:02:10PM +0100, Lad Prabhakar wrote: > From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> > > Hookup RZ/G2H (R8A774E1) to DU driver. R8A774E1 has one RGB output, > one LVDS output and one HDMI output. > > Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > --- > drivers/gpu/drm/rcar-du/rcar_du_drv.c | 30 +++++++++++++++++++++++++++ > 1 file changed, 30 insertions(+) > > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c > index 3e67cf70f040..398c180b8731 100644 > --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c > +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c > @@ -186,6 +186,35 @@ static const struct rcar_du_device_info rcar_du_r8a774c0_info = { > .lvds_clk_mask = BIT(1) | BIT(0), > }; > > +static const struct rcar_du_device_info rcar_du_r8a774e1_info = { > + .gen = 3, > + .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK > + | RCAR_DU_FEATURE_VSP1_SOURCE > + | RCAR_DU_FEATURE_INTERLACED > + | RCAR_DU_FEATURE_TVM_SYNC, > + .channels_mask = BIT(3) | BIT(1) | BIT(0), > + .routes = { > + /* > + * R8A774E1 has one RGB output, one LVDS output and one HDMI > + * output. > + */ > + [RCAR_DU_OUTPUT_DPAD0] = { > + .possible_crtcs = BIT(2), > + .port = 0, > + }, > + [RCAR_DU_OUTPUT_HDMI0] = { > + .possible_crtcs = BIT(1), > + .port = 1, > + }, > + [RCAR_DU_OUTPUT_LVDS0] = { > + .possible_crtcs = BIT(0), > + .port = 2, > + }, > + }, > + .num_lvds = 1, > + .dpll_mask = BIT(1), > +}; > + > static const struct rcar_du_device_info rcar_du_r8a7779_info = { > .gen = 1, > .features = RCAR_DU_FEATURE_INTERLACED > @@ -450,6 +479,7 @@ static const struct of_device_id rcar_du_of_table[] = { > { .compatible = "renesas,du-r8a774a1", .data = &rcar_du_r8a774a1_info }, > { .compatible = "renesas,du-r8a774b1", .data = &rcar_du_r8a774b1_info }, > { .compatible = "renesas,du-r8a774c0", .data = &rcar_du_r8a774c0_info }, > + { .compatible = "renesas,du-r8a774e1", .data = &rcar_du_r8a774e1_info }, > { .compatible = "renesas,du-r8a7779", .data = &rcar_du_r8a7779_info }, > { .compatible = "renesas,du-r8a7790", .data = &rcar_du_r8a7790_info }, > { .compatible = "renesas,du-r8a7791", .data = &rcar_du_r8a7791_info },
Hi Prabhakar, Thank you for the patch. On Wed, Aug 12, 2020 at 03:02:11PM +0100, Lad Prabhakar wrote: > From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> > > Populate the DU device node properties in R8A774E1 SoC dtsi. > > Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > --- > arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 19 ++++++++++++++++++- > 1 file changed, 18 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi > index abaa6d7f6b31..4b57c1ea762c 100644 > --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi > @@ -2623,22 +2623,39 @@ > }; > > du: display@feb00000 { > + compatible = "renesas,du-r8a774e1"; > reg = <0 0xfeb00000 0 0x80000>; > + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_MOD 724>, > + <&cpg CPG_MOD 723>, > + <&cpg CPG_MOD 721>; > + clock-names = "du.0", "du.1", "du.3"; > + resets = <&cpg 724>, <&cpg 722>; > + reset-names = "du.0", "du.3"; > status = "disabled"; > > - /* placeholder */ > + renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>; > + > ports { > #address-cells = <1>; > #size-cells = <0>; > > port@0 { > reg = <0>; > + du_out_rgb: endpoint { > + }; > }; > port@1 { > reg = <1>; > + du_out_hdmi0: endpoint { > + }; > }; > port@2 { > reg = <2>; > + du_out_lvds0: endpoint { > + }; > }; > }; > };
Hi Prabhakar, Thank you for the patch. On Wed, Aug 12, 2020 at 03:02:14PM +0100, Lad Prabhakar wrote: > From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> > > Populate HDMI node properties in R8A774E1 SoC dtsi. > > Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > --- > arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 15 +++++++++++++-- > 1 file changed, 13 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi > index 4b57c1ea762c..79efcd73cc46 100644 > --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi > @@ -2601,22 +2601,32 @@ > }; > > hdmi0: hdmi@fead0000 { > + compatible = "renesas,r8a774e1-hdmi", > + "renesas,rcar-gen3-hdmi"; > reg = <0 0xfead0000 0 0x10000>; > + interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_MOD 729>, > + <&cpg CPG_CORE R8A774E1_CLK_HDMI>; > + clock-names = "iahb", "isfr"; > + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; > + resets = <&cpg 729>; > status = "disabled"; > > - /* placeholder */ > - > ports { > #address-cells = <1>; > #size-cells = <0>; > > port@0 { > reg = <0>; > + dw_hdmi0_in: endpoint { > + remote-endpoint = <&du_out_hdmi0>; > + }; > }; > port@1 { > reg = <1>; > }; > port@2 { > + /* HDMI sound */ > reg = <2>; > }; > }; > @@ -2650,6 +2660,7 @@ > port@1 { > reg = <1>; > du_out_hdmi0: endpoint { > + remote-endpoint = <&dw_hdmi0_in>; > }; > }; > port@2 {
Hi Prabhakar, Thank you for the patch. On Wed, Aug 12, 2020 at 03:02:15PM +0100, Lad Prabhakar wrote: > From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> > > The LVDS encoder on RZ/G2H (R8A774E1) SoC is identical to R-Car Gen3 so > just reuse the rcar_lvds_gen3_info structure to hookup R8A774E1 to LVDS > encoder driver. > > Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > --- > drivers/gpu/drm/rcar-du/rcar_lvds.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/rcar-du/rcar_lvds.c b/drivers/gpu/drm/rcar-du/rcar_lvds.c > index ab0d49618cf9..424ca2b7d9ac 100644 > --- a/drivers/gpu/drm/rcar-du/rcar_lvds.c > +++ b/drivers/gpu/drm/rcar-du/rcar_lvds.c > @@ -987,6 +987,7 @@ static const struct of_device_id rcar_lvds_of_table[] = { > { .compatible = "renesas,r8a774a1-lvds", .data = &rcar_lvds_gen3_info }, > { .compatible = "renesas,r8a774b1-lvds", .data = &rcar_lvds_gen3_info }, > { .compatible = "renesas,r8a774c0-lvds", .data = &rcar_lvds_r8a77990_info }, > + { .compatible = "renesas,r8a774e1-lvds", .data = &rcar_lvds_gen3_info }, > { .compatible = "renesas,r8a7790-lvds", .data = &rcar_lvds_gen2_info }, > { .compatible = "renesas,r8a7791-lvds", .data = &rcar_lvds_gen2_info }, > { .compatible = "renesas,r8a7793-lvds", .data = &rcar_lvds_gen2_info },
Hi Prabhakar, Thank you for the patch. On Wed, Aug 12, 2020 at 03:02:16PM +0100, Lad Prabhakar wrote: > From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> > > Add the LVDS device node to R8A774E1 to SoC dtsi and connect it with > the DU node. > > Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > --- > arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 27 +++++++++++++++++++++++ > 1 file changed, 27 insertions(+) > > diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi > index 79efcd73cc46..f783ad8aeafa 100644 > --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi > @@ -2666,6 +2666,33 @@ > port@2 { > reg = <2>; > du_out_lvds0: endpoint { > + remote-endpoint = <&lvds0_in>; > + }; > + }; > + }; > + }; > + > + lvds0: lvds@feb90000 { > + compatible = "renesas,r8a774e1-lvds"; > + reg = <0 0xfeb90000 0 0x14>; > + clocks = <&cpg CPG_MOD 727>; > + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; > + resets = <&cpg 727>; > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + lvds0_in: endpoint { > + remote-endpoint = <&du_out_lvds0>; > + }; > + }; > + port@1 { > + reg = <1>; > + lvds0_out: endpoint { > }; > }; > };
Hi Prabhakar, Thank you for the patch. On Wed, Aug 12, 2020 at 03:02:17PM +0100, Lad Prabhakar wrote: > Setup up the required clocks for the DU to be functional. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h.dts | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h.dts b/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h.dts > index cdbe527e9340..12f9242e263b 100644 > --- a/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h.dts > +++ b/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h.dts > @@ -24,3 +24,14 @@ > reg = <0x5 0x00000000 0x0 0x80000000>; > }; > }; > + > +&du { > + clocks = <&cpg CPG_MOD 724>, > + <&cpg CPG_MOD 723>, > + <&cpg CPG_MOD 721>, > + <&versaclock5 1>, > + <&x302_clk>, > + <&versaclock5 2>; > + clock-names = "du.0", "du.1", "du.3", > + "dclkin.0", "dclkin.1", "dclkin.3"; I have no reason to doubt this is correct, but I also can't assess that as I don't have access to the schematics. Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > +};
Hi Prabhakar, Thank you for the patches. On Wed, Aug 12, 2020 at 03:02:08PM +0100, Lad Prabhakar wrote: > Hi All, > > This patch series adds support for DU, HDMI and LVDS to RZ/G2H SoC. I have added patches 1/9, 2/9, 4/9, 5/9 and 7/9 to my tree. I expect Geert to handle the rest. > Lad Prabhakar (1): > arm64: dts: renesas: r8a774e1-hihope-rzg2h: Setup DU clocks > > Marian-Cristian Rotariu (8): > dt-bindings: display: renesas,du: Document r8a774e1 bindings > drm: rcar-du: Add support for R8A774E1 SoC > arm64: dts: renesas: r8a774e1: Populate DU device node > dt-bindings: display: renesas,lvds: Document r8a774e1 bindings > dt-bindings: display: renesas,dw-hdmi: Add r8a774e1 support > arm64: dts: renesas: r8a774e1: Populate HDMI encoder node > drm: rcar-du: lvds: Add support for R8A774E1 SoC > arm64: dts: renesas: r8a774e1: Add LVDS device node > > .../display/bridge/renesas,dw-hdmi.txt | 1 + > .../bindings/display/bridge/renesas,lvds.txt | 1 + > .../bindings/display/renesas,du.txt | 2 + > .../dts/renesas/r8a774e1-hihope-rzg2h.dts | 11 ++++ > arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 61 ++++++++++++++++++- > drivers/gpu/drm/rcar-du/rcar_du_drv.c | 30 +++++++++ > drivers/gpu/drm/rcar-du/rcar_lvds.c | 1 + > 7 files changed, 104 insertions(+), 3 deletions(-)
Hi Laurent, On Wed, Aug 12, 2020 at 5:39 PM Laurent Pinchart <laurent.pinchart@ideasonboard.com> wrote: > > Hi Prabhakar, > > Thank you for the patches. > > On Wed, Aug 12, 2020 at 03:02:08PM +0100, Lad Prabhakar wrote: > > Hi All, > > > > This patch series adds support for DU, HDMI and LVDS to RZ/G2H SoC. > > I have added patches 1/9, 2/9, 4/9, 5/9 and 7/9 to my tree. I expect > Geert to handle the rest. > Thank you for the review and taking care of LVDS documentation binding patch. Cheers, Prabhakar > > Lad Prabhakar (1): > > arm64: dts: renesas: r8a774e1-hihope-rzg2h: Setup DU clocks > > > > Marian-Cristian Rotariu (8): > > dt-bindings: display: renesas,du: Document r8a774e1 bindings > > drm: rcar-du: Add support for R8A774E1 SoC > > arm64: dts: renesas: r8a774e1: Populate DU device node > > dt-bindings: display: renesas,lvds: Document r8a774e1 bindings > > dt-bindings: display: renesas,dw-hdmi: Add r8a774e1 support > > arm64: dts: renesas: r8a774e1: Populate HDMI encoder node > > drm: rcar-du: lvds: Add support for R8A774E1 SoC > > arm64: dts: renesas: r8a774e1: Add LVDS device node > > > > .../display/bridge/renesas,dw-hdmi.txt | 1 + > > .../bindings/display/bridge/renesas,lvds.txt | 1 + > > .../bindings/display/renesas,du.txt | 2 + > > .../dts/renesas/r8a774e1-hihope-rzg2h.dts | 11 ++++ > > arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 61 ++++++++++++++++++- > > drivers/gpu/drm/rcar-du/rcar_du_drv.c | 30 +++++++++ > > drivers/gpu/drm/rcar-du/rcar_lvds.c | 1 + > > 7 files changed, 104 insertions(+), 3 deletions(-) > > -- > Regards, > > Laurent Pinchart
On Wed, Aug 12, 2020 at 4:03 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> > > Populate the DU device node properties in R8A774E1 SoC dtsi. > > Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi > @@ -2623,22 +2623,39 @@ > }; > > du: display@feb00000 { > + compatible = "renesas,du-r8a774e1"; > reg = <0 0xfeb00000 0 0x80000>; > + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_MOD 724>, > + <&cpg CPG_MOD 723>, > + <&cpg CPG_MOD 721>; > + clock-names = "du.0", "du.1", "du.3"; > + resets = <&cpg 724>, <&cpg 722>; > + reset-names = "du.0", "du.3"; > status = "disabled"; > > - /* placeholder */ > + renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>; > + > ports { > #address-cells = <1>; > #size-cells = <0>; > > port@0 { > reg = <0>; > + du_out_rgb: endpoint { > + }; > }; > port@1 { > reg = <1>; > + du_out_hdmi0: endpoint { > + }; > }; > port@2 { > reg = <2>; > + du_out_lvds0: endpoint { > + }; Waiting for the port number discussion to settle before queuein in renesas-devel for v5.10. > }; > }; > }; > -- > 2.17.1 >
On Wed, Aug 12, 2020 at 4:03 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> > > Populate HDMI node properties in R8A774E1 SoC dtsi. > > Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v5.10 (after resolving the port numbering). Gr{oetje,eeting}s, Geert
On Wed, Aug 12, 2020 at 4:03 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> > > Add the LVDS device node to R8A774E1 to SoC dtsi and connect it with > the DU node. > > Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v5.10 (after resolving the port numbering). Gr{oetje,eeting}s, Geert
On Wed, Aug 12, 2020 at 4:03 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > Setup up the required clocks for the DU to be functional. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v5.10 (after resolving the port numbering). Gr{oetje,eeting}s, Geert
On Wed, Aug 12, 2020 at 07:36:54PM +0300, Laurent Pinchart wrote: > Hi Prabhakar, > > Thank you for the patch. > > On Wed, Aug 12, 2020 at 03:02:17PM +0100, Lad Prabhakar wrote: > > Setup up the required clocks for the DU to be functional. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > --- > > arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h.dts | 11 +++++++++++ > > 1 file changed, 11 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h.dts b/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h.dts > > index cdbe527e9340..12f9242e263b 100644 > > --- a/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h.dts > > +++ b/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h.dts > > @@ -24,3 +24,14 @@ > > reg = <0x5 0x00000000 0x0 0x80000000>; > > }; > > }; > > + > > +&du { > > + clocks = <&cpg CPG_MOD 724>, > > + <&cpg CPG_MOD 723>, > > + <&cpg CPG_MOD 721>, > > + <&versaclock5 1>, > > + <&x302_clk>, > > + <&versaclock5 2>; > > + clock-names = "du.0", "du.1", "du.3", > > + "dclkin.0", "dclkin.1", "dclkin.3"; > > I have no reason to doubt this is correct, but I also can't assess that > as I don't have access to the schematics. > > Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Upgrading to Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> :-) > > > +};