| Message ID | 20200730154545.3965-1-Sergey.Semin@baikalelectronics.ru |
|---|---|
| Headers | show |
| Series | dmaengine: dw: Introduce non-mem peripherals optimizations | expand |
On Thu, Jul 30, 2020 at 06:45:42PM +0300, Serge Semin wrote: > CFGx.FIFO_MODE field controls a DMA-controller "FIFO readiness" criterion. > In other words it determines when to start pushing data out of a DW > DMAC channel FIFO to a destination peripheral or from a source > peripheral to the DW DMAC channel FIFO. Currently FIFO-mode is set to one > for all DW DMAC channels. It means they are tuned to flush data out of > FIFO (to a memory peripheral or by accepting the burst transaction > requests) when FIFO is at least half-full (except at the end of the block > transfer, when FIFO-flush mode is activated) and are configured to get > data to the FIFO when it's at least half-empty. > > Such configuration is a good choice when there is no slave device involved > in the DMA transfers. In that case the number of bursts per block is less > than when CFGx.FIFO_MODE = 0 and, hence, the bus utilization will improve. > But the latency of DMA transfers may increase when CFGx.FIFO_MODE = 1, > since DW DMAC will wait for the channel FIFO contents to be either > half-full or half-empty depending on having the destination or the source > transfers. Such latencies might be dangerous in case if the DMA transfers > are expected to be performed from/to a slave device. Since normally > peripheral devices keep data in internal FIFOs, any latency at some > critical moment may cause one being overflown and consequently losing > data. This especially concerns a case when either a peripheral device is > relatively fast or the DW DMAC engine is relatively slow with respect to > the incoming data pace. > > In order to solve problems, which might be caused by the latencies > described above, let's enable the FIFO half-full/half-empty "FIFO > readiness" criterion only for DMA transfers with no slave device involved. > Thanks to the commit ???????????? ("dmaengine: dw: Initialize channel See below. > before each transfer") we can freely do that in the generic > dw_dma_initialize_chan() method. Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Thanks! > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> > > --- > > Note the DMA-engine repository git.infradead.org/users/vkoul/slave-dma.git > isn't accessible. So I couldn't find out the Andy' commit hash to use it in > the log. It's dmaengine.git on git.kernel.org. > --- > drivers/dma/dw/dw.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/dma/dw/dw.c b/drivers/dma/dw/dw.c > index 7a085b3c1854..d9810980920a 100644 > --- a/drivers/dma/dw/dw.c > +++ b/drivers/dma/dw/dw.c > @@ -14,7 +14,7 @@ > static void dw_dma_initialize_chan(struct dw_dma_chan *dwc) > { > struct dw_dma *dw = to_dw_dma(dwc->chan.device); > - u32 cfghi = DWC_CFGH_FIFO_MODE; > + u32 cfghi = is_slave_direction(dwc->direction) ? 0 : DWC_CFGH_FIFO_MODE; > u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority); > bool hs_polarity = dwc->dws.hs_polarity; > > -- > 2.27.0 >
On Thu, Jul 30, 2020 at 06:45:43PM +0300, Serge Semin wrote: > Indeed in case of the DMA_DEV_TO_MEM DMA transfers it's enough to take the > destination memory address and the destination master data width into > account to calculate the CTLx.DST_TR_WIDTH setting of the memory > peripheral. According to the DW DMAC IP-core Databook (page 66, Example 5) Always put a version of the Databook document. I have several and they may differ. > at the and of a DMA transfer when the DMA-channel internal FIFO is left > with data less than for a single destination burst transaction, the > destination peripheral will enter the Single Transaction Region where the > DW DMA controller can complete a block transfer to the destination using > single transactions (non-burst transaction of CTLx.DST_TR_WIDTH bytes). If > there is no enough data in the DMA-channel internal FIFO for even a single > non-burst transaction of CTLx.DST_TR_WIDTH bytes, then the channel enters > "FIFO flush mode". That mode is activated to empty the FIFO and flush the > leftovers out to the memory peripheral. The flushing procedure is simple. > The data is sent to the memory by means of a set of single transaction of > CTLx.SRC_TR_WIDTH bytes. To sum up it's redundant to use the LLPs length > to find out the CTLx.DST_TR_WIDTH parameter value, since each DMA transfer > will be completed with the CTLx.SRC_TR_WIDTH bytes transaction if it is > required. > In this commit we remove the LLP entry length from the statement which "In this commit" should be removed, see Submitting Patches ("This patch"). > calculates the memory peripheral DMA transaction width since it's > redundant due to the feature described above. By doing so we'll improve > the memory bus utilization and speed up the DMA-channel performance for > DMA_DEV_TO_MEM DMA-transfers. Okay, I have no objections. Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> > --- > drivers/dma/dw/core.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c > index 4700f2e87a62..3da0aea9fe25 100644 > --- a/drivers/dma/dw/core.c > +++ b/drivers/dma/dw/core.c > @@ -723,7 +723,7 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, > lli_write(desc, sar, reg); > lli_write(desc, dar, mem); > lli_write(desc, ctlhi, ctlhi); > - mem_width = __ffs(data_width | mem | dlen); > + mem_width = __ffs(data_width | mem); > lli_write(desc, ctllo, ctllo | DWC_CTLL_DST_WIDTH(mem_width)); > desc->len = dlen; > > -- > 2.27.0 >
On Thu, Jul 30, 2020 at 06:45:44PM +0300, Serge Semin wrote: > According to the DW DMA controller Databook (page 40 "3.5 Memory Which version of it? > Peripherals") memory peripherals don't have handshaking interface > connected to the controller, therefore they can never be a flow > controller. Since the CTLx.SRC_MSIZE and CTLx.DEST_MSIZE are > properties valid only for peripherals with a handshaking > interface, we can freely zero these fields out if the memory peripheral > is selected to be the source or the destination of the DMA transfers. > > Note according to the databook, length of burst transfers to memory is > always equal to the number of data items available in a channel FIFO or > data items required to complete the block transfer, whichever is smaller; > length of burst transfers from memory is always equal to the space > available in a channel FIFO or number of data items required to complete > the block transfer, whichever is smaller. But does it really matter if you program there something or not?
On Thu, Jul 30, 2020 at 07:24:28PM +0300, Andy Shevchenko wrote: > On Thu, Jul 30, 2020 at 06:45:42PM +0300, Serge Semin wrote: > > CFGx.FIFO_MODE field controls a DMA-controller "FIFO readiness" criterion. > > In other words it determines when to start pushing data out of a DW > > DMAC channel FIFO to a destination peripheral or from a source > > peripheral to the DW DMAC channel FIFO. Currently FIFO-mode is set to one > > for all DW DMAC channels. It means they are tuned to flush data out of > > FIFO (to a memory peripheral or by accepting the burst transaction > > requests) when FIFO is at least half-full (except at the end of the block > > transfer, when FIFO-flush mode is activated) and are configured to get > > data to the FIFO when it's at least half-empty. > > > > Such configuration is a good choice when there is no slave device involved > > in the DMA transfers. In that case the number of bursts per block is less > > than when CFGx.FIFO_MODE = 0 and, hence, the bus utilization will improve. > > But the latency of DMA transfers may increase when CFGx.FIFO_MODE = 1, > > since DW DMAC will wait for the channel FIFO contents to be either > > half-full or half-empty depending on having the destination or the source > > transfers. Such latencies might be dangerous in case if the DMA transfers > > are expected to be performed from/to a slave device. Since normally > > peripheral devices keep data in internal FIFOs, any latency at some > > critical moment may cause one being overflown and consequently losing > > data. This especially concerns a case when either a peripheral device is > > relatively fast or the DW DMAC engine is relatively slow with respect to > > the incoming data pace. > > > > In order to solve problems, which might be caused by the latencies > > described above, let's enable the FIFO half-full/half-empty "FIFO > > readiness" criterion only for DMA transfers with no slave device involved. > > > Thanks to the commit ???????????? ("dmaengine: dw: Initialize channel > > See below. > > > before each transfer") we can freely do that in the generic > > dw_dma_initialize_chan() method. > > Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> > Thanks! > > > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> > > > > --- > > > > Note the DMA-engine repository git.infradead.org/users/vkoul/slave-dma.git > > isn't accessible. So I couldn't find out the Andy' commit hash to use it in > > the log. > > It's dmaengine.git on git.kernel.org. Ah, thanks! I've just found out that the repo address has been changed. But I've also scanned the "next" branch of the repo: https://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine.git Your commit isn't there. Am I missing something? -Sergey > > > --- > > drivers/dma/dw/dw.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/dma/dw/dw.c b/drivers/dma/dw/dw.c > > index 7a085b3c1854..d9810980920a 100644 > > --- a/drivers/dma/dw/dw.c > > +++ b/drivers/dma/dw/dw.c > > @@ -14,7 +14,7 @@ > > static void dw_dma_initialize_chan(struct dw_dma_chan *dwc) > > { > > struct dw_dma *dw = to_dw_dma(dwc->chan.device); > > - u32 cfghi = DWC_CFGH_FIFO_MODE; > > + u32 cfghi = is_slave_direction(dwc->direction) ? 0 : DWC_CFGH_FIFO_MODE; > > u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority); > > bool hs_polarity = dwc->dws.hs_polarity; > > > > -- > > 2.27.0 > > > > -- > With Best Regards, > Andy Shevchenko > >
On Thu, Jul 30, 2020 at 07:31:22PM +0300, Andy Shevchenko wrote: > On Thu, Jul 30, 2020 at 06:45:44PM +0300, Serge Semin wrote: > > According to the DW DMA controller Databook (page 40 "3.5 Memory > > Which version of it? 2.18b > > > Peripherals") memory peripherals don't have handshaking interface > > connected to the controller, therefore they can never be a flow > > controller. Since the CTLx.SRC_MSIZE and CTLx.DEST_MSIZE are > > properties valid only for peripherals with a handshaking > > interface, we can freely zero these fields out if the memory peripheral > > is selected to be the source or the destination of the DMA transfers. > > > > Note according to the databook, length of burst transfers to memory is > > always equal to the number of data items available in a channel FIFO or > > data items required to complete the block transfer, whichever is smaller; > > length of burst transfers from memory is always equal to the space > > available in a channel FIFO or number of data items required to complete > > the block transfer, whichever is smaller. > > But does it really matter if you program there something or not? For memory peripherals it doesn't. But it's better to remove the redundant settings for consistency with the doc and to get rid of the unneeded stack-variable declaration. -Sergey > > -- > With Best Regards, > Andy Shevchenko > >
On Thu, Jul 30, 2020 at 06:45:45PM +0300, Serge Semin wrote: > DW DMA IP-core provides a way to synthesize the DMA controller with > channels having different parameters like maximum burst-length, > multi-block support, maximum data width, etc. Those parameters both > explicitly and implicitly affect the channels performance. Since DMA slave > devices might be very demanding to the DMA performance, let's provide a > functionality for the slaves to be assigned with DW DMA channels, which > performance according to the platform engineer fulfill their requirements. > After this patch is applied it can be done by passing the mask of suitable > DMA-channels either directly in the dw_dma_slave structure instance or as > a fifth cell of the DMA DT-property. If mask is zero or not provided, then > there is no limitation on the channels allocation. > > For instance Baikal-T1 SoC is equipped with a DW DMAC engine, which first > two channels are synthesized with max burst length of 16, while the rest > of the channels have been created with max-burst-len=4. It would seem that > the first two channels must be faster than the others and should be more > preferable for the time-critical DMA slave devices. In practice it turned > out that the situation is quite the opposite. The channels with > max-burst-len=4 demonstrated a better performance than the channels with > max-burst-len=16 even when they both had been initialized with the same > settings. The performance drop of the first two DMA-channels made them > unsuitable for the DW APB SSI slave device. No matter what settings they > are configured with, full-duplex SPI transfers occasionally experience the > Rx FIFO overflow. It means that the DMA-engine doesn't keep up with > incoming data pace even though the SPI-bus is enabled with speed of 25MHz > while the DW DMA controller is clocked with 50MHz signal. There is no such > problem has been noticed for the channels synthesized with > max-burst-len=4. ... > + if (dws->channels && !(dws->channels & dwc->mask)) You can drop the first check if... > + return false; ... > + if (dma_spec->args_count >= 4) > + slave.channels = dma_spec->args[3]; ...you apply sane default here or somewhere else. ... > + fls(slave.channels) > dw->pdata->nr_channels)) Does it really make sense? I think it can also be simplified to faster op, i.e. BIT(nr_channels) < slave.channels (but check for off-by-one errors) ... > + * @channels: mask of the channels permitted for allocation (zero > + * value means any) Perhaps on one line?
On Thu, Jul 30, 2020 at 07:31:54PM +0300, Serge Semin wrote: > On Thu, Jul 30, 2020 at 07:24:28PM +0300, Andy Shevchenko wrote: > > On Thu, Jul 30, 2020 at 06:45:42PM +0300, Serge Semin wrote: ... > > > Thanks to the commit ???????????? ("dmaengine: dw: Initialize channel ... > > > Note the DMA-engine repository git.infradead.org/users/vkoul/slave-dma.git > > > isn't accessible. So I couldn't find out the Andy' commit hash to use it in > > > the log. > > > It's dmaengine.git on git.kernel.org. > > Ah, thanks! I've just found out that the repo address has been changed. But I've > also scanned the "next" branch of the repo: > https://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine.git > > Your commit isn't there. Am I missing something? It's a fix. It went to upstream branch (don't remember its name by heart in Vinod's repo).
On Thu, Jul 30, 2020 at 07:41:46PM +0300, Andy Shevchenko wrote: > On Thu, Jul 30, 2020 at 06:45:45PM +0300, Serge Semin wrote: > > DW DMA IP-core provides a way to synthesize the DMA controller with > > channels having different parameters like maximum burst-length, > > multi-block support, maximum data width, etc. Those parameters both > > explicitly and implicitly affect the channels performance. Since DMA slave > > devices might be very demanding to the DMA performance, let's provide a > > functionality for the slaves to be assigned with DW DMA channels, which > > performance according to the platform engineer fulfill their requirements. > > After this patch is applied it can be done by passing the mask of suitable > > DMA-channels either directly in the dw_dma_slave structure instance or as > > a fifth cell of the DMA DT-property. If mask is zero or not provided, then > > there is no limitation on the channels allocation. > > > > For instance Baikal-T1 SoC is equipped with a DW DMAC engine, which first > > two channels are synthesized with max burst length of 16, while the rest > > of the channels have been created with max-burst-len=4. It would seem that > > the first two channels must be faster than the others and should be more > > preferable for the time-critical DMA slave devices. In practice it turned > > out that the situation is quite the opposite. The channels with > > max-burst-len=4 demonstrated a better performance than the channels with > > max-burst-len=16 even when they both had been initialized with the same > > settings. The performance drop of the first two DMA-channels made them > > unsuitable for the DW APB SSI slave device. No matter what settings they > > are configured with, full-duplex SPI transfers occasionally experience the > > Rx FIFO overflow. It means that the DMA-engine doesn't keep up with > > incoming data pace even though the SPI-bus is enabled with speed of 25MHz > > while the DW DMA controller is clocked with 50MHz signal. There is no such > > problem has been noticed for the channels synthesized with > > max-burst-len=4. > > ... > > > + if (dws->channels && !(dws->channels & dwc->mask)) > > You can drop the first check if... See below. > > > + return false; > > ... > > > + if (dma_spec->args_count >= 4) > > + slave.channels = dma_spec->args[3]; > > ...you apply sane default here or somewhere else. Alas I can't because dw_dma_slave structure is defined all over the kernel drivers/spi/spi-dw-dma.c drivers/spi/spi-pxa2xx-pci.c drivers/tty/serial/8250/8250_lpss.c These devices aren't always placed on the OF-based platforms. In that case the corresponding DMA-channels won't be requested by means of the dw_dma_of_xlate() method. So we have to preserve a default behavior if dws->channels is zero. > > ... > > > + fls(slave.channels) > dw->pdata->nr_channels)) > > Does it really make sense? It does to prevent the clients to specify an invalid channels mask, which can't have bits set higher than the number of channels the engine supports. > > I think it can also be simplified to faster op, i.e. > BIT(nr_channels) < slave.channels > (but check for off-by-one errors) Makes sense. Thanks. I'll replace it with the next statement: slave.channels >= BIT(dw->pdata->nr_channels) > > ... > > > + * @channels: mask of the channels permitted for allocation (zero > > + * value means any) > > Perhaps on one line? I don't really care. If you insist on that, I'll make it a single line, but it will be over 80 columns. 85 to be exact. -Sergey > > -- > With Best Regards, > Andy Shevchenko > >
On Thu, Jul 30, 2020 at 07:47:03PM +0300, Andy Shevchenko wrote: > On Thu, Jul 30, 2020 at 07:31:54PM +0300, Serge Semin wrote: > > On Thu, Jul 30, 2020 at 07:24:28PM +0300, Andy Shevchenko wrote: > > > On Thu, Jul 30, 2020 at 06:45:42PM +0300, Serge Semin wrote: > > ... > > > > > Thanks to the commit ???????????? ("dmaengine: dw: Initialize channel > > ... > > > > > Note the DMA-engine repository git.infradead.org/users/vkoul/slave-dma.git > > > > isn't accessible. So I couldn't find out the Andy' commit hash to use it in > > > > the log. > > > > > It's dmaengine.git on git.kernel.org. > > > > Ah, thanks! I've just found out that the repo address has been changed. But I've > > also scanned the "next" branch of the repo: > > https://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine.git > > > > Your commit isn't there. Am I missing something? > > It's a fix. It went to upstream branch (don't remember its name by heart in > Vinod's repo). Right. Found it. Thanks. -Sergey > > -- > With Best Regards, > Andy Shevchenko > >
On 30-07-20, 20:13, Serge Semin wrote: > On Thu, Jul 30, 2020 at 07:47:03PM +0300, Andy Shevchenko wrote: > > On Thu, Jul 30, 2020 at 07:31:54PM +0300, Serge Semin wrote: > > > On Thu, Jul 30, 2020 at 07:24:28PM +0300, Andy Shevchenko wrote: > > > > On Thu, Jul 30, 2020 at 06:45:42PM +0300, Serge Semin wrote: > > > > ... > > > > > > > Thanks to the commit ???????????? ("dmaengine: dw: Initialize channel > > > > ... > > > > > > > Note the DMA-engine repository git.infradead.org/users/vkoul/slave-dma.git > > > > > isn't accessible. So I couldn't find out the Andy' commit hash to use it in > > > > > the log. Yeah I moved tree to k.org after disk issue with infradead, change patch was on dmaengine ML > > > > It's dmaengine.git on git.kernel.org. > > > > > > Ah, thanks! I've just found out that the repo address has been changed. But I've > > > also scanned the "next" branch of the repo: > > > https://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine.git > > > > > > Your commit isn't there. Am I missing something? > > > > > It's a fix. It went to upstream branch (don't remember its name by heart in > > Vinod's repo). Yes it is Linus's tree now and in dmaengine you can find in fixes branch https://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine.git/commit/?h=fixes&id=99ba8b9b0d9780e9937eb1d488d120e9e5c2533d > > Right. Found it. Thanks. > > -Sergey > > > > > -- > > With Best Regards, > > Andy Shevchenko > > > >
On Fri, Jul 31, 2020 at 10:22:54PM +0530, Vinod Koul wrote: > On 30-07-20, 20:13, Serge Semin wrote: > > On Thu, Jul 30, 2020 at 07:47:03PM +0300, Andy Shevchenko wrote: > > > On Thu, Jul 30, 2020 at 07:31:54PM +0300, Serge Semin wrote: > > > > On Thu, Jul 30, 2020 at 07:24:28PM +0300, Andy Shevchenko wrote: > > > > > On Thu, Jul 30, 2020 at 06:45:42PM +0300, Serge Semin wrote: > > > > > > ... > > > > > > > > > Thanks to the commit ???????????? ("dmaengine: dw: Initialize channel > > > > > > ... > > > > > > > > > Note the DMA-engine repository git.infradead.org/users/vkoul/slave-dma.git > > > > > > isn't accessible. So I couldn't find out the Andy' commit hash to use it in > > > > > > the log. > > Yeah I moved tree to k.org after disk issue with infradead, change patch > was on dmaengine ML > > > > > > It's dmaengine.git on git.kernel.org. > > > > > > > > Ah, thanks! I've just found out that the repo address has been changed. But I've > > > > also scanned the "next" branch of the repo: > > > > https://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine.git > > > > > > > > Your commit isn't there. Am I missing something? > > > > > > > > It's a fix. It went to upstream branch (don't remember its name by heart in > > > Vinod's repo). > > Yes it is Linus's tree now and in dmaengine you can find in fixes branch > > https://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine.git/commit/?h=fixes&id=99ba8b9b0d9780e9937eb1d488d120e9e5c2533d Thanks for pointing out to the commit. I'll add the hash to the patch log and resend the series shortly. -Sergey > > > > > Right. Found it. Thanks. > > > > -Sergey > > > > > > > > -- > > > With Best Regards, > > > Andy Shevchenko > > > > > > > > -- > ~Vinod
After a lot of tests and thorough DW DMAC databook studying we've discovered that the driver can be optimized especially when it comes to working with non-memory peripherals. First of all we've found out that since each DW DMAC channel can be synthesized with different parameters, then even when two of them are configured to perform the same DMA transactions they may execute them with different performance. Since some DMA client devices might be sensitive to such important parameter as performance, then it is a good idea to let them request only suitable DMA channels. In this patchset we introduce a functionality, which makes it possible by passing the DMA channels mask either over the "dmas" DT property or in the dw_dma_slave platform data descriptor. Secondly FIFO-mode of the "FIFO readiness" criterion is more suitable for the pure memory DMA transfers, since it minimizes the system bus utilization, but causes some performance drop. When it comes to working with non-memory peripherals the DMA engine performance comes to the first place. Since normally DMA client devices keep data in internal FIFOs, any latency at some critical moment may cause a FIFO being overflown and consequently losing data. So in order to minimize a chance of the DW DMAC internal FIFO being a bottle neck during the DMA transfers to and from non-memory peripherals we propose not to use FIFO-mode for them. Thirdly it has been discovered that using a DMA transaction length is redundant when calculating the destination transfer width for the dev-to-mem DMA communications. That shall increase performance of the DMA transfers with unaligned data length. Finally there is a small optimization in the burst length setting. In particular we've found out, that according to the DW DMAC databoot it's pointless to set one for the memory peripherals since they don't have handshaking interface connected to the DMA controller. So we suggest to just ignore the burst length config when it comes to setting the memory peripherals up. Note this patchset is supposed to be applied on top of the series: Link: https://lore.kernel.org/dmaengine/20200723005848.31907-1-Sergey.Semin@baikalelectronics.ru Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> Cc: Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru> Cc: Peter Ujfalusi <peter.ujfalusi@ti.com> Cc: Andy Shevchenko <andy.shevchenko@gmail.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: dmaengine@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Serge Semin (5): dt-bindings: dma: dw: Add optional DMA-channels mask cell support dmaengine: dw: Activate FIFO-mode for memory peripherals only dmaengine: dw: Discard dlen from the dev-to-mem xfer width calculation dmaengine: dw: Ignore burst setting for memory peripherals dmaengine: dw: Add DMA-channels mask cell support .../devicetree/bindings/dma/snps,dma-spear1340.yaml | 7 +++++-- drivers/dma/dw/core.c | 6 +++++- drivers/dma/dw/dw.c | 7 +++---- drivers/dma/dw/idma32.c | 5 ++--- drivers/dma/dw/of.c | 7 +++++-- include/linux/platform_data/dma-dw.h | 3 +++ 6 files changed, 23 insertions(+), 12 deletions(-)