From patchwork Wed Jul 8 17:50:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniele Alessandrelli X-Patchwork-Id: 1325403 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4B26Kc1rHpz9sRW for ; Thu, 9 Jul 2020 03:50:44 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726174AbgGHRun (ORCPT ); Wed, 8 Jul 2020 13:50:43 -0400 Received: from mga05.intel.com ([192.55.52.43]:31319 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726100AbgGHRum (ORCPT ); Wed, 8 Jul 2020 13:50:42 -0400 IronPort-SDR: WllNX5RC/mK+MeIPawjzjZ9DPX0WLlE395OKgm9AwNumLKy8K+6iENrTuwI2uaXGWlhdJhkgFP fiHAa3KbFj4Q== X-IronPort-AV: E=McAfee;i="6000,8403,9676"; a="232753512" X-IronPort-AV: E=Sophos;i="5.75,328,1589266800"; d="scan'208";a="232753512" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2020 10:50:42 -0700 IronPort-SDR: VZ9GFeLDbkCynhnB5XBEGm94Mvjvl1gYqGh27J3Q+nnaOJKZVqiFBxTOrYUGUBjM4C+CELdZNk Qwm2XnLrr86w== X-IronPort-AV: E=Sophos;i="5.75,328,1589266800"; d="scan'208";a="457591788" Received: from sgyanama-mobl1.gar.corp.intel.com (HELO dalessan-mobl1.ir.intel.com) ([10.252.5.67]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2020 10:50:37 -0700 From: Daniele Alessandrelli To: linux-arm-kernel@lists.infradead.org, SoC Team , Rob Herring , Jassi Brar , Arnd Bergmann , Olof Johansson Cc: devicetree@vger.kernel.org, Catalin Marinas , linux-kernel@vger.kernel.org, Dinh Nguyen , Paul Murphy , Will Deacon , Daniele Alessandrelli Subject: [PATCH v2 0/5] Add initial Keem Bay SoC / Board support Date: Wed, 8 Jul 2020 18:50:15 +0100 Message-Id: <20200708175020.194436-1-daniele.alessandrelli@linux.intel.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi, This patch-set adds initial support for a new Intel Movidius SoC code-named Keem Bay. The SoC couples an ARM Cortex A53 CPU with an Intel Movidius VPU. This initial patch-set enables only the minimal set of components required to make the Keem Bay EVM board boot into initramfs. Changes from v1 to v2: * Moved keembay-scmi-mailbox driver to a separate patchset * Removed Keem Bay SCMI mailbox and SCMI node from Keem Bay SoC device tree Regards, Daniele Daniele Alessandrelli (5): arm64: Add config for Keem Bay SoC dt-bindings: arm: Add Keem Bay bindings MAINTAINERS: Add maintainers for Keem Bay SoC arm64: dts: keembay: Add device tree for Keem Bay SoC arm64: dts: keembay: Add device tree for Keem Bay EVM board .../devicetree/bindings/arm/keembay.yaml | 19 ++ MAINTAINERS | 10 + arch/arm64/Kconfig.platforms | 5 + arch/arm64/boot/dts/intel/Makefile | 1 + arch/arm64/boot/dts/intel/keembay-evm.dts | 39 ++++ arch/arm64/boot/dts/intel/keembay-soc.dtsi | 125 ++++++++++++ include/dt-bindings/clock/keembay-clocks.h | 188 ++++++++++++++++++ include/dt-bindings/power/keembay-power.h | 19 ++ 8 files changed, 406 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/keembay.yaml create mode 100644 arch/arm64/boot/dts/intel/keembay-evm.dts create mode 100644 arch/arm64/boot/dts/intel/keembay-soc.dtsi create mode 100644 include/dt-bindings/clock/keembay-clocks.h create mode 100644 include/dt-bindings/power/keembay-power.h