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dkim=none (message not signed) header.d=none;dabbelt.com; dmarc=none action=none header.from=wdc.com; Received: from MN2PR04MB6207.namprd04.prod.outlook.com (2603:10b6:208:de::32) by MN2PR04MB5599.namprd04.prod.outlook.com (2603:10b6:208:fe::26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3131.21; Sat, 27 Jun 2020 16:20:38 +0000 Received: from MN2PR04MB6207.namprd04.prod.outlook.com ([fe80::e0ef:7fce:ff0d:f580]) by MN2PR04MB6207.namprd04.prod.outlook.com ([fe80::e0ef:7fce:ff0d:f580%7]) with mapi id 15.20.3131.026; Sat, 27 Jun 2020 16:20:38 +0000 From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Albert Ou , Rob Herring , Daniel Lezcano , Thomas Gleixner Cc: Damien Le Moal , Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: [PATCH v2 0/5] Dedicated CLINT timer driver Date: Sat, 27 Jun 2020 21:49:52 +0530 Message-Id: <20200627161957.134376-1-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 X-ClientProxiedBy: MAXPR0101CA0029.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:d::15) To MN2PR04MB6207.namprd04.prod.outlook.com (2603:10b6:208:de::32) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (42.109.128.251) by MAXPR0101CA0029.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:d::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3131.21 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: 944vChs3SsWKH1nhtN1yviC5aIHdgfeKVciIa+yJrNKgR8hcZr0CD35uLpMsmPBYpQXbv40MyhirapSnzoOsArhKNJSkgKIkUj0evpCK+GgukdNpXh9cbYv130kw+hEz+tP3R3We+hdAzhPB0E3b8frbHr8WS8N891iB7RerYGb7TwK1MisWOqwS9oo9/H87DaYV4tT2otuTyQzFAWhdOoXq3nITcXzfVYwlyR6MTNPN1U0brjEmOpIj0jiXzOhGV7k2re8DdCgAJG6Fmo9w7Sae6mM7gRcfoFLWEb7BZV4FTD2sQhyeEa0NP1htHWGFSyGjiYQt/yQDk8yHQ5BbsGGBvXnyUuX2j5ZpUvVtjWYLv/caAjs13tTj5Mu8t3PVzPLciNXSdZHKMP9JRbc0w7idGviZqkMNw8CxAcOph29it4A28HBwuqLsoaEADaM3FSgVFt9mxosIAEtid1B1fMzSXfuCTb7Ov9CSqZot0gEIdA4VxRhoB/wTOchc3JqB X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1fa3b50b-a110-4601-2d76-08d81ab606b8 X-MS-Exchange-CrossTenant-AuthSource: MN2PR04MB6207.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jun 2020 16:20:37.8055 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: qKr5/RfX2zKBv1UIr7x2UcmjgLoTht/20X8NE4ISQw6Kq49UZNbUJcBEJahxZDjubwGcFvOjiTowNf7+cAoCzA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB5599 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The current RISC-V timer driver is convoluted and implements two distinct timers: 1. S-mode timer: This is for Linux RISC-V S-mode with MMU. The clocksource is implemented using TIME CSR and clockevent device is implemented using SBI Timer calls. 2. M-mode timer: This is for Linux RISC-V M-mode without MMU. The clocksource is implemented using CLINT MMIO time register and clockevent device is implemented using CLINT MMIO timecmp registers. This patchset removes clint related code from RISC-V timer driver and arch/riscv directory. Instead, the series adds a dedicated MMIO based CLINT driver under drivers/clocksource directory which can be used by Linux RISC-V M-mode (i.e NoMMU Linux RISC-V). The patchset is based up Linux-5.8-rc2 and can be found at riscv_clint_v2 branch of: https://github.com/avpatel/linux.git This series is tested on: 1. QEMU RV64 virt machine using Linux RISC-V S-mode 2. QEMU RV32 virt machine using Linux RISC-V S-mode 3. QEMU RV64 virt machine using Linux RISC-V M-mode (i.e. NoMMU) Changes since v1: - Rebased series on Linux-5.8-rc2 - Added pr_warn() for case where ipi_ops not available in PATCH1 - Updated ipi_inject() prototype to use "struct cpumask *" in PATCH1 - Updated CLINT_TIMER kconfig option to depend on RISCV_M_MODE in PATCH4 - Added riscv,clint0 compatible string in DT bindings document Anup Patel (5): RISC-V: Add mechanism to provide custom IPI operations RISC-V: Remove CLINT related code clocksource/drivers/timer-riscv: Remove MMIO related stuff clocksource/drivers: Add CLINT timer driver dt-bindings: timer: Add CLINT bindings .../bindings/timer/sifive,clint.txt | 34 +++ arch/riscv/Kconfig | 2 +- arch/riscv/include/asm/clint.h | 39 --- arch/riscv/include/asm/smp.h | 11 + arch/riscv/include/asm/timex.h | 28 +-- arch/riscv/kernel/Makefile | 2 +- arch/riscv/kernel/clint.c | 44 ---- arch/riscv/kernel/sbi.c | 14 ++ arch/riscv/kernel/setup.c | 2 - arch/riscv/kernel/smp.c | 44 ++-- arch/riscv/kernel/smpboot.c | 4 +- drivers/clocksource/Kconfig | 12 +- drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-clint.c | 229 ++++++++++++++++++ drivers/clocksource/timer-riscv.c | 17 +- include/linux/cpuhotplug.h | 1 + 16 files changed, 337 insertions(+), 147 deletions(-) create mode 100644 Documentation/devicetree/bindings/timer/sifive,clint.txt delete mode 100644 arch/riscv/include/asm/clint.h delete mode 100644 arch/riscv/kernel/clint.c create mode 100644 drivers/clocksource/timer-clint.c