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[PATCH/RFC,0/5] ravb: Add support for explicit internal clock delay configuration

Message ID 20200619191554.24942-1-geert+renesas@glider.be
Headers show
Series ravb: Add support for explicit internal clock delay configuration | expand

Message

Geert Uytterhoeven June 19, 2020, 7:15 p.m. UTC
Hi all,

Some Renesas EtherAVB variants support internal clock delay
configuration, which can add larger delays than the delays that are
typically supported by the PHY (using an "rgmii-*id" PHY mode, and/or
"[rt]xc-skew-ps" properties).

Historically, the EtherAVB driver configured these delays based on the
"rgmii-*id" PHY mode.  This caused issues with PHY drivers that
implement PHY internal delays properly[1].  Hence a backwards-compatible
workaround was added by masking the PHY mode[2].

This RFC patch series implements the next step of the plan outlined in
[3], and adds proper support for explicit configuration of the MAC
internal clock delays using new "renesas,[rt]xc-delay-ps" properties.
If none of these properties is present, the driver falls back to the old
handling.

The series consists of 4 parts:
  1. DT binding update documenting the new properties,
  2. A preparatory improvement,
  3. Driver update implementing support for the new properties,
  4. DT updates, one for R-Car Gen3 and RZ/G2 SoC families each.

Note that patches 4 and 5 depend on patch 3, and must not be applied
before that dependency has hit upstream.

Impacted, tested:
  - Salvator-X(S) with R-Car H3 ES1.0 and ES2.0, M3-W, and M3-N.

Not impacted, tested:
  - Ebisu with R-Car E3.

Impacted, not tested:
  - Salvator-X(S) with other SoC variants,
  - ULCB with R-Car H3/M3-W/M3-N variants,
  - V3MSK and Eagle with R-Car V3M,
  - Draak with R-Car V3H,
  - HiHope RZ/G2[MN] with RZ/G2M or RZ/G2N.

Thanks for your comments!

References:
  [1] Commit bcf3440c6dd78bfe ("net: phy: micrel: add phy-mode support
      for the KSZ9031 PHY")
  [2] Commit 9b23203c32ee02cd ("ravb: Mask PHY mode to avoid inserting
      delays twice").
      https://lore.kernel.org/r/20200529122540.31368-1-geert+renesas@glider.be/
  [3] https://lore.kernel.org/r/CAMuHMdU+MR-2tr3-pH55G0GqPG9HwH3XUd=8HZxprFDMGQeWUw@mail.gmail.com/

Geert Uytterhoeven (5):
  dt-bindings: net: renesas,ravb: Document internal clock delay
    properties
  ravb: Split delay handling in parsing and applying
  ravb: Add support for explicit internal clock delay configuration
  arm64: dts: renesas: rcar-gen3: Convert EtherAVB to explicit delay
    handling
  arm64: dts: renesas: rzg2: Convert EtherAVB to explicit delay handling

 .../devicetree/bindings/net/renesas,ravb.txt  | 29 ++++++-----
 .../boot/dts/renesas/hihope-rzg2-ex.dtsi      |  2 +-
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi     |  2 +
 arch/arm64/boot/dts/renesas/r8a774b1.dtsi     |  2 +
 arch/arm64/boot/dts/renesas/r8a774c0.dtsi     |  1 +
 arch/arm64/boot/dts/renesas/r8a77951.dtsi     |  2 +
 arch/arm64/boot/dts/renesas/r8a77960.dtsi     |  2 +
 arch/arm64/boot/dts/renesas/r8a77961.dtsi     |  2 +
 arch/arm64/boot/dts/renesas/r8a77965.dtsi     |  2 +
 .../arm64/boot/dts/renesas/r8a77970-eagle.dts |  3 +-
 .../arm64/boot/dts/renesas/r8a77970-v3msk.dts |  3 +-
 arch/arm64/boot/dts/renesas/r8a77970.dtsi     |  2 +
 arch/arm64/boot/dts/renesas/r8a77980.dtsi     |  2 +
 arch/arm64/boot/dts/renesas/r8a77990.dtsi     |  1 +
 arch/arm64/boot/dts/renesas/r8a77995.dtsi     |  1 +
 .../boot/dts/renesas/salvator-common.dtsi     |  2 +-
 arch/arm64/boot/dts/renesas/ulcb.dtsi         |  2 +-
 drivers/net/ethernet/renesas/ravb.h           |  5 +-
 drivers/net/ethernet/renesas/ravb_main.c      | 52 ++++++++++++++-----
 19 files changed, 86 insertions(+), 31 deletions(-)

Comments

Sergei Shtylyov June 20, 2020, 6:34 p.m. UTC | #1
On 06/19/2020 10:15 PM, Geert Uytterhoeven wrote:

> Currently, full delay handling is done in both the probe and resume
> paths.  Split it in two parts, so the resume path doesn't have to redo
> the parsing part over and over again.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

[...]

MBR, Sergei
Sergei Shtylyov June 20, 2020, 7:03 p.m. UTC | #2
On 06/19/2020 10:15 PM, Geert Uytterhoeven wrote:

> Some EtherAVB variants support internal clock delay configuration, which
> can add larger delays than the delays that are typically supported by
> the PHY (using an "rgmii-*id" PHY mode, and/or "[rt]xc-skew-ps"
> properties).
> 
> Historically, the EtherAVB driver configured these delays based on the
> "rgmii-*id" PHY mode.  This caused issues with PHY drivers that
> implement PHY internal delays properly[1].  Hence a backwards-compatible
> workaround was added by masking the PHY mode[2].
> 
> Add proper support for explicit configuration of the MAC internal clock
> delays using the new "renesas,[rt]xc-delay-ps" properties.
> Fall back to the old handling if none of these properties is present.
> 
> [1] Commit bcf3440c6dd78bfe ("net: phy: micrel: add phy-mode support for
>     the KSZ9031 PHY")
> [2] Commit 9b23203c32ee02cd ("ravb: Mask PHY mode to avoid inserting
>     delays twice").
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

> ---
>  drivers/net/ethernet/renesas/ravb.h      |  1 +
>  drivers/net/ethernet/renesas/ravb_main.c | 35 ++++++++++++++++++------
>  2 files changed, 27 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h
> index e5ca12ce93c730a9..7453b17a37a2c8d0 100644
> --- a/drivers/net/ethernet/renesas/ravb.h
> +++ b/drivers/net/ethernet/renesas/ravb.h
> @@ -1038,6 +1038,7 @@ struct ravb_private {
>  	unsigned wol_enabled:1;
>  	unsigned rxcidm:1;		/* RX Clock Internal Delay Mode */
>  	unsigned txcidm:1;		/* TX Clock Internal Delay Mode */
> +	unsigned rgmii_override:1;	/* Deprecated rgmii-*id behavior */
>  	int num_tx_desc;		/* TX descriptors per packet */
>  };
>  
> diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
> index f326234d1940f43e..0582846bec7726b6 100644
> --- a/drivers/net/ethernet/renesas/ravb_main.c
> +++ b/drivers/net/ethernet/renesas/ravb_main.c
[...]
> @@ -1967,20 +1963,41 @@ static const struct soc_device_attribute ravb_delay_mode_quirk_match[] = {
>  };
>  
>  /* Set tx and rx clock internal delay modes */
> -static void ravb_parse_delay_mode(struct net_device *ndev)
> +static void ravb_parse_delay_mode(struct device_node *np, struct net_device *ndev)
>  {
>  	struct ravb_private *priv = netdev_priv(ndev);
> +	bool explicit_delay = false;
> +	u32 delay;
> +
> +	if (!of_property_read_u32(np, "renesas,rxc-delay-ps", &delay)) {
> +		/* Valid values are 0 and 1800, according to DT bindings */
> +		priv->rxcidm = !!delay;
> +		explicit_delay = true;
> +	}
> +	if (!of_property_read_u32(np, "renesas,txc-delay-ps", &delay)) {
> +		/* Valid values are 0 and 2000, according to DT bindings */
> +		priv->txcidm = !!delay;
> +		explicit_delay = true;
> +	}
>  
> +	if (explicit_delay)
> +		return;
> +
> +	/* Fall back to legacy rgmii-*id behavior */
>  	if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
> -	    priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID)
> +	    priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) {
>  		priv->rxcidm = true;
> +		priv->rgmii_override = true;

   Mhm, these fields are not bool...

> +	}
>  
>  	if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
>  	    priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) {
>  		if (!WARN(soc_device_match(ravb_delay_mode_quirk_match),
>  			  "phy-mode %s requires TX clock internal delay mode which is not supported by this hardware revision. Please update device tree",
> -			  phy_modes(priv->phy_interface)))
> +			  phy_modes(priv->phy_interface))) {
>  			priv->txcidm = true;
> +			priv->rgmii_override = true;

    Same here...

[...]

MBR, Sergei