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[v3,00/13] MMP2 Clock Updates (GPU, Audio, Power Islands)

Message ID 20200519224151.2074597-1-lkundrak@v3.sk
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Series MMP2 Clock Updates (GPU, Audio, Power Islands) | expand

Message

Lubomir Rintel May 19, 2020, 10:41 p.m. UTC
Hi,

please consider applying this patch set. It contains patches that were
previously sent in two separate series ("clk: mmp2: Enable Audio and GPU
on MMP2 and MMP3" and "MMP2 Audio clock controller driver") but given
there are some dependencies, it seems more practical to merge them into
one.

The ultimate goal it so make GPU and Audio clocks work on MMP2 and
MMP3-based machines.

This patch set aims to address issues pointed out in review of v1 of the
clock controller set.

Ther first few patches add the clocks for the audio block, setting a few
things beforehands:

  [01/13] clk: mmp: frac: Do not lose last 4 digits of precision
  [02/13] clk: mmp: frac: Allow setting bits other than the
  [03/13] dt-bindings: marvell,mmp2: Add clock id for the I2S
  [04/13] dt-bindings: marvell,mmp2: Add clock id for the Audio
  [05/13] clk: mmp2: Move thermal register defines up a bit
  [06/13] clk: mmp2: Rename mmp2_pll_init() to
  [07/13] clk: mmp2: Add the I2S clocks
  [08/13] clk: mmp2: Add the audio clock

Then the support for controlling the power to Audio, GPU and (on a MMP3)
Camera blocks is added. The power is controlled by the same hardware
(the PMUs) as one that drives the clocks:

  [09/13] dt-bindings: clock: Make marvell,mmp2-clock a power
  [10/13] dt-bindings: marvell,mmp2: Add ids for the power
  [11/13] clk: mmp2: Add support for power islands

Finally a driver for the clocks used by I2S is added. The controller is
separate from a PMUs and lives in the audio block along with a pair of
I2S controllers:

  [12/13] dt-bindings: clock: Add Marvell MMP Audio Clock
  [13/13] clk: mmp2: Add audio clock controller driver

Tested the GPU and Audio on an OLPC XO-1.75 laptop (MMP2).

Thanks,
Lubo

Comments

Stephen Boyd May 28, 2020, 1:01 a.m. UTC | #1
Quoting Lubomir Rintel (2020-05-19 15:41:39)
> While calculating the output rate of a fractional divider clock, the
> value is divided and multipled by 10000, discarding the least
> significant digits -- presumably to fit the intermediate value within 32
> bits.
> 
> The precision we're losing is, however, not insignificant for things like
> I2S clock. Maybe also elsewhere, now that since commit ea56ad60260e ("clk:
> mmp2: Stop pretending PLL outputs are constant") the parent rates are more
> precise and no longer rounded to 10000s.
> 
> Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
> ---

Applied to clk-next
Stephen Boyd May 28, 2020, 1:01 a.m. UTC | #2
Quoting Lubomir Rintel (2020-05-19 15:41:40)
> For the I2S fractional clocks, there are more bits that need to be set
> for the clock to run. Their actual meaning is unknown.
> 
> Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
> ---

Applied to clk-next
Stephen Boyd May 28, 2020, 1:01 a.m. UTC | #3
Quoting Lubomir Rintel (2020-05-19 15:41:43)
> A trivial change to keep the sorting sane. The APBC registers are happier
> when they are grouped together, instead of mixed with the APMU ones.
> 
> Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
> ---

Applied to clk-next
Stephen Boyd May 28, 2020, 1:01 a.m. UTC | #4
Quoting Lubomir Rintel (2020-05-19 15:41:44)
> This is a trivial rename for a routine that registers more clock sources
> than the PLLs -- there's also a XO.
> 
> Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
> ---

Applied to clk-next
Stephen Boyd May 28, 2020, 1:01 a.m. UTC | #5
Quoting Lubomir Rintel (2020-05-19 15:41:45)
> A pair of fractional clock sources for PLLs and gates.
> 
> Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
> 
> ---

Applied to clk-next
Stephen Boyd May 28, 2020, 1:01 a.m. UTC | #6
Quoting Lubomir Rintel (2020-05-19 15:41:46)
> This clocks the Audio block.
> 
> Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
> ---

Applied to clk-next
Stephen Boyd May 28, 2020, 1:01 a.m. UTC | #7
Quoting Lubomir Rintel (2020-05-19 15:41:49)
> Apart from the clocks and resets, the PMU hardware also controls power
> to peripherals that are on separate power islands. On MMP2, that's the
> GC860 GPU and the SSPA audio interface, while on MMP3 also the camera
> interface is on a separate island, along with the pair of GC2000 and GC300
> GPUs and the SSPA.
> 
> Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
> 
> ---

Applied to clk-next
Stephen Boyd May 28, 2020, 1:01 a.m. UTC | #8
Quoting Lubomir Rintel (2020-05-19 15:41:51)
> This is a driver for a block that generates master and bit clocks for
> the I2S interface. It's separate from the PMUs that generate clocks for
> the peripherals.
> 
> Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
> 
> ---

Applied to clk-next