mbox series

[v2,0/7] Allwinner H6 DMA support

Message ID 20190525163819.21055-1-peron.clem@gmail.com
Headers show
Series Allwinner H6 DMA support | expand

Message

Clément Péron May 25, 2019, 4:38 p.m. UTC 
Hi,

This series has been first proposed by Jernej Skrabec[1].
As this series is mandatory for SPDIF/I2S support and because he is
busy on Cedrus stuff. I asked him to make the minor change requested
and repost it.
Authorship remains to him.

I have tested this series with SPDIF driver and added a patch to enable
DMA_SUN6I_CONFIG for arm64.

Original Post:
"
DMA engine engine on H6 almost the same as on older SoCs. The biggest
difference is that it has slightly rearranged bits in registers and
it needs additional clock, probably due to iommu.

These patches were tested with I2S connected to HDMI. I2S needs
additional patches which will be sent later.

Please take a look.

Best regards,
Jernej
"

Thanks,
Clément

Changes since v1:
 - Enable DMA_SUN6I in arm64 defconfig
 - Change mbus_clk to has_mbus_clk
 - Collect Rob H. reviewed-by

Clément Péron (1):
  arm64: defconfig: enable Allwinner DMA drivers

Jernej Skrabec (6):
  dt-bindings: arm64: allwinner: h6: Add binding for DMA controller
  dmaengine: sun6i: Add a quirk for additional mbus clock
  dmaengine: sun6i: Add a quirk for setting DRQ fields
  dmaengine: sun6i: Add a quirk for setting mode fields
  dmaengine: sun6i: Add support for H6 DMA
  arm64: dts: allwinner: h6: Add DMA node

 .../devicetree/bindings/dma/sun6i-dma.txt     |   9 +-
 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi  |  12 ++
 arch/arm64/configs/defconfig                  |   1 +
 drivers/dma/sun6i-dma.c                       | 147 +++++++++++++-----
 4 files changed, 132 insertions(+), 37 deletions(-)

Comments

Maxime Ripard May 26, 2019, 6:34 p.m. UTC | #1 
On Sat, May 25, 2019 at 06:38:17PM +0200, Clément Péron wrote:
> From: Jernej Skrabec <jernej.skrabec@siol.net>
>
> H6 DMA has more than 32 supported DRQs, which means that configuration
> register is slightly rearranged. It also needs additional clock to be
> enabled.
>
> Add support for it.
>
> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> Signed-off-by: Clément Péron <peron.clem@gmail.com>
> ---
>  drivers/dma/sun6i-dma.c | 44 +++++++++++++++++++++++++++++++++++++++--
>  1 file changed, 42 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
> index f5cb5e89bf7b..8d44ddae926a 100644
> --- a/drivers/dma/sun6i-dma.c
> +++ b/drivers/dma/sun6i-dma.c
> @@ -69,14 +69,19 @@
>
>  #define DMA_CHAN_CUR_CFG	0x0c
>  #define DMA_CHAN_MAX_DRQ_A31		0x1f
> +#define DMA_CHAN_MAX_DRQ_H6		0x3f
>  #define DMA_CHAN_CFG_SRC_DRQ_A31(x)	((x) & DMA_CHAN_MAX_DRQ_A31)
> +#define DMA_CHAN_CFG_SRC_DRQ_H6(x)	((x) & DMA_CHAN_MAX_DRQ_H6)
>  #define DMA_CHAN_CFG_SRC_MODE_A31(x)	(((x) & 0x1) << 5)
> +#define DMA_CHAN_CFG_SRC_MODE_H6(x)	(((x) & 0x1) << 8)
>  #define DMA_CHAN_CFG_SRC_BURST_A31(x)	(((x) & 0x3) << 7)
>  #define DMA_CHAN_CFG_SRC_BURST_H3(x)	(((x) & 0x3) << 6)
>  #define DMA_CHAN_CFG_SRC_WIDTH(x)	(((x) & 0x3) << 9)
>
>  #define DMA_CHAN_CFG_DST_DRQ_A31(x)	(DMA_CHAN_CFG_SRC_DRQ_A31(x) << 16)
> +#define DMA_CHAN_CFG_DST_DRQ_H6(x)	(DMA_CHAN_CFG_SRC_DRQ_H6(x) << 16)
>  #define DMA_CHAN_CFG_DST_MODE_A31(x)	(DMA_CHAN_CFG_SRC_MODE_A31(x) << 16)
> +#define DMA_CHAN_CFG_DST_MODE_H6(x)	(DMA_CHAN_CFG_SRC_MODE_H6(x) << 16)
>  #define DMA_CHAN_CFG_DST_BURST_A31(x)	(DMA_CHAN_CFG_SRC_BURST_A31(x) << 16)
>  #define DMA_CHAN_CFG_DST_BURST_H3(x)	(DMA_CHAN_CFG_SRC_BURST_H3(x) << 16)
>  #define DMA_CHAN_CFG_DST_WIDTH(x)	(DMA_CHAN_CFG_SRC_WIDTH(x) << 16)
> @@ -319,12 +324,24 @@ static void sun6i_set_drq_a31(u32 *p_cfg, s8 src_drq, s8 dst_drq)
>  		  DMA_CHAN_CFG_DST_DRQ_A31(dst_drq);
>  }
>
> +static void sun6i_set_drq_h6(u32 *p_cfg, s8 src_drq, s8 dst_drq)
> +{
> +	*p_cfg |= DMA_CHAN_CFG_SRC_DRQ_H6(src_drq) |
> +		  DMA_CHAN_CFG_DST_DRQ_H6(dst_drq);
> +}
> +
>  static void sun6i_set_mode_a31(u32 *p_cfg, s8 src_mode, s8 dst_mode)
>  {
>  	*p_cfg |= DMA_CHAN_CFG_SRC_MODE_A31(src_mode) |
>  		  DMA_CHAN_CFG_DST_MODE_A31(dst_mode);
>  }
>
> +static void sun6i_set_mode_h6(u32 *p_cfg, s8 src_mode, s8 dst_mode)
> +{
> +	*p_cfg |= DMA_CHAN_CFG_SRC_MODE_H6(src_mode) |
> +		  DMA_CHAN_CFG_DST_MODE_H6(dst_mode);
> +}
> +
>  static size_t sun6i_get_chan_size(struct sun6i_pchan *pchan)
>  {
>  	struct sun6i_desc *txd = pchan->desc;
> @@ -1160,6 +1177,28 @@ static struct sun6i_dma_config sun50i_a64_dma_cfg = {
>  			     BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
>  };
>
> +/*
> + * The H6 binding uses the number of dma channels from the
> + * device tree node.
> + */
> +static struct sun6i_dma_config sun50i_h6_dma_cfg = {
> +	.clock_autogate_enable = sun6i_enable_clock_autogate_h3,
> +	.set_burst_length = sun6i_set_burst_length_h3,
> +	.set_drq          = sun6i_set_drq_h6,
> +	.set_mode         = sun6i_set_mode_h6,
> +	.src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
> +	.dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
> +	.src_addr_widths   = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
> +			     BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
> +			     BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
> +			     BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
> +	.dst_addr_widths   = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
> +			     BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
> +			     BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
> +			     BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
> +	.has_mbus_clk = true,
> +};
> +
>  /*
>   * The V3s have only 8 physical channels, a maximum DRQ port id of 23,
>   * and a total of 24 usable source and destination endpoints.
> @@ -1190,6 +1229,7 @@ static const struct of_device_id sun6i_dma_match[] = {
>  	{ .compatible = "allwinner,sun8i-h3-dma", .data = &sun8i_h3_dma_cfg },
>  	{ .compatible = "allwinner,sun8i-v3s-dma", .data = &sun8i_v3s_dma_cfg },
>  	{ .compatible = "allwinner,sun50i-a64-dma", .data = &sun50i_a64_dma_cfg },
> +	{ .compatible = "allwinner,sun50i-h6-dma", .data = &sun50i_h6_dma_cfg },
>  	{ /* sentinel */ }
>  };
>  MODULE_DEVICE_TABLE(of, sun6i_dma_match);
> @@ -1288,8 +1328,8 @@ static int sun6i_dma_probe(struct platform_device *pdev)
>  	ret = of_property_read_u32(np, "dma-requests", &sdc->max_request);
>  	if (ret && !sdc->max_request) {
>  		dev_info(&pdev->dev, "Missing dma-requests, using %u.\n",
> -			 DMA_CHAN_MAX_DRQ_A31);
> -		sdc->max_request = DMA_CHAN_MAX_DRQ_A31;
> +			 DMA_CHAN_MAX_DRQ_H6);
> +		sdc->max_request = DMA_CHAN_MAX_DRQ_H6;

This is changing the binding though, since we're changing the
default. This should be reflected in the binding, and we should keep
the same default in the device tree binding.

Maxime

--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
Clément Péron May 26, 2019, 7:12 p.m. UTC | #2 
Hi Maxime,

On Sun, 26 May 2019 at 20:34, Maxime Ripard <maxime.ripard@bootlin.com> wrote:
>
> On Sat, May 25, 2019 at 06:38:17PM +0200, Clément Péron wrote:
> > From: Jernej Skrabec <jernej.skrabec@siol.net>
> >
> > H6 DMA has more than 32 supported DRQs, which means that configuration
> > register is slightly rearranged. It also needs additional clock to be
> > enabled.
> >
> > Add support for it.
> >
> > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> > Signed-off-by: Clément Péron <peron.clem@gmail.com>
> > ---
> >  drivers/dma/sun6i-dma.c | 44 +++++++++++++++++++++++++++++++++++++++--
> >  1 file changed, 42 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
> > index f5cb5e89bf7b..8d44ddae926a 100644
> > --- a/drivers/dma/sun6i-dma.c
> > +++ b/drivers/dma/sun6i-dma.c
> > @@ -69,14 +69,19 @@
> >
> >  #define DMA_CHAN_CUR_CFG     0x0c
> >  #define DMA_CHAN_MAX_DRQ_A31         0x1f
> > +#define DMA_CHAN_MAX_DRQ_H6          0x3f
> >  #define DMA_CHAN_CFG_SRC_DRQ_A31(x)  ((x) & DMA_CHAN_MAX_DRQ_A31)
> > +#define DMA_CHAN_CFG_SRC_DRQ_H6(x)   ((x) & DMA_CHAN_MAX_DRQ_H6)
> >  #define DMA_CHAN_CFG_SRC_MODE_A31(x) (((x) & 0x1) << 5)
> > +#define DMA_CHAN_CFG_SRC_MODE_H6(x)  (((x) & 0x1) << 8)
> >  #define DMA_CHAN_CFG_SRC_BURST_A31(x)        (((x) & 0x3) << 7)
> >  #define DMA_CHAN_CFG_SRC_BURST_H3(x) (((x) & 0x3) << 6)
> >  #define DMA_CHAN_CFG_SRC_WIDTH(x)    (((x) & 0x3) << 9)
> >
> >  #define DMA_CHAN_CFG_DST_DRQ_A31(x)  (DMA_CHAN_CFG_SRC_DRQ_A31(x) << 16)
> > +#define DMA_CHAN_CFG_DST_DRQ_H6(x)   (DMA_CHAN_CFG_SRC_DRQ_H6(x) << 16)
> >  #define DMA_CHAN_CFG_DST_MODE_A31(x) (DMA_CHAN_CFG_SRC_MODE_A31(x) << 16)
> > +#define DMA_CHAN_CFG_DST_MODE_H6(x)  (DMA_CHAN_CFG_SRC_MODE_H6(x) << 16)
> >  #define DMA_CHAN_CFG_DST_BURST_A31(x)        (DMA_CHAN_CFG_SRC_BURST_A31(x) << 16)
> >  #define DMA_CHAN_CFG_DST_BURST_H3(x) (DMA_CHAN_CFG_SRC_BURST_H3(x) << 16)
> >  #define DMA_CHAN_CFG_DST_WIDTH(x)    (DMA_CHAN_CFG_SRC_WIDTH(x) << 16)
> > @@ -319,12 +324,24 @@ static void sun6i_set_drq_a31(u32 *p_cfg, s8 src_drq, s8 dst_drq)
> >                 DMA_CHAN_CFG_DST_DRQ_A31(dst_drq);
> >  }
> >
> > +static void sun6i_set_drq_h6(u32 *p_cfg, s8 src_drq, s8 dst_drq)
> > +{
> > +     *p_cfg |= DMA_CHAN_CFG_SRC_DRQ_H6(src_drq) |
> > +               DMA_CHAN_CFG_DST_DRQ_H6(dst_drq);
> > +}
> > +
> >  static void sun6i_set_mode_a31(u32 *p_cfg, s8 src_mode, s8 dst_mode)
> >  {
> >       *p_cfg |= DMA_CHAN_CFG_SRC_MODE_A31(src_mode) |
> >                 DMA_CHAN_CFG_DST_MODE_A31(dst_mode);
> >  }
> >
> > +static void sun6i_set_mode_h6(u32 *p_cfg, s8 src_mode, s8 dst_mode)
> > +{
> > +     *p_cfg |= DMA_CHAN_CFG_SRC_MODE_H6(src_mode) |
> > +               DMA_CHAN_CFG_DST_MODE_H6(dst_mode);
> > +}
> > +
> >  static size_t sun6i_get_chan_size(struct sun6i_pchan *pchan)
> >  {
> >       struct sun6i_desc *txd = pchan->desc;
> > @@ -1160,6 +1177,28 @@ static struct sun6i_dma_config sun50i_a64_dma_cfg = {
> >                            BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
> >  };
> >
> > +/*
> > + * The H6 binding uses the number of dma channels from the
> > + * device tree node.
> > + */
> > +static struct sun6i_dma_config sun50i_h6_dma_cfg = {
> > +     .clock_autogate_enable = sun6i_enable_clock_autogate_h3,
> > +     .set_burst_length = sun6i_set_burst_length_h3,
> > +     .set_drq          = sun6i_set_drq_h6,
> > +     .set_mode         = sun6i_set_mode_h6,
> > +     .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
> > +     .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
> > +     .src_addr_widths   = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
> > +                          BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
> > +                          BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
> > +                          BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
> > +     .dst_addr_widths   = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
> > +                          BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
> > +                          BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
> > +                          BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
> > +     .has_mbus_clk = true,
> > +};
> > +
> >  /*
> >   * The V3s have only 8 physical channels, a maximum DRQ port id of 23,
> >   * and a total of 24 usable source and destination endpoints.
> > @@ -1190,6 +1229,7 @@ static const struct of_device_id sun6i_dma_match[] = {
> >       { .compatible = "allwinner,sun8i-h3-dma", .data = &sun8i_h3_dma_cfg },
> >       { .compatible = "allwinner,sun8i-v3s-dma", .data = &sun8i_v3s_dma_cfg },
> >       { .compatible = "allwinner,sun50i-a64-dma", .data = &sun50i_a64_dma_cfg },
> > +     { .compatible = "allwinner,sun50i-h6-dma", .data = &sun50i_h6_dma_cfg },
> >       { /* sentinel */ }
> >  };
> >  MODULE_DEVICE_TABLE(of, sun6i_dma_match);
> > @@ -1288,8 +1328,8 @@ static int sun6i_dma_probe(struct platform_device *pdev)
> >       ret = of_property_read_u32(np, "dma-requests", &sdc->max_request);
> >       if (ret && !sdc->max_request) {
> >               dev_info(&pdev->dev, "Missing dma-requests, using %u.\n",
> > -                      DMA_CHAN_MAX_DRQ_A31);
> > -             sdc->max_request = DMA_CHAN_MAX_DRQ_A31;
> > +                      DMA_CHAN_MAX_DRQ_H6);
> > +             sdc->max_request = DMA_CHAN_MAX_DRQ_H6;
>
> This is changing the binding though, since we're changing the
> default. This should be reflected in the binding, and we should keep
> the same default in the device tree binding.

Agree, H6 device-tree will have the "dma-request" property.
As this modification is not mandatory, we can drop it to avoid
bindings modification.

What do you think?

Thanks for your review,
Clément

>
> Maxime
>
> --
> Maxime Ripard, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com
Maxime Ripard May 27, 2019, 12:49 p.m. UTC | #3 
On Sun, May 26, 2019 at 09:12:36PM +0200, Clément Péron wrote:
> Hi Maxime,
>
> On Sun, 26 May 2019 at 20:34, Maxime Ripard <maxime.ripard@bootlin.com> wrote:
> >
> > On Sat, May 25, 2019 at 06:38:17PM +0200, Clément Péron wrote:
> > > From: Jernej Skrabec <jernej.skrabec@siol.net>
> > >
> > > H6 DMA has more than 32 supported DRQs, which means that configuration
> > > register is slightly rearranged. It also needs additional clock to be
> > > enabled.
> > >
> > > Add support for it.
> > >
> > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> > > Signed-off-by: Clément Péron <peron.clem@gmail.com>
> > > ---
> > >  drivers/dma/sun6i-dma.c | 44 +++++++++++++++++++++++++++++++++++++++--
> > >  1 file changed, 42 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
> > > index f5cb5e89bf7b..8d44ddae926a 100644
> > > --- a/drivers/dma/sun6i-dma.c
> > > +++ b/drivers/dma/sun6i-dma.c
> > > @@ -69,14 +69,19 @@
> > >
> > >  #define DMA_CHAN_CUR_CFG     0x0c
> > >  #define DMA_CHAN_MAX_DRQ_A31         0x1f
> > > +#define DMA_CHAN_MAX_DRQ_H6          0x3f
> > >  #define DMA_CHAN_CFG_SRC_DRQ_A31(x)  ((x) & DMA_CHAN_MAX_DRQ_A31)
> > > +#define DMA_CHAN_CFG_SRC_DRQ_H6(x)   ((x) & DMA_CHAN_MAX_DRQ_H6)
> > >  #define DMA_CHAN_CFG_SRC_MODE_A31(x) (((x) & 0x1) << 5)
> > > +#define DMA_CHAN_CFG_SRC_MODE_H6(x)  (((x) & 0x1) << 8)
> > >  #define DMA_CHAN_CFG_SRC_BURST_A31(x)        (((x) & 0x3) << 7)
> > >  #define DMA_CHAN_CFG_SRC_BURST_H3(x) (((x) & 0x3) << 6)
> > >  #define DMA_CHAN_CFG_SRC_WIDTH(x)    (((x) & 0x3) << 9)
> > >
> > >  #define DMA_CHAN_CFG_DST_DRQ_A31(x)  (DMA_CHAN_CFG_SRC_DRQ_A31(x) << 16)
> > > +#define DMA_CHAN_CFG_DST_DRQ_H6(x)   (DMA_CHAN_CFG_SRC_DRQ_H6(x) << 16)
> > >  #define DMA_CHAN_CFG_DST_MODE_A31(x) (DMA_CHAN_CFG_SRC_MODE_A31(x) << 16)
> > > +#define DMA_CHAN_CFG_DST_MODE_H6(x)  (DMA_CHAN_CFG_SRC_MODE_H6(x) << 16)
> > >  #define DMA_CHAN_CFG_DST_BURST_A31(x)        (DMA_CHAN_CFG_SRC_BURST_A31(x) << 16)
> > >  #define DMA_CHAN_CFG_DST_BURST_H3(x) (DMA_CHAN_CFG_SRC_BURST_H3(x) << 16)
> > >  #define DMA_CHAN_CFG_DST_WIDTH(x)    (DMA_CHAN_CFG_SRC_WIDTH(x) << 16)
> > > @@ -319,12 +324,24 @@ static void sun6i_set_drq_a31(u32 *p_cfg, s8 src_drq, s8 dst_drq)
> > >                 DMA_CHAN_CFG_DST_DRQ_A31(dst_drq);
> > >  }
> > >
> > > +static void sun6i_set_drq_h6(u32 *p_cfg, s8 src_drq, s8 dst_drq)
> > > +{
> > > +     *p_cfg |= DMA_CHAN_CFG_SRC_DRQ_H6(src_drq) |
> > > +               DMA_CHAN_CFG_DST_DRQ_H6(dst_drq);
> > > +}
> > > +
> > >  static void sun6i_set_mode_a31(u32 *p_cfg, s8 src_mode, s8 dst_mode)
> > >  {
> > >       *p_cfg |= DMA_CHAN_CFG_SRC_MODE_A31(src_mode) |
> > >                 DMA_CHAN_CFG_DST_MODE_A31(dst_mode);
> > >  }
> > >
> > > +static void sun6i_set_mode_h6(u32 *p_cfg, s8 src_mode, s8 dst_mode)
> > > +{
> > > +     *p_cfg |= DMA_CHAN_CFG_SRC_MODE_H6(src_mode) |
> > > +               DMA_CHAN_CFG_DST_MODE_H6(dst_mode);
> > > +}
> > > +
> > >  static size_t sun6i_get_chan_size(struct sun6i_pchan *pchan)
> > >  {
> > >       struct sun6i_desc *txd = pchan->desc;
> > > @@ -1160,6 +1177,28 @@ static struct sun6i_dma_config sun50i_a64_dma_cfg = {
> > >                            BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
> > >  };
> > >
> > > +/*
> > > + * The H6 binding uses the number of dma channels from the
> > > + * device tree node.
> > > + */
> > > +static struct sun6i_dma_config sun50i_h6_dma_cfg = {
> > > +     .clock_autogate_enable = sun6i_enable_clock_autogate_h3,
> > > +     .set_burst_length = sun6i_set_burst_length_h3,
> > > +     .set_drq          = sun6i_set_drq_h6,
> > > +     .set_mode         = sun6i_set_mode_h6,
> > > +     .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
> > > +     .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
> > > +     .src_addr_widths   = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
> > > +                          BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
> > > +                          BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
> > > +                          BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
> > > +     .dst_addr_widths   = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
> > > +                          BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
> > > +                          BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
> > > +                          BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
> > > +     .has_mbus_clk = true,
> > > +};
> > > +
> > >  /*
> > >   * The V3s have only 8 physical channels, a maximum DRQ port id of 23,
> > >   * and a total of 24 usable source and destination endpoints.
> > > @@ -1190,6 +1229,7 @@ static const struct of_device_id sun6i_dma_match[] = {
> > >       { .compatible = "allwinner,sun8i-h3-dma", .data = &sun8i_h3_dma_cfg },
> > >       { .compatible = "allwinner,sun8i-v3s-dma", .data = &sun8i_v3s_dma_cfg },
> > >       { .compatible = "allwinner,sun50i-a64-dma", .data = &sun50i_a64_dma_cfg },
> > > +     { .compatible = "allwinner,sun50i-h6-dma", .data = &sun50i_h6_dma_cfg },
> > >       { /* sentinel */ }
> > >  };
> > >  MODULE_DEVICE_TABLE(of, sun6i_dma_match);
> > > @@ -1288,8 +1328,8 @@ static int sun6i_dma_probe(struct platform_device *pdev)
> > >       ret = of_property_read_u32(np, "dma-requests", &sdc->max_request);
> > >       if (ret && !sdc->max_request) {
> > >               dev_info(&pdev->dev, "Missing dma-requests, using %u.\n",
> > > -                      DMA_CHAN_MAX_DRQ_A31);
> > > -             sdc->max_request = DMA_CHAN_MAX_DRQ_A31;
> > > +                      DMA_CHAN_MAX_DRQ_H6);
> > > +             sdc->max_request = DMA_CHAN_MAX_DRQ_H6;
> >
> > This is changing the binding though, since we're changing the
> > default. This should be reflected in the binding, and we should keep
> > the same default in the device tree binding.
>
> Agree, H6 device-tree will have the "dma-request" property.
> As this modification is not mandatory, we can drop it to avoid
> bindings modification.
>
> What do you think?

That works for me

Maxime

--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com