| Message ID | 20180809214414.20905-1-paul@crapouillou.net |
|---|---|
| Headers | show |
| Series | Ingenic TCU patchset v6 | expand |
On Thu, Aug 09, 2018 at 11:43:58PM +0200, Paul Cercueil wrote: > Instead of requesting the "ext" clock and handling the watchdog clock > divider and gating in the watchdog driver, we now request and use the > "wdt" clock that is supplied by the ingenic-timer "TCU" driver. > > The major benefit is that the watchdog's clock rate and parent can now > be specified from within devicetree, instead of hardcoded in the driver. > > Also, this driver won't poke anymore into the TCU registers to > enable/disable the clock, as this is now handled by the TCU driver. > > On the bad side, we break the ABI with devicetree - as we now request a > different clock. In this very specific case it is still okay, as every > Ingenic JZ47xx-based board out there compile the devicetree within the > kernel; so it's still time to push breaking changes, in order to get a > clean devicetree that won't break once it musn't. > > Signed-off-by: Paul Cercueil <paul@crapouillou.net> Reviewed-by: Guenter Roeck <linux@roeck-us.net> > --- > drivers/watchdog/Kconfig | 2 + > drivers/watchdog/jz4740_wdt.c | 86 +++++++++++++++++-------------------------- > 2 files changed, 36 insertions(+), 52 deletions(-) > > v5: New patch > > v6: - Split regmap change to new patch 09/24 > - The code now sets the WDT clock to the smallest rate possible and > calculates the maximum timeout from that > > diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig > index 9af07fd92763..834222abbbdb 100644 > --- a/drivers/watchdog/Kconfig > +++ b/drivers/watchdog/Kconfig > @@ -1476,7 +1476,9 @@ config INDYDOG > config JZ4740_WDT > tristate "Ingenic jz4740 SoC hardware watchdog" > depends on MACH_JZ4740 || MACH_JZ4780 > + depends on COMMON_CLK > select WATCHDOG_CORE > + select INGENIC_TIMER > help > Hardware driver for the built-in watchdog timer on Ingenic jz4740 SoCs. > > diff --git a/drivers/watchdog/jz4740_wdt.c b/drivers/watchdog/jz4740_wdt.c > index ec4d99a830ba..1d504ecf45e1 100644 > --- a/drivers/watchdog/jz4740_wdt.c > +++ b/drivers/watchdog/jz4740_wdt.c > @@ -26,25 +26,9 @@ > #include <linux/err.h> > #include <linux/of.h> > > -#include <asm/mach-jz4740/timer.h> > - > #define JZ_REG_WDT_TIMER_DATA 0x0 > #define JZ_REG_WDT_COUNTER_ENABLE 0x4 > #define JZ_REG_WDT_TIMER_COUNTER 0x8 > -#define JZ_REG_WDT_TIMER_CONTROL 0xC > - > -#define JZ_WDT_CLOCK_PCLK 0x1 > -#define JZ_WDT_CLOCK_RTC 0x2 > -#define JZ_WDT_CLOCK_EXT 0x4 > - > -#define JZ_WDT_CLOCK_DIV_SHIFT 3 > - > -#define JZ_WDT_CLOCK_DIV_1 (0 << JZ_WDT_CLOCK_DIV_SHIFT) > -#define JZ_WDT_CLOCK_DIV_4 (1 << JZ_WDT_CLOCK_DIV_SHIFT) > -#define JZ_WDT_CLOCK_DIV_16 (2 << JZ_WDT_CLOCK_DIV_SHIFT) > -#define JZ_WDT_CLOCK_DIV_64 (3 << JZ_WDT_CLOCK_DIV_SHIFT) > -#define JZ_WDT_CLOCK_DIV_256 (4 << JZ_WDT_CLOCK_DIV_SHIFT) > -#define JZ_WDT_CLOCK_DIV_1024 (5 << JZ_WDT_CLOCK_DIV_SHIFT) > > #define DEFAULT_HEARTBEAT 5 > #define MAX_HEARTBEAT 2048 > @@ -65,7 +49,8 @@ MODULE_PARM_DESC(heartbeat, > struct jz4740_wdt_drvdata { > struct watchdog_device wdt; > void __iomem *base; > - struct clk *rtc_clk; > + struct clk *clk; > + unsigned long clk_rate; > }; > > static int jz4740_wdt_ping(struct watchdog_device *wdt_dev) > @@ -80,31 +65,12 @@ static int jz4740_wdt_set_timeout(struct watchdog_device *wdt_dev, > unsigned int new_timeout) > { > struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev); > - unsigned int rtc_clk_rate; > - unsigned int timeout_value; > - unsigned short clock_div = JZ_WDT_CLOCK_DIV_1; > - > - rtc_clk_rate = clk_get_rate(drvdata->rtc_clk); > - > - timeout_value = rtc_clk_rate * new_timeout; > - while (timeout_value > 0xffff) { > - if (clock_div == JZ_WDT_CLOCK_DIV_1024) { > - /* Requested timeout too high; > - * use highest possible value. */ > - timeout_value = 0xffff; > - break; > - } > - timeout_value >>= 2; > - clock_div += (1 << JZ_WDT_CLOCK_DIV_SHIFT); > - } > + u16 timeout_value = (u16)(drvdata->clk_rate * new_timeout); > > writeb(0x0, drvdata->base + JZ_REG_WDT_COUNTER_ENABLE); > - writew(clock_div, drvdata->base + JZ_REG_WDT_TIMER_CONTROL); > > writew((u16)timeout_value, drvdata->base + JZ_REG_WDT_TIMER_DATA); > writew(0x0, drvdata->base + JZ_REG_WDT_TIMER_COUNTER); > - writew(clock_div | JZ_WDT_CLOCK_RTC, > - drvdata->base + JZ_REG_WDT_TIMER_CONTROL); > > writeb(0x1, drvdata->base + JZ_REG_WDT_COUNTER_ENABLE); > > @@ -114,7 +80,13 @@ static int jz4740_wdt_set_timeout(struct watchdog_device *wdt_dev, > > static int jz4740_wdt_start(struct watchdog_device *wdt_dev) > { > - jz4740_timer_enable_watchdog(); > + struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev); > + int ret; > + > + ret = clk_prepare_enable(drvdata->clk); > + if (ret) > + return ret; > + > jz4740_wdt_set_timeout(wdt_dev, wdt_dev->timeout); > > return 0; > @@ -125,7 +97,7 @@ static int jz4740_wdt_stop(struct watchdog_device *wdt_dev) > struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev); > > writeb(0x0, drvdata->base + JZ_REG_WDT_COUNTER_ENABLE); > - jz4740_timer_disable_watchdog(); > + clk_disable_unprepare(drvdata->clk); > > return 0; > } > @@ -163,26 +135,42 @@ MODULE_DEVICE_TABLE(of, jz4740_wdt_of_matches); > > static int jz4740_wdt_probe(struct platform_device *pdev) > { > + struct device *dev = &pdev->dev; > struct jz4740_wdt_drvdata *drvdata; > struct watchdog_device *jz4740_wdt; > struct resource *res; > + long rate; > int ret; > > - drvdata = devm_kzalloc(&pdev->dev, sizeof(struct jz4740_wdt_drvdata), > - GFP_KERNEL); > + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); > if (!drvdata) > return -ENOMEM; > > - if (heartbeat < 1 || heartbeat > MAX_HEARTBEAT) > - heartbeat = DEFAULT_HEARTBEAT; > + drvdata->clk = devm_clk_get(&pdev->dev, "wdt"); > + if (IS_ERR(drvdata->clk)) { > + dev_err(&pdev->dev, "cannot find WDT clock\n"); > + return PTR_ERR(drvdata->clk); > + } > + > + /* Set smallest clock possible */ > + rate = clk_round_rate(drvdata->clk, 1); > + if (rate < 0) > + return rate; > > + ret = clk_set_rate(drvdata->clk, rate); > + if (ret) > + return ret; > + > + drvdata->clk_rate = rate; > jz4740_wdt = &drvdata->wdt; > jz4740_wdt->info = &jz4740_wdt_info; > jz4740_wdt->ops = &jz4740_wdt_ops; > - jz4740_wdt->timeout = heartbeat; > jz4740_wdt->min_timeout = 1; > - jz4740_wdt->max_timeout = MAX_HEARTBEAT; > - jz4740_wdt->parent = &pdev->dev; > + jz4740_wdt->max_timeout = 0xffff / rate; > + jz4740_wdt->timeout = clamp(heartbeat, > + jz4740_wdt->min_timeout, > + jz4740_wdt->max_timeout); > + jz4740_wdt->parent = dev; > watchdog_set_nowayout(jz4740_wdt, nowayout); > watchdog_set_drvdata(jz4740_wdt, drvdata); > > @@ -191,12 +179,6 @@ static int jz4740_wdt_probe(struct platform_device *pdev) > if (IS_ERR(drvdata->base)) > return PTR_ERR(drvdata->base); > > - drvdata->rtc_clk = devm_clk_get(&pdev->dev, "rtc"); > - if (IS_ERR(drvdata->rtc_clk)) { > - dev_err(&pdev->dev, "cannot find RTC clock\n"); > - return PTR_ERR(drvdata->rtc_clk); > - } > - > ret = devm_watchdog_register_device(&pdev->dev, &drvdata->wdt); > if (ret < 0) > return ret; > -- > 2.11.0 >
On Thu, Aug 09, 2018 at 11:43:59PM +0200, Paul Cercueil wrote: > Since we broke the ABI by changing the clock, the driver was also > updated to use the regmap provided by the TCU driver. > > Signed-off-by: Paul Cercueil <paul@crapouillou.net> Reviewed-by: Guenter Roeck <linux@roeck-us.net> > --- > drivers/watchdog/jz4740_wdt.c | 30 ++++++++++++++---------------- > 1 file changed, 14 insertions(+), 16 deletions(-) > > v6: New patch > > diff --git a/drivers/watchdog/jz4740_wdt.c b/drivers/watchdog/jz4740_wdt.c > index 1d504ecf45e1..0f54306aee25 100644 > --- a/drivers/watchdog/jz4740_wdt.c > +++ b/drivers/watchdog/jz4740_wdt.c > @@ -13,6 +13,7 @@ > * > */ > > +#include <linux/mfd/ingenic-tcu.h> > #include <linux/module.h> > #include <linux/moduleparam.h> > #include <linux/types.h> > @@ -25,10 +26,7 @@ > #include <linux/slab.h> > #include <linux/err.h> > #include <linux/of.h> > - > -#define JZ_REG_WDT_TIMER_DATA 0x0 > -#define JZ_REG_WDT_COUNTER_ENABLE 0x4 > -#define JZ_REG_WDT_TIMER_COUNTER 0x8 > +#include <linux/regmap.h> > > #define DEFAULT_HEARTBEAT 5 > #define MAX_HEARTBEAT 2048 > @@ -48,7 +46,7 @@ MODULE_PARM_DESC(heartbeat, > > struct jz4740_wdt_drvdata { > struct watchdog_device wdt; > - void __iomem *base; > + struct regmap *map; > struct clk *clk; > unsigned long clk_rate; > }; > @@ -57,7 +55,7 @@ static int jz4740_wdt_ping(struct watchdog_device *wdt_dev) > { > struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev); > > - writew(0x0, drvdata->base + JZ_REG_WDT_TIMER_COUNTER); > + regmap_write(drvdata->map, TCU_REG_WDT_TCNT, 0); > return 0; > } > > @@ -67,12 +65,12 @@ static int jz4740_wdt_set_timeout(struct watchdog_device *wdt_dev, > struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev); > u16 timeout_value = (u16)(drvdata->clk_rate * new_timeout); > > - writeb(0x0, drvdata->base + JZ_REG_WDT_COUNTER_ENABLE); > + regmap_write(drvdata->map, TCU_REG_WDT_TCER, 0); > > - writew((u16)timeout_value, drvdata->base + JZ_REG_WDT_TIMER_DATA); > - writew(0x0, drvdata->base + JZ_REG_WDT_TIMER_COUNTER); > + regmap_write(drvdata->map, TCU_REG_WDT_TDR, timeout_value); > + regmap_write(drvdata->map, TCU_REG_WDT_TCNT, 0); > > - writeb(0x1, drvdata->base + JZ_REG_WDT_COUNTER_ENABLE); > + regmap_write(drvdata->map, TCU_REG_WDT_TCER, TCU_WDT_TCER_TCEN); > > wdt_dev->timeout = new_timeout; > return 0; > @@ -96,7 +94,7 @@ static int jz4740_wdt_stop(struct watchdog_device *wdt_dev) > { > struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev); > > - writeb(0x0, drvdata->base + JZ_REG_WDT_COUNTER_ENABLE); > + regmap_write(drvdata->map, TCU_REG_WDT_TCER, 0); > clk_disable_unprepare(drvdata->clk); > > return 0; > @@ -138,7 +136,6 @@ static int jz4740_wdt_probe(struct platform_device *pdev) > struct device *dev = &pdev->dev; > struct jz4740_wdt_drvdata *drvdata; > struct watchdog_device *jz4740_wdt; > - struct resource *res; > long rate; > int ret; > > @@ -174,10 +171,11 @@ static int jz4740_wdt_probe(struct platform_device *pdev) > watchdog_set_nowayout(jz4740_wdt, nowayout); > watchdog_set_drvdata(jz4740_wdt, drvdata); > > - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > - drvdata->base = devm_ioremap_resource(&pdev->dev, res); > - if (IS_ERR(drvdata->base)) > - return PTR_ERR(drvdata->base); > + drvdata->map = dev_get_regmap(dev->parent, NULL); > + if (!drvdata->map) { > + dev_err(dev, "regmap not found\n"); > + return -EINVAL; > + } > > ret = devm_watchdog_register_device(&pdev->dev, &drvdata->wdt); > if (ret < 0) > -- > 2.11.0 >
On Thu, Aug 09, 2018 at 11:44:00PM +0200, Paul Cercueil wrote: > Previously the jz4740_wdt_set_timeout() function was starting the timer > unconditionally, even if it was stopped when that function was entered. > > Now, the timer will be restarted only if it was already running before > this function is called. > > Signed-off-by: Paul Cercueil <paul@crapouillou.net> Reviewed-by: Guenter Roeck <linux@roeck-us.net> > --- > drivers/watchdog/jz4740_wdt.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > v6: New patch > > diff --git a/drivers/watchdog/jz4740_wdt.c b/drivers/watchdog/jz4740_wdt.c > index 0f54306aee25..45d9495170e5 100644 > --- a/drivers/watchdog/jz4740_wdt.c > +++ b/drivers/watchdog/jz4740_wdt.c > @@ -64,13 +64,15 @@ static int jz4740_wdt_set_timeout(struct watchdog_device *wdt_dev, > { > struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev); > u16 timeout_value = (u16)(drvdata->clk_rate * new_timeout); > + u32 tcer; > > + regmap_read(drvdata->map, TCU_REG_WDT_TCER, &tcer); > regmap_write(drvdata->map, TCU_REG_WDT_TCER, 0); > > regmap_write(drvdata->map, TCU_REG_WDT_TDR, timeout_value); > regmap_write(drvdata->map, TCU_REG_WDT_TCNT, 0); > > - regmap_write(drvdata->map, TCU_REG_WDT_TCER, TCU_WDT_TCER_TCEN); > + regmap_write(drvdata->map, TCU_REG_WDT_TCER, tcer & TCU_WDT_TCER_TCEN); > > wdt_dev->timeout = new_timeout; > return 0; > @@ -86,6 +88,7 @@ static int jz4740_wdt_start(struct watchdog_device *wdt_dev) > return ret; > > jz4740_wdt_set_timeout(wdt_dev, wdt_dev->timeout); > + regmap_write(drvdata->map, TCU_REG_WDT_TCER, TCU_WDT_TCER_TCEN); > > return 0; > } > -- > 2.11.0 >
On Thu, Aug 09, 2018 at 11:44:01PM +0200, Paul Cercueil wrote: > Depending on MACH_JZ47xx prevent us from creating a generic kernel that > works on more than one MIPS board. Instead, we just depend on MIPS being > set. > > On other architectures, this driver can still be built, thanks to > COMPILE_TEST. This is used by automated tools to find bugs, for > instance. > > Signed-off-by: Paul Cercueil <paul@crapouillou.net> Reviewed-by: Guenter Roeck <linux@roeck-us.net> > --- > drivers/watchdog/Kconfig | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > v5: New patch > > v6: No change > > diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig > index 834222abbbdb..13a46cfa69b0 100644 > --- a/drivers/watchdog/Kconfig > +++ b/drivers/watchdog/Kconfig > @@ -1475,7 +1475,7 @@ config INDYDOG > > config JZ4740_WDT > tristate "Ingenic jz4740 SoC hardware watchdog" > - depends on MACH_JZ4740 || MACH_JZ4780 > + depends on MIPS || COMPILE_TEST > depends on COMMON_CLK > select WATCHDOG_CORE > select INGENIC_TIMER > -- > 2.11.0 >
On Thu, Aug 9, 2018 at 11:44 PM Paul Cercueil <paul@crapouillou.net> wrote: > > From: Maarten ter Huurne <maarten@treewalker.org> > > OST is the OS Timer, a 64-bit timer/counter with buffered reading. > > SoCs before the JZ4770 had (if any) a 32-bit OST; the JZ4770 and > JZ4780 have a 64-bit OST. > > This driver will register both a clocksource and a sched_clock to the > system. With CONFIG_DEBUG_SECTION_MISMATCH=y here is what I see: MODPOST vmlinux.o WARNING: vmlinux.o(.data+0x26600): Section mismatch in reference from the variable ingenic_ost_driver to the function .init.text:ingenic_ost_probe() The variable ingenic_ost_driver references the function __init ingenic_ost_probe() If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console WARNING: vmlinux.o(.data+0x26660): Section mismatch in reference from the variable ingenic_tcu_driver to the function .init.text:ingenic_tcu_probe() The variable ingenic_tcu_driver references the function __init ingenic_tcu_probe() If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console Thanks > Signed-off-by: Maarten ter Huurne <maarten@treewalker.org> > Signed-off-by: Paul Cercueil <paul@crapouillou.net> > --- > drivers/clocksource/Kconfig | 8 ++ > drivers/clocksource/Makefile | 1 + > drivers/clocksource/ingenic-ost.c | 208 ++++++++++++++++++++++++++++++++++++++ > 3 files changed, 217 insertions(+) > create mode 100644 drivers/clocksource/ingenic-ost.c > > v5: New patch > > v6: - Get rid of SoC IDs; pass pointer to ingenic_ost_soc_info as > devicetree match data instead. > - Use device_get_match_data() instead of the of_* variant > - Handle error of dev_get_regmap() properly > > diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig > index 98f708208a8d..e855938c69f1 100644 > --- a/drivers/clocksource/Kconfig > +++ b/drivers/clocksource/Kconfig > @@ -619,4 +619,12 @@ config INGENIC_TIMER > help > Support for the timer/counter unit of the Ingenic JZ SoCs. > > +config INGENIC_OST > + bool "Ingenic JZ47xx Operating System Timer" > + depends on MIPS || COMPILE_TEST > + depends on COMMON_CLK > + select INGENIC_TIMER > + help > + Support for the OS Timer of the Ingenic JZ4770 or similar SoC. > + > endmenu > diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile > index 26877505d400..56ce37252944 100644 > --- a/drivers/clocksource/Makefile > +++ b/drivers/clocksource/Makefile > @@ -75,6 +75,7 @@ obj-$(CONFIG_ASM9260_TIMER) += asm9260_timer.o > obj-$(CONFIG_H8300_TMR8) += h8300_timer8.o > obj-$(CONFIG_H8300_TMR16) += h8300_timer16.o > obj-$(CONFIG_H8300_TPU) += h8300_tpu.o > +obj-$(CONFIG_INGENIC_OST) += ingenic-ost.o > obj-$(CONFIG_INGENIC_TIMER) += ingenic-timer.o > obj-$(CONFIG_CLKSRC_ST_LPC) += clksrc_st_lpc.o > obj-$(CONFIG_X86_NUMACHIP) += numachip.o > diff --git a/drivers/clocksource/ingenic-ost.c b/drivers/clocksource/ingenic-ost.c > new file mode 100644 > index 000000000000..400d30656790 > --- /dev/null > +++ b/drivers/clocksource/ingenic-ost.c > @@ -0,0 +1,208 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * JZ47xx SoCs TCU Operating System Timer driver > + * > + * Copyright (C) 2016 Maarten ter Huurne <maarten@treewalker.org> > + * Copyright (C) 2018 Paul Cercueil <paul@crapouillou.net> > + */ > + > +#include <linux/clk.h> > +#include <linux/clocksource.h> > +#include <linux/mfd/ingenic-tcu.h> > +#include <linux/module.h> > +#include <linux/platform_device.h> > +#include <linux/pm.h> > +#include <linux/regmap.h> > +#include <linux/sched_clock.h> > + > +#include "ingenic-timer.h" > + > +#define TCU_OST_TCSR_MASK 0xc0 > +#define TCU_OST_TCSR_CNT_MD BIT(15) > + > +#define TCU_OST_CHANNEL 15 > + > +struct ingenic_ost_soc_info { > + bool is64bit; > +}; > + > +struct ingenic_ost { > + struct regmap *map; > + struct clk *clk; > + > + struct clocksource cs; > +}; > + > +static u64 notrace ingenic_ost_read_cntl(void) > +{ > + /* Bypass the regmap here as we must return as soon as possible */ > + return readl(ingenic_tcu_base + TCU_REG_OST_CNTL); > +} > + > +static u64 notrace ingenic_ost_read_cnth(void) > +{ > + /* Bypass the regmap here as we must return as soon as possible */ > + return readl(ingenic_tcu_base + TCU_REG_OST_CNTH); > +} > + > +static u64 notrace ingenic_ost_clocksource_read(struct clocksource *cs) > +{ > + u32 val1, val2; > + u64 count, recount; > + s64 diff; > + > + /* > + * The buffering of the upper 32 bits of the timer prevents wrong > + * results from the bottom 32 bits overflowing due to the timer ticking > + * along. However, it does not prevent wrong results from simultaneous > + * reads of the timer, which could reset the buffer mid-read. > + * Since this kind of wrong read can happen only when the bottom bits > + * overflow, there will be minutes between wrong reads, so if we read > + * twice in succession, at least one of the reads will be correct. > + */ > + > + /* Bypass the regmap here as we must return as soon as possible */ > + val1 = readl(ingenic_tcu_base + TCU_REG_OST_CNTL); > + val2 = readl(ingenic_tcu_base + TCU_REG_OST_CNTHBUF); > + count = (u64)val1 | (u64)val2 << 32; > + > + val1 = readl(ingenic_tcu_base + TCU_REG_OST_CNTL); > + val2 = readl(ingenic_tcu_base + TCU_REG_OST_CNTHBUF); > + recount = (u64)val1 | (u64)val2 << 32; > + > + /* > + * A wrong read will produce a result that is 1<<32 too high: the bottom > + * part from before overflow and the upper part from after overflow. > + * Therefore, the lower value of the two reads is the correct value. > + */ > + > + diff = (s64)(recount - count); > + if (unlikely(diff < 0)) > + count = recount; > + > + return count; > +} > + > +static int __init ingenic_ost_probe(struct platform_device *pdev) > +{ > + const struct ingenic_ost_soc_info *soc_info; > + struct device *dev = &pdev->dev; > + struct ingenic_ost *ost; > + struct clocksource *cs; > + unsigned long rate, flags; > + int err; > + > + soc_info = device_get_match_data(dev); > + if (!soc_info) > + return -EINVAL; > + > + ost = devm_kzalloc(dev, sizeof(*ost), GFP_KERNEL); > + if (!ost) > + return -ENOMEM; > + > + ost->map = dev_get_regmap(dev->parent, NULL); > + if (!ost->map) { > + dev_err(dev, "regmap not found\n"); > + return -EINVAL; > + } > + > + ost->clk = devm_clk_get(dev, "ost"); > + if (IS_ERR(ost->clk)) > + return PTR_ERR(ost->clk); > + > + err = clk_prepare_enable(ost->clk); > + if (err) > + return err; > + > + /* Clear counter high/low registers */ > + if (soc_info->is64bit) > + regmap_write(ost->map, TCU_REG_OST_CNTL, 0); > + regmap_write(ost->map, TCU_REG_OST_CNTH, 0); > + > + /* Don't reset counter at compare value. */ > + regmap_update_bits(ost->map, TCU_REG_OST_TCSR, > + TCU_OST_TCSR_MASK, TCU_OST_TCSR_CNT_MD); > + > + rate = clk_get_rate(ost->clk); > + > + /* Enable OST TCU channel */ > + regmap_write(ost->map, TCU_REG_TESR, BIT(TCU_OST_CHANNEL)); > + > + cs = &ost->cs; > + cs->name = "ingenic-ost"; > + cs->rating = 320; > + cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; > + > + if (soc_info->is64bit) { > + cs->mask = CLOCKSOURCE_MASK(64); > + cs->read = ingenic_ost_clocksource_read; > + } else { > + cs->mask = CLOCKSOURCE_MASK(32); > + cs->read = (u64 (*)(struct clocksource *))ingenic_ost_read_cnth; > + } > + > + err = clocksource_register_hz(cs, rate); > + if (err) { > + dev_err(dev, "clocksource registration failed: %d\n", err); > + clk_disable_unprepare(ost->clk); > + return err; > + } > + > + /* Cannot register a sched_clock with interrupts on */ > + local_irq_save(flags); > + if (soc_info->is64bit) > + sched_clock_register(ingenic_ost_read_cntl, 32, rate); > + else > + sched_clock_register(ingenic_ost_read_cnth, 32, rate); > + local_irq_restore(flags); > + > + return 0; > +} > + > +#ifdef CONFIG_PM_SLEEP > +static int ingenic_ost_suspend(struct device *dev) > +{ > + struct ingenic_ost *ost = dev_get_drvdata(dev); > + > + clk_disable(ost->clk); > + return 0; > +} > + > +static int ingenic_ost_resume(struct device *dev) > +{ > + struct ingenic_ost *ost = dev_get_drvdata(dev); > + > + return clk_enable(ost->clk); > +} > + > +static SIMPLE_DEV_PM_OPS(ingenic_ost_pm_ops, ingenic_ost_suspend, > + ingenic_ost_resume); > +#define INGENIC_OST_PM_OPS (&ingenic_ost_pm_ops) > +#else > +#define INGENIC_OST_PM_OPS NULL > +#endif /* CONFIG_PM_SUSPEND */ > + > +static const struct ingenic_ost_soc_info jz4725b_ost_soc_info = { > + .is64bit = false, > +}; > + > +static const struct ingenic_ost_soc_info jz4770_ost_soc_info = { > + .is64bit = true, > +}; > + > +static const struct of_device_id ingenic_ost_of_match[] = { > + { .compatible = "ingenic,jz4725b-ost", .data = &jz4725b_ost_soc_info, }, > + { .compatible = "ingenic,jz4770-ost", .data = &jz4770_ost_soc_info, }, > + { } > +}; > +MODULE_DEVICE_TABLE(of, ingenic_ost_of_match); > + > +static struct platform_driver ingenic_ost_driver = { > + .probe = ingenic_ost_probe, > + .driver = { > + .name = "ingenic-ost", > + .pm = INGENIC_OST_PM_OPS, > + .of_match_table = ingenic_ost_of_match, > + }, > +}; > +module_platform_driver(ingenic_ost_driver); > -- > 2.11.0 >
Hi Mathieu, Le mar. 14 août 2018 à 11:42, Mathieu Malaterre <malat@debian.org> a écrit : > On Thu, Aug 9, 2018 at 11:44 PM Paul Cercueil <paul@crapouillou.net> > wrote: >> >> From: Maarten ter Huurne <maarten@treewalker.org> >> >> OST is the OS Timer, a 64-bit timer/counter with buffered reading. >> >> SoCs before the JZ4770 had (if any) a 32-bit OST; the JZ4770 and >> JZ4780 have a 64-bit OST. >> >> This driver will register both a clocksource and a sched_clock to >> the >> system. > > With CONFIG_DEBUG_SECTION_MISMATCH=y here is what I see: > > MODPOST vmlinux.o > WARNING: vmlinux.o(.data+0x26600): Section mismatch in reference from > the variable ingenic_ost_driver to the function > .init.text:ingenic_ost_probe() > The variable ingenic_ost_driver references > the function __init ingenic_ost_probe() > If the reference is valid then annotate the > variable with __init* or __refdata (see linux/init.h) or name the > variable: > *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console > > WARNING: vmlinux.o(.data+0x26660): Section mismatch in reference from > the variable ingenic_tcu_driver to the function > .init.text:ingenic_tcu_probe() > The variable ingenic_tcu_driver references > the function __init ingenic_tcu_probe() > If the reference is valid then annotate the > variable with __init* or __refdata (see linux/init.h) or name the > variable: > *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console > > Thanks Right, I'll fix it in V7. Thanks! >> Signed-off-by: Maarten ter Huurne <maarten@treewalker.org> >> Signed-off-by: Paul Cercueil <paul@crapouillou.net> >> --- >> drivers/clocksource/Kconfig | 8 ++ >> drivers/clocksource/Makefile | 1 + >> drivers/clocksource/ingenic-ost.c | 208 >> ++++++++++++++++++++++++++++++++++++++ >> 3 files changed, 217 insertions(+) >> create mode 100644 drivers/clocksource/ingenic-ost.c >> >> v5: New patch >> >> v6: - Get rid of SoC IDs; pass pointer to ingenic_ost_soc_info as >> devicetree match data instead. >> - Use device_get_match_data() instead of the of_* variant >> - Handle error of dev_get_regmap() properly >> >> diff --git a/drivers/clocksource/Kconfig >> b/drivers/clocksource/Kconfig >> index 98f708208a8d..e855938c69f1 100644 >> --- a/drivers/clocksource/Kconfig >> +++ b/drivers/clocksource/Kconfig >> @@ -619,4 +619,12 @@ config INGENIC_TIMER >> help >> Support for the timer/counter unit of the Ingenic JZ SoCs. >> >> +config INGENIC_OST >> + bool "Ingenic JZ47xx Operating System Timer" >> + depends on MIPS || COMPILE_TEST >> + depends on COMMON_CLK >> + select INGENIC_TIMER >> + help >> + Support for the OS Timer of the Ingenic JZ4770 or similar >> SoC. >> + >> endmenu >> diff --git a/drivers/clocksource/Makefile >> b/drivers/clocksource/Makefile >> index 26877505d400..56ce37252944 100644 >> --- a/drivers/clocksource/Makefile >> +++ b/drivers/clocksource/Makefile >> @@ -75,6 +75,7 @@ obj-$(CONFIG_ASM9260_TIMER) += >> asm9260_timer.o >> obj-$(CONFIG_H8300_TMR8) += h8300_timer8.o >> obj-$(CONFIG_H8300_TMR16) += h8300_timer16.o >> obj-$(CONFIG_H8300_TPU) += h8300_tpu.o >> +obj-$(CONFIG_INGENIC_OST) += ingenic-ost.o >> obj-$(CONFIG_INGENIC_TIMER) += ingenic-timer.o >> obj-$(CONFIG_CLKSRC_ST_LPC) += clksrc_st_lpc.o >> obj-$(CONFIG_X86_NUMACHIP) += numachip.o >> diff --git a/drivers/clocksource/ingenic-ost.c >> b/drivers/clocksource/ingenic-ost.c >> new file mode 100644 >> index 000000000000..400d30656790 >> --- /dev/null >> +++ b/drivers/clocksource/ingenic-ost.c >> @@ -0,0 +1,208 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * JZ47xx SoCs TCU Operating System Timer driver >> + * >> + * Copyright (C) 2016 Maarten ter Huurne <maarten@treewalker.org> >> + * Copyright (C) 2018 Paul Cercueil <paul@crapouillou.net> >> + */ >> + >> +#include <linux/clk.h> >> +#include <linux/clocksource.h> >> +#include <linux/mfd/ingenic-tcu.h> >> +#include <linux/module.h> >> +#include <linux/platform_device.h> >> +#include <linux/pm.h> >> +#include <linux/regmap.h> >> +#include <linux/sched_clock.h> >> + >> +#include "ingenic-timer.h" >> + >> +#define TCU_OST_TCSR_MASK 0xc0 >> +#define TCU_OST_TCSR_CNT_MD BIT(15) >> + >> +#define TCU_OST_CHANNEL 15 >> + >> +struct ingenic_ost_soc_info { >> + bool is64bit; >> +}; >> + >> +struct ingenic_ost { >> + struct regmap *map; >> + struct clk *clk; >> + >> + struct clocksource cs; >> +}; >> + >> +static u64 notrace ingenic_ost_read_cntl(void) >> +{ >> + /* Bypass the regmap here as we must return as soon as >> possible */ >> + return readl(ingenic_tcu_base + TCU_REG_OST_CNTL); >> +} >> + >> +static u64 notrace ingenic_ost_read_cnth(void) >> +{ >> + /* Bypass the regmap here as we must return as soon as >> possible */ >> + return readl(ingenic_tcu_base + TCU_REG_OST_CNTH); >> +} >> + >> +static u64 notrace ingenic_ost_clocksource_read(struct clocksource >> *cs) >> +{ >> + u32 val1, val2; >> + u64 count, recount; >> + s64 diff; >> + >> + /* >> + * The buffering of the upper 32 bits of the timer prevents >> wrong >> + * results from the bottom 32 bits overflowing due to the >> timer ticking >> + * along. However, it does not prevent wrong results from >> simultaneous >> + * reads of the timer, which could reset the buffer >> mid-read. >> + * Since this kind of wrong read can happen only when the >> bottom bits >> + * overflow, there will be minutes between wrong reads, so >> if we read >> + * twice in succession, at least one of the reads will be >> correct. >> + */ >> + >> + /* Bypass the regmap here as we must return as soon as >> possible */ >> + val1 = readl(ingenic_tcu_base + TCU_REG_OST_CNTL); >> + val2 = readl(ingenic_tcu_base + TCU_REG_OST_CNTHBUF); >> + count = (u64)val1 | (u64)val2 << 32; >> + >> + val1 = readl(ingenic_tcu_base + TCU_REG_OST_CNTL); >> + val2 = readl(ingenic_tcu_base + TCU_REG_OST_CNTHBUF); >> + recount = (u64)val1 | (u64)val2 << 32; >> + >> + /* >> + * A wrong read will produce a result that is 1<<32 too >> high: the bottom >> + * part from before overflow and the upper part from after >> overflow. >> + * Therefore, the lower value of the two reads is the >> correct value. >> + */ >> + >> + diff = (s64)(recount - count); >> + if (unlikely(diff < 0)) >> + count = recount; >> + >> + return count; >> +} >> + >> +static int __init ingenic_ost_probe(struct platform_device *pdev) >> +{ >> + const struct ingenic_ost_soc_info *soc_info; >> + struct device *dev = &pdev->dev; >> + struct ingenic_ost *ost; >> + struct clocksource *cs; >> + unsigned long rate, flags; >> + int err; >> + >> + soc_info = device_get_match_data(dev); >> + if (!soc_info) >> + return -EINVAL; >> + >> + ost = devm_kzalloc(dev, sizeof(*ost), GFP_KERNEL); >> + if (!ost) >> + return -ENOMEM; >> + >> + ost->map = dev_get_regmap(dev->parent, NULL); >> + if (!ost->map) { >> + dev_err(dev, "regmap not found\n"); >> + return -EINVAL; >> + } >> + >> + ost->clk = devm_clk_get(dev, "ost"); >> + if (IS_ERR(ost->clk)) >> + return PTR_ERR(ost->clk); >> + >> + err = clk_prepare_enable(ost->clk); >> + if (err) >> + return err; >> + >> + /* Clear counter high/low registers */ >> + if (soc_info->is64bit) >> + regmap_write(ost->map, TCU_REG_OST_CNTL, 0); >> + regmap_write(ost->map, TCU_REG_OST_CNTH, 0); >> + >> + /* Don't reset counter at compare value. */ >> + regmap_update_bits(ost->map, TCU_REG_OST_TCSR, >> + TCU_OST_TCSR_MASK, TCU_OST_TCSR_CNT_MD); >> + >> + rate = clk_get_rate(ost->clk); >> + >> + /* Enable OST TCU channel */ >> + regmap_write(ost->map, TCU_REG_TESR, BIT(TCU_OST_CHANNEL)); >> + >> + cs = &ost->cs; >> + cs->name = "ingenic-ost"; >> + cs->rating = 320; >> + cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; >> + >> + if (soc_info->is64bit) { >> + cs->mask = CLOCKSOURCE_MASK(64); >> + cs->read = ingenic_ost_clocksource_read; >> + } else { >> + cs->mask = CLOCKSOURCE_MASK(32); >> + cs->read = (u64 (*)(struct clocksource >> *))ingenic_ost_read_cnth; >> + } >> + >> + err = clocksource_register_hz(cs, rate); >> + if (err) { >> + dev_err(dev, "clocksource registration failed: >> %d\n", err); >> + clk_disable_unprepare(ost->clk); >> + return err; >> + } >> + >> + /* Cannot register a sched_clock with interrupts on */ >> + local_irq_save(flags); >> + if (soc_info->is64bit) >> + sched_clock_register(ingenic_ost_read_cntl, 32, >> rate); >> + else >> + sched_clock_register(ingenic_ost_read_cnth, 32, >> rate); >> + local_irq_restore(flags); >> + >> + return 0; >> +} >> + >> +#ifdef CONFIG_PM_SLEEP >> +static int ingenic_ost_suspend(struct device *dev) >> +{ >> + struct ingenic_ost *ost = dev_get_drvdata(dev); >> + >> + clk_disable(ost->clk); >> + return 0; >> +} >> + >> +static int ingenic_ost_resume(struct device *dev) >> +{ >> + struct ingenic_ost *ost = dev_get_drvdata(dev); >> + >> + return clk_enable(ost->clk); >> +} >> + >> +static SIMPLE_DEV_PM_OPS(ingenic_ost_pm_ops, ingenic_ost_suspend, >> + ingenic_ost_resume); >> +#define INGENIC_OST_PM_OPS (&ingenic_ost_pm_ops) >> +#else >> +#define INGENIC_OST_PM_OPS NULL >> +#endif /* CONFIG_PM_SUSPEND */ >> + >> +static const struct ingenic_ost_soc_info jz4725b_ost_soc_info = { >> + .is64bit = false, >> +}; >> + >> +static const struct ingenic_ost_soc_info jz4770_ost_soc_info = { >> + .is64bit = true, >> +}; >> + >> +static const struct of_device_id ingenic_ost_of_match[] = { >> + { .compatible = "ingenic,jz4725b-ost", .data = >> &jz4725b_ost_soc_info, }, >> + { .compatible = "ingenic,jz4770-ost", .data = >> &jz4770_ost_soc_info, }, >> + { } >> +}; >> +MODULE_DEVICE_TABLE(of, ingenic_ost_of_match); >> + >> +static struct platform_driver ingenic_ost_driver = { >> + .probe = ingenic_ost_probe, >> + .driver = { >> + .name = "ingenic-ost", >> + .pm = INGENIC_OST_PM_OPS, >> + .of_match_table = ingenic_ost_of_match, >> + }, >> +}; >> +module_platform_driver(ingenic_ost_driver); >> -- >> 2.11.0 >>