[v4,0/8] Tegra20 External Memory Controller driver

Hello,

Couple years ago the Tegra20 EMC driver was removed from the kernel
due to incompatible changes in the Tegra's clock driver. This patchset
introduces a modernized EMC driver. Currently the sole purpose of the
driver is to initialize DRAM frequency to maximum rate during of the
kernels boot-up. Later we may consider implementing dynamic memory
frequency scaling, utilizing functionality provided by this driver.

Changelog:

v4:
	- Fixed "bad of_node_put()" error which was revealed by enabling
	  some extra kernel debug config options.

	- The "emc-table" DT nodes are now parsed starting from the "emc"
	  node instead of the DT root.

	- Adjusted code comment in the "Turn EMC clock gate into divider"
	  patch as was suggested by Stephen Boyd to the v3.

v3:
	- Handle "nvidia,use-ram-code" DT property, its handling was missed
	  in the previous versions.

	- Honor "emc-tables" DT node naming which is explicitly specified
	  in the DT binding, also was missed in the previous versions.

	- Two new DT binding patches: one adds the EMC clock property,
	  other relocates the binding doc file to the appropriate directory.
	  One new patch that adds EMC clock property to the DTS file.

	- Addressed v2 review comments from Thierry Reding. Driver does not
	  preserve backwards compatibility with older device tree binding.

	- The PLL_M and PLL_P clocks are kept internal to the driver because
	  after some more considering I couldn't find a really good reason why
	  these clocks should be in the device tree.

	- Some minor cleanups and fixes in the drivers code.

v2:
	- Minor code cleanups like consistent use of writel_relaxed instead
	  of non-relaxed version, reworded error messages, etc.

	- Factored out use_pllm_ud bit checking into a standalone patch for
	  consistency.

Dmitry Osipenko (8):
  dt: bindings: tegra20-emc: Document interrupt property
  dt: bindings: tegra20-emc: Document clock property
  dt: bindings: Move tegra20-emc binding to memory-controllers directory
  ARM: dts: tegra20: Add interrupt entry to External Memory Controller
  ARM: dts: tegra20: Add clock entry to External Memory Controller
  clk: tegra20: Turn EMC clock gate into divider
  clk: tegra20: Check whether direct PLLM sourcing is turned off for EMC
  memory: tegra: Introduce Tegra20 EMC driver

 .../nvidia,tegra20-emc.txt                    |   4 +
 arch/arm/boot/dts/tegra20.dtsi                |   2 +
 drivers/clk/tegra/clk-tegra20.c               |  46 +-
 drivers/memory/tegra/Kconfig                  |  10 +
 drivers/memory/tegra/Makefile                 |   1 +
 drivers/memory/tegra/tegra20-emc.c            | 575 ++++++++++++++++++
 6 files changed, 628 insertions(+), 10 deletions(-)
 rename Documentation/devicetree/bindings/{arm/tegra => memory-controllers}/nvidia,tegra20-emc.txt (95%)
 create mode 100644 drivers/memory/tegra/tegra20-emc.c

On Thursday, 19 July 2018 16:21:30 MSK Dmitry Osipenko wrote:
> Kernel should never gate the EMC clock as it causes immediate lockup, so
> removing clk-gate functionality doesn't affect anything. Turning EMC clk
> gate into divider allows to implement glitch-less EMC scaling, avoiding
> reparenting to a backup clock.
> 
> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> ---
>  drivers/clk/tegra/clk-tegra20.c | 36 ++++++++++++++++++++++++---------
>  1 file changed, 26 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/clk/tegra/clk-tegra20.c
> b/drivers/clk/tegra/clk-tegra20.c index cc857d4d4a86..ebea97016d58 100644
> --- a/drivers/clk/tegra/clk-tegra20.c
> +++ b/drivers/clk/tegra/clk-tegra20.c
> @@ -578,7 +578,6 @@ static struct tegra_clk tegra20_clks[tegra_clk_max]
> __initdata = { [tegra_clk_afi] = { .dt_id = TEGRA20_CLK_AFI, .present =
> true }, [tegra_clk_fuse] = { .dt_id = TEGRA20_CLK_FUSE, .present = true },
> [tegra_clk_kfuse] = { .dt_id = TEGRA20_CLK_KFUSE, .present = true },
> -	[tegra_clk_emc] = { .dt_id = TEGRA20_CLK_EMC, .present = true }, };
> 
>  static unsigned long tegra20_clk_measure_input_freq(void)
> @@ -799,6 +798,31 @@ static struct tegra_periph_init_data
> tegra_periph_nodiv_clk_list[] = {
> TEGRA_INIT_DATA_NODIV("disp2",	mux_pllpdc_clkm, CLK_SOURCE_DISP2, 30, 2,
> 26,  0, TEGRA20_CLK_DISP2), };
> 
> +static void __init tegra20_emc_clk_init(void)
> +{
> +	struct clk *clk;
> +
> +	clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
> +			       ARRAY_SIZE(mux_pllmcp_clkm),
> +			       CLK_SET_RATE_NO_REPARENT,
> +			       clk_base + CLK_SOURCE_EMC,
> +			       30, 2, 0, &emc_lock);
> +
> +	clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
> +				    &emc_lock);
> +	clks[TEGRA20_CLK_MC] = clk;
> +
> +	/*
> +	 * Note that 'emc_mux' source and 'emc' rate shouldn't be changed at
> +	 * the same time due to a HW bug, this won't happen because we're
> +	 * defining 'emc_mux' and 'emc' as distinct clocks.
> +	 */
> +	clk = clk_register_divider(NULL, "emc", "emc_mux", CLK_IS_CRITICAL,
> +				   clk_base + CLK_SOURCE_EMC, 0, 7,
> +				   0, &emc_lock);

Actually this is wrong. The divisor is 8 bits-wide and "lsb denote 0.5x", so 
this is a 7.1 divider. I'll prepare v5.



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