| Message ID | 20180316140215.28663-1-icenowy@aosc.io |
|---|---|
| Headers | show |
| Series | Initial Allwinner H6 support | expand |
On Fri, Mar 16, 2018 at 10:02:07PM +0800, Icenowy Zheng wrote: > As the new H6 SoC has holes in the IRQ registers, refactor the IRQ > related register function for getting the full pinctrl desc structure. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Maxime
On Fri, Mar 16, 2018 at 10:02:08PM +0800, Icenowy Zheng wrote: > The Allwinner H6 SoC have its pin controllers with the first IRQ-capable > GPIO bank at IRQ bank 1 and the second bank at IRQ bank 5. Some > refactors in the sunxi pinctrl framework are needed. > > This commit introduces a IRQ bank conversion function, which replaces > the "(bank_base + bank)" code in IRQ register access. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Thanks! Maxime
On Fri, Mar 16, 2018 at 10:02:09PM +0800, Icenowy Zheng wrote: > The Allwinner H6 SoC have its pin controllers with the first IRQ-capable > GPIO bank at IRQ bank 1 and the second bank at IRQ bank 5. > > Change the current code that uses IRQ bank base to a IRQ bank map, in > order to support the case that holes exist among IRQ banks. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Thanks! Maxime
On Fri, Mar 16, 2018 at 10:02:06PM +0800, Icenowy Zheng wrote: > This patchset adds initial support for the Allwinner H6 SoC. > > It's quite different from earlier Allwinner SoCs. For example, the > memory map is refactored, and the CCU is rearranged. It's also the first > Allwinner SoC with PCI Express interface (although the implementation > of the PCI Express controller is broken), and the second one with USB > 3.0 (the first one is A80). > > This patchset adds the most basical support for it, including the main pin > controller, the main CCU and the basical device tree. > > Icenowy Zheng (9): > pinctrl: sunxi: refactor irq related register function to have desc > pinctrl: sunxi: introduce IRQ bank conversion function > pinctrl: sunxi: change irq_bank_base to irq_bank_map > pinctrl: sunxi: add support for the Allwinner H6 main pin controller > clk: sunxi-ng: Support fixed post-dividers on NKMP style clocks > dt-bindings: add device tree binding for Allwinner H6 main CCU > clk: sunxi-ng: add support for the Allwinner H6 CCU > arm64: allwinner: h6: add the basical Allwinner H6 DTSI file > arm64: allwinner: h6: add support for Pine H64 board Applied the !pinctrl patches. Thanks! Maxime
于 2018年3月19日 GMT+08:00 上午4:17:44, Maxime Ripard <maxime.ripard@bootlin.com> 写到: >On Fri, Mar 16, 2018 at 10:02:06PM +0800, Icenowy Zheng wrote: >> This patchset adds initial support for the Allwinner H6 SoC. >> >> It's quite different from earlier Allwinner SoCs. For example, the >> memory map is refactored, and the CCU is rearranged. It's also the >first >> Allwinner SoC with PCI Express interface (although the implementation >> of the PCI Express controller is broken), and the second one with USB >> 3.0 (the first one is A80). >> >> This patchset adds the most basical support for it, including the >main pin >> controller, the main CCU and the basical device tree. >> >> Icenowy Zheng (9): >> pinctrl: sunxi: refactor irq related register function to have desc >> pinctrl: sunxi: introduce IRQ bank conversion function >> pinctrl: sunxi: change irq_bank_base to irq_bank_map >> pinctrl: sunxi: add support for the Allwinner H6 main pin >controller >> clk: sunxi-ng: Support fixed post-dividers on NKMP style clocks >> dt-bindings: add device tree binding for Allwinner H6 main CCU >> clk: sunxi-ng: add support for the Allwinner H6 CCU >> arm64: allwinner: h6: add the basical Allwinner H6 DTSI file >> arm64: allwinner: h6: add support for Pine H64 board > >Applied the !pinctrl patches. Oops, one clock (CLK_HDMI_SLOW) is missing in the CCU driver, as Jernej pointed out. Should I send a patch that fix it? > >Thanks! >Maxime -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Mon, Mar 19, 2018 at 09:28:23AM +0800, Icenowy Zheng wrote: > > > 于 2018年3月19日 GMT+08:00 上午4:17:44, Maxime Ripard <maxime.ripard@bootlin.com> 写到: > >On Fri, Mar 16, 2018 at 10:02:06PM +0800, Icenowy Zheng wrote: > >> This patchset adds initial support for the Allwinner H6 SoC. > >> > >> It's quite different from earlier Allwinner SoCs. For example, the > >> memory map is refactored, and the CCU is rearranged. It's also the > >first > >> Allwinner SoC with PCI Express interface (although the implementation > >> of the PCI Express controller is broken), and the second one with USB > >> 3.0 (the first one is A80). > >> > >> This patchset adds the most basical support for it, including the > >main pin > >> controller, the main CCU and the basical device tree. > >> > >> Icenowy Zheng (9): > >> pinctrl: sunxi: refactor irq related register function to have desc > >> pinctrl: sunxi: introduce IRQ bank conversion function > >> pinctrl: sunxi: change irq_bank_base to irq_bank_map > >> pinctrl: sunxi: add support for the Allwinner H6 main pin > >controller > >> clk: sunxi-ng: Support fixed post-dividers on NKMP style clocks > >> dt-bindings: add device tree binding for Allwinner H6 main CCU > >> clk: sunxi-ng: add support for the Allwinner H6 CCU > >> arm64: allwinner: h6: add the basical Allwinner H6 DTSI file > >> arm64: allwinner: h6: add support for Pine H64 board > > > >Applied the !pinctrl patches. > > Oops, one clock (CLK_HDMI_SLOW) is missing in the CCU > driver, as Jernej pointed out. > > Should I send a patch that fix it? Yes, please. Thanks! Maxime
On Fri, Mar 16, 2018 at 3:02 PM, Icenowy Zheng <icenowy@aosc.io> wrote: > As the new H6 SoC has holes in the IRQ registers, refactor the IRQ > related register function for getting the full pinctrl desc structure. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > --- > Changes in v4: > - Adjusted parameter sequence. Patch applied with Maxime's ACK. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Fri, Mar 16, 2018 at 3:02 PM, Icenowy Zheng <icenowy@aosc.io> wrote: > The Allwinner H6 SoC have its pin controllers with the first IRQ-capable > GPIO bank at IRQ bank 1 and the second bank at IRQ bank 5. Some > refactors in the sunxi pinctrl framework are needed. > > This commit introduces a IRQ bank conversion function, which replaces > the "(bank_base + bank)" code in IRQ register access. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > --- > Extracted in v4. Patch applied with Maxime's ACK. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Fri, Mar 16, 2018 at 3:02 PM, Icenowy Zheng <icenowy@aosc.io> wrote: > The Allwinner H6 SoC have its pin controllers with the first IRQ-capable > GPIO bank at IRQ bank 1 and the second bank at IRQ bank 5. > > Change the current code that uses IRQ bank base to a IRQ bank map, in > order to support the case that holes exist among IRQ banks. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > --- > Extracted in v4. Patch applied with Maxime's ACK. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Fri, Mar 16, 2018 at 3:02 PM, Icenowy Zheng <icenowy@aosc.io> wrote: > This patchset adds initial support for the Allwinner H6 SoC. > > It's quite different from earlier Allwinner SoCs. For example, the > memory map is refactored, and the CCU is rearranged. It's also the first > Allwinner SoC with PCI Express interface (although the implementation > of the PCI Express controller is broken), and the second one with USB > 3.0 (the first one is A80). > > This patchset adds the most basical support for it, including the main pin > controller, the main CCU and the basical device tree. > > Icenowy Zheng (9): > pinctrl: sunxi: refactor irq related register function to have desc > pinctrl: sunxi: introduce IRQ bank conversion function > pinctrl: sunxi: change irq_bank_base to irq_bank_map > pinctrl: sunxi: add support for the Allwinner H6 main pin controller I applied these pinctrl patches for v4.17 so anything dependent on that can now be merged. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html