| Message ID | 1695218113-31198-1-git-send-email-quic_msarkar@quicinc.com |
|---|---|
| Headers | show |
| Series | arm64: qcom: sa8775p: add support for EP PCIe | expand |
On 9/20/23 15:55, Mrinmay Sarkar wrote: > Add support for SA8775P SoC to the Qualcomm PCIe Endpoint Controller > driver. > > Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com> > --- This compatible does not bring anything new to the table on its own. Please create a fallback compatible, document it in the bindings and use that. See [1] and [2] for example. Konrad [1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-repeater.yaml?h=next-20230920 [2] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/qcom/pm7550ba.dtsi?h=next-20230920#n65
On 9/20/23 15:55, Mrinmay Sarkar wrote: > Add support for Qualcomm Snapdragon SA8775P SoC to the EPF driver. > SA8775P has the PID (0x0306) and supports HDMA. Currently, it has > no fixed PCI class, so it is being advertised as "PCI_CLASS_OTHERS". > > Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com> > --- > drivers/pci/endpoint/functions/pci-epf-mhi.c | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/drivers/pci/endpoint/functions/pci-epf-mhi.c b/drivers/pci/endpoint/functions/pci-epf-mhi.c > index b7b9d3e..4b349fd 100644 > --- a/drivers/pci/endpoint/functions/pci-epf-mhi.c > +++ b/drivers/pci/endpoint/functions/pci-epf-mhi.c > @@ -114,6 +114,23 @@ static const struct pci_epf_mhi_ep_info sm8450_info = { > .flags = MHI_EPF_USE_DMA, > }; > > +static struct pci_epf_header sa8775p_header = { const? Konrad
On Wed, Sep 20, 2023 at 04:24:30PM +0200, Konrad Dybcio wrote: > > > On 9/20/23 15:55, Mrinmay Sarkar wrote: > > Add support for SA8775P SoC to the Qualcomm PCIe Endpoint Controller > > driver. > > > > Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com> > > --- > This compatible does not bring anything new to the table > on its own. Please create a fallback compatible, document it > in the bindings and use that. See [1] and [2] for example. > Ack. - Mani > Konrad > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-repeater.yaml?h=next-20230920 > > [2] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/qcom/pm7550ba.dtsi?h=next-20230920#n65
On Wed, Sep 20, 2023 at 07:25:10PM +0530, Mrinmay Sarkar wrote: > Add support for dual lane end point mode PHY found on sa8755p platform. > > Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com> > --- > drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 41 ++++++++++++++++++++++ > drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h | 2 ++ > drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v5.h | 1 + > 3 files changed, 44 insertions(+) > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c > index a63ca74..351047c 100644 > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c > @@ -2147,6 +2147,38 @@ static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl[] > QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), > }; > > +static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl[] = { > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02), > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07), > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27), > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a), > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17), > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19), > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00), > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03), > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00), > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01), > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01), > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CMN_MODE, 0x14), > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04), > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff), > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09), > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19), > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28), > +}; > + > +static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_ep_pcs_misc_tbl[] = { > + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08), > +}; > + > +static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl[] = { > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_INSIG_MX_CTRL7, 0x00), > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_INSIG_SW_CTRL7, 0x00), > +}; > + > struct qmp_pcie_offsets { > u16 serdes; > u16 pcs; > @@ -3043,6 +3075,15 @@ static const struct qmp_phy_cfg sa8775p_qmp_gen4x2_pciephy_cfg = { > .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl), > }, > > + .tbls_ep = &(const struct qmp_phy_cfg_tbls) { > + .serdes = sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl, > + .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl), > + .pcs_misc = sa8775p_qmp_gen4_pcie_ep_pcs_misc_tbl, > + .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_ep_pcs_misc_tbl), > + .pcs = sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl, > + .pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl), > + }, > + > .reset_list = sdm845_pciephy_reset_l, > .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), > .vreg_list = qmp_phy_vreg_l, > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h > index 36cc80b..2b33dc7 100644 > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h > @@ -30,5 +30,7 @@ > #define QPHY_V5_PCS_EQ_CONFIG2 0x1e0 > #define QPHY_V5_PCS_EQ_CONFIG3 0x1e4 > #define QPHY_V5_PCS_EQ_CONFIG5 0x1ec > +#define QPHY_V5_PCS_INSIG_MX_CTRL7 0x07c > +#define QPHY_V5_PCS_INSIG_SW_CTRL7 0x060 Sort the defines please, here and below. - Mani > > #endif > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v5.h > index c8afdf7..ad587c8 100644 > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v5.h > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v5.h > @@ -120,5 +120,6 @@ > #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 > #define QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc > #define QSERDES_V5_COM_RESERVED_1 0x1c0 > +#define QSERDES_V5_COM_PLL_CMN_MODE 0x1a0 > > #endif > -- > 2.7.4 >
On Wed, Sep 20, 2023 at 07:25:11PM +0530, Mrinmay Sarkar wrote: > Add support for Qualcomm Snapdragon SA8775P SoC to the EPF driver. > SA8775P has the PID (0x0306) and supports HDMA. Currently, it has > no fixed PCI class, so it is being advertised as "PCI_CLASS_OTHERS". > > Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com> > --- > drivers/pci/endpoint/functions/pci-epf-mhi.c | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/drivers/pci/endpoint/functions/pci-epf-mhi.c b/drivers/pci/endpoint/functions/pci-epf-mhi.c > index b7b9d3e..4b349fd 100644 > --- a/drivers/pci/endpoint/functions/pci-epf-mhi.c > +++ b/drivers/pci/endpoint/functions/pci-epf-mhi.c > @@ -114,6 +114,23 @@ static const struct pci_epf_mhi_ep_info sm8450_info = { > .flags = MHI_EPF_USE_DMA, > }; > > +static struct pci_epf_header sa8775p_header = { static const struct... > + .vendorid = PCI_VENDOR_ID_QCOM, > + .deviceid = 0x0306, Why are you not using a distinct device id? - Mani > + .baseclass_code = PCI_CLASS_OTHERS, > + .interrupt_pin = PCI_INTERRUPT_INTA, > +}; > + > +static const struct pci_epf_mhi_ep_info sa8775p_info = { > + .config = &mhi_v1_config, > + .epf_header = &sa8775p_header, > + .bar_num = BAR_0, > + .epf_flags = PCI_BASE_ADDRESS_MEM_TYPE_32, > + .msi_count = 32, > + .mru = 0x8000, > + .flags = MHI_EPF_USE_DMA, > +}; > + > struct pci_epf_mhi { > const struct pci_epc_features *epc_features; > const struct pci_epf_mhi_ep_info *info; > @@ -677,6 +694,7 @@ static int pci_epf_mhi_probe(struct pci_epf *epf, > } > > static const struct pci_epf_device_id pci_epf_mhi_ids[] = { > + { .name = "sa8775p", .driver_data = (kernel_ulong_t)&sa8775p_info }, > { .name = "sdx55", .driver_data = (kernel_ulong_t)&sdx55_info }, > { .name = "sm8450", .driver_data = (kernel_ulong_t)&sm8450_info }, > {}, > -- > 2.7.4 >
On Wed, Sep 20, 2023 at 07:25:12PM +0530, Mrinmay Sarkar wrote: > Add ep pcie dtsi node for pcie0 controller found on sa8775p platform. > It would be good to add more info in the commit message, like PCIe Gen, lane info, IP revision etc... > Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com> > --- > arch/arm64/boot/dts/qcom/sa8775p.dtsi | 45 +++++++++++++++++++++++++++++++++++ > 1 file changed, 45 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > index 9f4f58e8..5571131 100644 > --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi > +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > @@ -2600,4 +2600,49 @@ > > status = "disabled"; > }; > + > + pcie0_ep: pcie-ep@1c00000 { > + compatible = "qcom,sa8775p-pcie-ep"; > + reg = <0x0 0x01c00000 0x0 0x3000>, > + <0x0 0x40000000 0x0 0xf20>, > + <0x0 0x40000f20 0x0 0xa8>, > + <0x0 0x40001000 0x0 0x4000>, > + <0x0 0x40200000 0x0 0x100000>, > + <0x0 0x01c03000 0x0 0x1000>, > + <0x0 0x40005000 0x0 0x2000>; > + reg-names = "parf", "dbi", "elbi", "atu", "addr_space", > + "mmio", "dma"; > + > + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, > + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, > + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, > + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, > + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; > + > + clock-names = "aux", > + "cfg", > + "bus_master", > + "bus_slave", > + "slave_q2a"; > + > + interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>; > + > + interrupt-names = "global", "doorbell", "dma"; > + > + interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; > + interconnect-names = "pcie-mem", "cpu-pcie"; > + Don't you need iommu property? > + resets = <&gcc GCC_PCIE_0_BCR>; > + reset-names = "core"; > + power-domains = <&gcc PCIE_0_GDSC>; > + phys = <&pcie0_phy>; > + phy-names = "pciephy"; > + max-link-speed = <3>; Gen 3? > + num-lanes = <2>; Only 2 lanes? Or the other one has 4 lanes? - Mani > + > + status = "disabled"; > + }; > }; > -- > 2.7.4 >
On 9/21/2023 2:10 PM, Manivannan Sadhasivam wrote: > On Wed, Sep 20, 2023 at 07:25:11PM +0530, Mrinmay Sarkar wrote: >> Add support for Qualcomm Snapdragon SA8775P SoC to the EPF driver. >> SA8775P has the PID (0x0306) and supports HDMA. Currently, it has >> no fixed PCI class, so it is being advertised as "PCI_CLASS_OTHERS". >> >> Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com> >> --- >> drivers/pci/endpoint/functions/pci-epf-mhi.c | 18 ++++++++++++++++++ >> 1 file changed, 18 insertions(+) >> >> diff --git a/drivers/pci/endpoint/functions/pci-epf-mhi.c b/drivers/pci/endpoint/functions/pci-epf-mhi.c >> index b7b9d3e..4b349fd 100644 >> --- a/drivers/pci/endpoint/functions/pci-epf-mhi.c >> +++ b/drivers/pci/endpoint/functions/pci-epf-mhi.c >> @@ -114,6 +114,23 @@ static const struct pci_epf_mhi_ep_info sm8450_info = { >> .flags = MHI_EPF_USE_DMA, >> }; >> >> +static struct pci_epf_header sa8775p_header = { > static const struct... > >> + .vendorid = PCI_VENDOR_ID_QCOM, >> + .deviceid = 0x0306, > Why are you not using a distinct device id? > > - Mani distinct device id for EP is not created yet as of now we are reusing this. Will update once device id is decided. Thanks, Mrinmay >> + .baseclass_code = PCI_CLASS_OTHERS, >> + .interrupt_pin = PCI_INTERRUPT_INTA, >> +}; >> + >> +static const struct pci_epf_mhi_ep_info sa8775p_info = { >> + .config = &mhi_v1_config, >> + .epf_header = &sa8775p_header, >> + .bar_num = BAR_0, >> + .epf_flags = PCI_BASE_ADDRESS_MEM_TYPE_32, >> + .msi_count = 32, >> + .mru = 0x8000, >> + .flags = MHI_EPF_USE_DMA, >> +}; >> + >> struct pci_epf_mhi { >> const struct pci_epc_features *epc_features; >> const struct pci_epf_mhi_ep_info *info; >> @@ -677,6 +694,7 @@ static int pci_epf_mhi_probe(struct pci_epf *epf, >> } >> >> static const struct pci_epf_device_id pci_epf_mhi_ids[] = { >> + { .name = "sa8775p", .driver_data = (kernel_ulong_t)&sa8775p_info }, >> { .name = "sdx55", .driver_data = (kernel_ulong_t)&sdx55_info }, >> { .name = "sm8450", .driver_data = (kernel_ulong_t)&sm8450_info }, >> {}, >> -- >> 2.7.4 >>
On 9/21/2023 3:18 PM, Manivannan Sadhasivam wrote: > On Wed, Sep 20, 2023 at 07:25:12PM +0530, Mrinmay Sarkar wrote: >> Add ep pcie dtsi node for pcie0 controller found on sa8775p platform. >> > It would be good to add more info in the commit message, like PCIe Gen, lane > info, IP revision etc... > >> Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 45 +++++++++++++++++++++++++++++++++++ >> 1 file changed, 45 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi >> index 9f4f58e8..5571131 100644 >> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi >> @@ -2600,4 +2600,49 @@ >> >> status = "disabled"; >> }; >> + >> + pcie0_ep: pcie-ep@1c00000 { >> + compatible = "qcom,sa8775p-pcie-ep"; >> + reg = <0x0 0x01c00000 0x0 0x3000>, >> + <0x0 0x40000000 0x0 0xf20>, >> + <0x0 0x40000f20 0x0 0xa8>, >> + <0x0 0x40001000 0x0 0x4000>, >> + <0x0 0x40200000 0x0 0x100000>, >> + <0x0 0x01c03000 0x0 0x1000>, >> + <0x0 0x40005000 0x0 0x2000>; >> + reg-names = "parf", "dbi", "elbi", "atu", "addr_space", >> + "mmio", "dma"; >> + >> + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, >> + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, >> + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, >> + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, >> + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; >> + >> + clock-names = "aux", >> + "cfg", >> + "bus_master", >> + "bus_slave", >> + "slave_q2a"; >> + >> + interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>; >> + >> + interrupt-names = "global", "doorbell", "dma"; >> + >> + interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; >> + interconnect-names = "pcie-mem", "cpu-pcie"; >> + > Don't you need iommu property? > >> + resets = <&gcc GCC_PCIE_0_BCR>; >> + reset-names = "core"; >> + power-domains = <&gcc PCIE_0_GDSC>; >> + phys = <&pcie0_phy>; >> + phy-names = "pciephy"; >> + max-link-speed = <3>; > Gen 3? there is some stability issue with gen4 so going with gen3 as of now. Will update once issue is resolved. Thanks, Mrinmay >> + num-lanes = <2>; > Only 2 lanes? Or the other one has 4 lanes? > > - Mani pcie0 has lane2 and pcie1 has lane4 configuration. Thanks, Mrinmay >> + >> + status = "disabled"; >> + }; >> }; >> -- >> 2.7.4 >>
On 10/11/23 12:44, Mrinmay Sarkar wrote: > > On 9/21/2023 3:18 PM, Manivannan Sadhasivam wrote: >> On Wed, Sep 20, 2023 at 07:25:12PM +0530, Mrinmay Sarkar wrote: >>> Add ep pcie dtsi node for pcie0 controller found on sa8775p platform. >>> >> It would be good to add more info in the commit message, like PCIe >> Gen, lane >> info, IP revision etc... >> >>> Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com> >>> --- [...] >>> + max-link-speed = <3>; >> Gen 3? > there is some stability issue with gen4 so going with gen3 as of now. > Will update once issue is resolved. That's something that should have definitely been mentioned in the commit message.. Please try resolving this first, if it ends up requiring bindings changes (missing clocks or whatever), it will be a pain. Konrad
On 9/20/2023 7:54 PM, Konrad Dybcio wrote: > > > On 9/20/23 15:55, Mrinmay Sarkar wrote: >> Add support for SA8775P SoC to the Qualcomm PCIe Endpoint Controller >> driver. >> >> Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com> >> --- > This compatible does not bring anything new to the table > on its own. Please create a fallback compatible, document it > in the bindings and use that. See [1] and [2] for example. > > Konrad > > [1] > https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-repeater.yaml?h=next-20230920 > > [2] > https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/qcom/pm7550ba.dtsi?h=next-20230920#n65 Hi Konrad, yes as of now this compatible does not bring anything new to the table. recently we got additional feature regarding cache coherency for sa8775p for that we need to add change only for sa8775p. that's why we need to add the compatible for sa8775p. and I will be uploading patch for that in some days. Thanks, Mrinmay