| Message ID | 1694670204-11515-1-git-send-email-quic_taozha@quicinc.com |
|---|---|
| Headers | show |
| Series | Add support to configure TPDM DSB subunit | expand |
On 14/09/2023 06:43, Tao Zhang wrote: > Add the nodes for DSB subunit MSR(mux select register) support. > The TPDM MSR (mux select register) interface is an optional > interface and associated bank of registers per TPDM subunit. > The intent of mux select registers is to control muxing structures > driving the TPDM’s’ various subunit interfaces. > > Signed-off-by: Tao Zhang <quic_taozha@quicinc.com> > --- > .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 8 +++ > drivers/hwtracing/coresight/coresight-tpdm.c | 81 ++++++++++++++++++++++ > drivers/hwtracing/coresight/coresight-tpdm.h | 12 ++++ > 3 files changed, 101 insertions(+) > > diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm > index 1f20a3f..f07218e 100644 > --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm > +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm > @@ -162,3 +162,11 @@ Description: > Accepts only one of the 2 values - 0 or 1. > 0 : Set the DSB pattern type to value. > 1 : Set the DSB pattern type to toggle. > + > +What: /sys/bus/coresight/devices/<tpdm-name>/dsb_msr/msr[0:31] > +Date: March 2023 > +KernelVersion 6.7 > +Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com> > +Description: > + (RW) Set/Get the MSR(mux select register) for the DSB subunit > + TPDM. > diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c > index 7acc220..ea29e05 100644 > --- a/drivers/hwtracing/coresight/coresight-tpdm.c > +++ b/drivers/hwtracing/coresight/coresight-tpdm.c > @@ -61,6 +61,11 @@ static ssize_t tpdm_simple_dataset_show(struct device *dev, > return -EINVAL; > return sysfs_emit(buf, "0x%x\n", > drvdata->dsb->patt_mask[tpdm_attr->idx]); > + case DSB_MSR: > + if (tpdm_attr->idx >= drvdata->dsb_msr_num) > + return -EINVAL; > + return sysfs_emit(buf, "0x%x\n", > + drvdata->dsb->msr[tpdm_attr->idx]); > } > return -EINVAL; > } > @@ -107,6 +112,12 @@ static ssize_t tpdm_simple_dataset_store(struct device *dev, > else > ret = -EINVAL; > break; > + case DSB_MSR: > + if (tpdm_attr->idx < drvdata->dsb_msr_num) > + drvdata->dsb->msr[tpdm_attr->idx] = val; > + else > + ret = -EINVAL; > + break; > default: > ret = -EINVAL; > } > @@ -132,6 +143,18 @@ static umode_t tpdm_dsb_is_visible(struct kobject *kobj, > return 0; > } > > +static umode_t tpdm_dsb_msr_is_visible(struct kobject *kobj, > + struct attribute *attr, int n) > +{ > + struct device *dev = kobj_to_dev(kobj); > + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); > + > + if (drvdata->dsb_msr_num != 0) > + return attr->mode; I did mention in the last review, that we should limit the number of files visible based on the number of msrs ? struct tpdm_dataset_attribute *tpdm_attr = container_of(attr, struct tpdm_dataset_attribute, attr); if (tpdm_attr->idx < drvdata->dsb_msr_num) return attr->mode; That way, only the available msrs are listed in the directory ? Suzuki > + > + return 0; > +} > + > static void tpdm_reset_datasets(struct tpdm_drvdata *drvdata) > { > if (tpdm_has_dsb_dataset(drvdata)) { > @@ -193,6 +216,15 @@ static void set_dsb_tier(struct tpdm_drvdata *drvdata) > writel_relaxed(val, drvdata->base + TPDM_DSB_TIER); > } > > +static void set_dsb_msr(struct tpdm_drvdata *drvdata) > +{ > + int i; > + > + for (i = 0; i < drvdata->dsb_msr_num; i++) > + writel_relaxed(drvdata->dsb->msr[i], > + drvdata->base + TPDM_DSB_MSR(i)); > +} > + > static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) > { > u32 val, i; > @@ -216,6 +248,8 @@ static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) > > set_dsb_tier(drvdata); > > + set_dsb_msr(drvdata); > + > val = readl_relaxed(drvdata->base + TPDM_DSB_CR); > /* Set the mode of DSB dataset */ > set_dsb_mode(drvdata, &val); > @@ -739,6 +773,42 @@ static struct attribute *tpdm_dsb_patt_attrs[] = { > NULL, > }; > > +static struct attribute *tpdm_dsb_msr_attrs[] = { > + DSB_MSR_ATTR(0), > + DSB_MSR_ATTR(1), > + DSB_MSR_ATTR(2), > + DSB_MSR_ATTR(3), > + DSB_MSR_ATTR(4), > + DSB_MSR_ATTR(5), > + DSB_MSR_ATTR(6), > + DSB_MSR_ATTR(7), > + DSB_MSR_ATTR(8), > + DSB_MSR_ATTR(9), > + DSB_MSR_ATTR(10), > + DSB_MSR_ATTR(11), > + DSB_MSR_ATTR(12), > + DSB_MSR_ATTR(13), > + DSB_MSR_ATTR(14), > + DSB_MSR_ATTR(15), > + DSB_MSR_ATTR(16), > + DSB_MSR_ATTR(17), > + DSB_MSR_ATTR(18), > + DSB_MSR_ATTR(19), > + DSB_MSR_ATTR(20), > + DSB_MSR_ATTR(21), > + DSB_MSR_ATTR(22), > + DSB_MSR_ATTR(23), > + DSB_MSR_ATTR(24), > + DSB_MSR_ATTR(25), > + DSB_MSR_ATTR(26), > + DSB_MSR_ATTR(27), > + DSB_MSR_ATTR(28), > + DSB_MSR_ATTR(29), > + DSB_MSR_ATTR(30), > + DSB_MSR_ATTR(31), > + NULL, > +}; > + > static struct attribute *tpdm_dsb_attrs[] = { > &dev_attr_dsb_mode.attr, > &dev_attr_dsb_trig_ts.attr, > @@ -769,12 +839,19 @@ static struct attribute_group tpdm_dsb_patt_grp = { > .name = "dsb_patt", > }; > > +static struct attribute_group tpdm_dsb_msr_grp = { > + .attrs = tpdm_dsb_msr_attrs, > + .is_visible = tpdm_dsb_msr_is_visible, > + .name = "dsb_msr", > +}; > + > static const struct attribute_group *tpdm_attr_grps[] = { > &tpdm_attr_grp, > &tpdm_dsb_attrs_grp, > &tpdm_dsb_edge_grp, > &tpdm_dsb_trig_patt_grp, > &tpdm_dsb_patt_grp, > + &tpdm_dsb_msr_grp, > NULL, > }; > > @@ -809,6 +886,10 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) > if (ret) > return ret; > > + if (drvdata && tpdm_has_dsb_dataset(drvdata)) > + of_property_read_u32(drvdata->dev->of_node, > + "qcom,dsb_msr_num", &drvdata->dsb_msr_num); > + > /* Set up coresight component description */ > desc.name = coresight_alloc_device_name(&tpdm_devs, dev); > if (!desc.name) > diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h > index 891979d..4115b2a1 100644 > --- a/drivers/hwtracing/coresight/coresight-tpdm.h > +++ b/drivers/hwtracing/coresight/coresight-tpdm.h > @@ -18,6 +18,7 @@ > #define TPDM_DSB_XPMR(n) (0x7E8 + (n * 4)) > #define TPDM_DSB_EDCR(n) (0x808 + (n * 4)) > #define TPDM_DSB_EDCMR(n) (0x848 + (n * 4)) > +#define TPDM_DSB_MSR(n) (0x980 + (n * 4)) > > /* Enable bit for DSB subunit */ > #define TPDM_DSB_CR_ENA BIT(0) > @@ -90,6 +91,8 @@ > #define TPDM_DSB_MAX_EDCMR 8 > /* MAX number of DSB pattern */ > #define TPDM_DSB_MAX_PATT 8 > +/* MAX number of DSB MSR */ > +#define TPDM_DSB_MAX_MSR 32 > > #define tpdm_simple_dataset_ro(name, mem, idx) \ > (&((struct tpdm_dataset_attribute[]) { \ > @@ -134,6 +137,10 @@ > tpdm_simple_dataset_rw(tpmr##nr, \ > DSB_PATT_MASK, nr) > > +#define DSB_MSR_ATTR(nr) \ > + tpdm_simple_dataset_rw(msr##nr, \ > + DSB_MSR, nr) > + > /** > * struct dsb_dataset - specifics associated to dsb dataset > * @mode: DSB programming mode > @@ -144,6 +151,7 @@ > * @patt_mask: Save value for pattern mask > * @trig_patt: Save value for trigger pattern > * @trig_patt_mask: Save value for trigger pattern mask > + * @msr Save value for MSR > * @patt_ts: Enable/Disable pattern timestamp > * @patt_type: Set pattern type > * @trig_ts: Enable/Disable trigger timestamp. > @@ -158,6 +166,7 @@ struct dsb_dataset { > u32 patt_mask[TPDM_DSB_MAX_PATT]; > u32 trig_patt[TPDM_DSB_MAX_PATT]; > u32 trig_patt_mask[TPDM_DSB_MAX_PATT]; > + u32 msr[TPDM_DSB_MAX_MSR]; > bool patt_ts; > bool patt_type; > bool trig_ts; > @@ -173,6 +182,7 @@ struct dsb_dataset { > * @enable: enable status of the component. > * @datasets: The datasets types present of the TPDM. > * @dsb Specifics associated to TPDM DSB. > + * @dsb_msr_num Number of MSR supported by DSB TPDM > */ > > struct tpdm_drvdata { > @@ -183,6 +193,7 @@ struct tpdm_drvdata { > bool enable; > unsigned long datasets; > struct dsb_dataset *dsb; > + u32 dsb_msr_num; > }; > > /* Enumerate members of various datasets */ > @@ -193,6 +204,7 @@ enum dataset_mem { > DSB_TRIG_PATT_MASK, > DSB_PATT, > DSB_PATT_MASK, > + DSB_MSR, > }; > > /**
On 14/09/2023 06:43, Tao Zhang wrote: > Introduction of TPDM DSB subunit > DSB subunit is responsible for creating a dataset element, and is also > optionally responsible for packing it to fit multiple elements on a > single ATB transfer if possible in the configuration. The TPDM Core > Datapath requests timestamps be stored by the TPDA and then delivering > ATB sized data (depending on ATB width and element size, this could > be smaller or larger than a dataset element) to the ATB Mast FSM. > > The DSB subunit must be configured prior to enablement. This series > adds support for TPDM to configure the configure DSB subunit. > > Once this series patches are applied properly, the new tpdm nodes for > should be observed at the tpdm path /sys/bus/coresight/devices/tpdm* > which supports DSB subunit. > e.g. > root@qemuarm64:/sys/devices/platform/soc@0/6c08000.tpdm/tpdm1# ls -l > drwxr-xr-x 2 root root 0 Jan 1 00:00 connections > drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_edge > -rw-r--r-- 1 root root 4096 Jan 1 00:00 dsb_mode > drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_msr > drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_patt > -rw-r--r-- 1 root root 4096 Jan 1 00:00 dsb_patt_ts > -rw-r--r-- 1 root root 4096 Jan 1 00:00 dsb_patt_type > drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_trig_patt > -rw-r--r-- 1 root root 4096 Jan 1 00:00 dsb_trig_ts > -rw-r--r-- 1 root root 4096 Jan 1 00:00 dsb_trig_type > -rw-r--r-- 1 root root 4096 Jan 1 00:02 enable_source > --w------- 1 root root 4096 Jan 1 00:00 integration_test > drwxr-xr-x 2 root root 0 Jan 1 00:00 power > --w------- 1 root root 4096 Jan 1 00:02 reset_dataset > lrwxrwxrwx 1 root root 0 Apr 5 2021 subsystem -> ../../../../../bus/coresight > -rw-r--r-- 1 root root 4096 Apr 5 2021 uevent > -r--r--r-- 1 root root 4096 Jan 1 00:00 waiting_for_supplier > > We can use the commands are similar to the below to configure the > TPDMs which support DSB subunit. Enable coresight sink first. > echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink > echo 1 > /sys/bus/coresight/devices/tpdm1/reset_dataset > echo 0x3 > /sys/bus/coresight/devices/tpdm1/dsb_edge/ctrl_idx > echo 0x1 > /sys/bus/coresight/devices/tpdm1/dsb_edge/ctrl_mask > echo 0x0 > /sys/bus/coresight/devices/tpdm1/dsb_edge/ctrl_val > echo 1 > /sys/bus/coresight/devices/tpdm1/dsb_patt/enable_ts > echo 1 > /sys/bus/coresight/devices/tpdm1/dsb_patt/set_type > echo 0 > /sys/bus/coresight/devices/tpdm1/dsb_trig_ts > echo 0xFFFFFFFF > /sys/bus/coresight/devices/tpdm1/dsb_patt/tpmr5 > echo 0xFFFFFFFF > /sys/bus/coresight/devices/tpdm1/dsb_trig_patt/xpr2 > echo 1 > /sys/bus/coresight/devices/tpdm1/enable_source > I have reviewed this set, except for the last patch, rest looks fine. If you could resend the series with the comments addressed, we could queue this. Suzuki
On 9/26/2023 7:46 PM, Suzuki K Poulose wrote: > On 14/09/2023 06:43, Tao Zhang wrote: >> Add the nodes for DSB subunit MSR(mux select register) support. >> The TPDM MSR (mux select register) interface is an optional >> interface and associated bank of registers per TPDM subunit. >> The intent of mux select registers is to control muxing structures >> driving the TPDM’s’ various subunit interfaces. >> >> Signed-off-by: Tao Zhang <quic_taozha@quicinc.com> >> --- >> .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 8 +++ >> drivers/hwtracing/coresight/coresight-tpdm.c | 81 >> ++++++++++++++++++++++ >> drivers/hwtracing/coresight/coresight-tpdm.h | 12 ++++ >> 3 files changed, 101 insertions(+) >> >> diff --git >> a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >> b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >> index 1f20a3f..f07218e 100644 >> --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >> @@ -162,3 +162,11 @@ Description: >> Accepts only one of the 2 values - 0 or 1. >> 0 : Set the DSB pattern type to value. >> 1 : Set the DSB pattern type to toggle. >> + >> +What: /sys/bus/coresight/devices/<tpdm-name>/dsb_msr/msr[0:31] >> +Date: March 2023 >> +KernelVersion 6.7 >> +Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang >> (QUIC) <quic_taozha@quicinc.com> >> +Description: >> + (RW) Set/Get the MSR(mux select register) for the DSB subunit >> + TPDM. >> diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c >> b/drivers/hwtracing/coresight/coresight-tpdm.c >> index 7acc220..ea29e05 100644 >> --- a/drivers/hwtracing/coresight/coresight-tpdm.c >> +++ b/drivers/hwtracing/coresight/coresight-tpdm.c >> @@ -61,6 +61,11 @@ static ssize_t tpdm_simple_dataset_show(struct >> device *dev, >> return -EINVAL; >> return sysfs_emit(buf, "0x%x\n", >> drvdata->dsb->patt_mask[tpdm_attr->idx]); >> + case DSB_MSR: >> + if (tpdm_attr->idx >= drvdata->dsb_msr_num) >> + return -EINVAL; >> + return sysfs_emit(buf, "0x%x\n", >> + drvdata->dsb->msr[tpdm_attr->idx]); >> } >> return -EINVAL; >> } >> @@ -107,6 +112,12 @@ static ssize_t tpdm_simple_dataset_store(struct >> device *dev, >> else >> ret = -EINVAL; >> break; >> + case DSB_MSR: >> + if (tpdm_attr->idx < drvdata->dsb_msr_num) >> + drvdata->dsb->msr[tpdm_attr->idx] = val; >> + else >> + ret = -EINVAL; >> + break; >> default: >> ret = -EINVAL; >> } >> @@ -132,6 +143,18 @@ static umode_t tpdm_dsb_is_visible(struct >> kobject *kobj, >> return 0; >> } >> +static umode_t tpdm_dsb_msr_is_visible(struct kobject *kobj, >> + struct attribute *attr, int n) >> +{ >> + struct device *dev = kobj_to_dev(kobj); >> + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); >> + >> + if (drvdata->dsb_msr_num != 0) >> + return attr->mode; > > I did mention in the last review, that we should limit the number of > files visible based on the number of msrs ? > struct tpdm_dataset_attribute *tpdm_attr = > container_of(attr, struct tpdm_dataset_attribute, attr); > > if (tpdm_attr->idx < drvdata->dsb_msr_num) > return attr->mode; > > That way, only the available msrs are listed in the directory ? > > Suzuki Since "device_attribute" is the member of "tpdm_dataset_attribute", not "attribute". I need to get the "device_attribute " pointer first. List the following code I have verified. I will post the new patch series if you agree on this approach. struct device_attribute *dev_attr = container_of(attr, struct device_attribute, attr); struct tpdm_dataset_attribute *tpdm_attr = container_of(dev_attr, struct tpdm_dataset_attribute, attr); if (tpdm_attr->idx < drvdata->dsb_msr_num) return attr->mode; Best, Tao > > >> + >> + return 0; >> +} >> + >> static void tpdm_reset_datasets(struct tpdm_drvdata *drvdata) >> { >> if (tpdm_has_dsb_dataset(drvdata)) { >> @@ -193,6 +216,15 @@ static void set_dsb_tier(struct tpdm_drvdata >> *drvdata) >> writel_relaxed(val, drvdata->base + TPDM_DSB_TIER); >> } >> +static void set_dsb_msr(struct tpdm_drvdata *drvdata) >> +{ >> + int i; >> + >> + for (i = 0; i < drvdata->dsb_msr_num; i++) >> + writel_relaxed(drvdata->dsb->msr[i], >> + drvdata->base + TPDM_DSB_MSR(i)); >> +} >> + >> static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) >> { >> u32 val, i; >> @@ -216,6 +248,8 @@ static void tpdm_enable_dsb(struct tpdm_drvdata >> *drvdata) >> set_dsb_tier(drvdata); >> + set_dsb_msr(drvdata); >> + >> val = readl_relaxed(drvdata->base + TPDM_DSB_CR); >> /* Set the mode of DSB dataset */ >> set_dsb_mode(drvdata, &val); >> @@ -739,6 +773,42 @@ static struct attribute *tpdm_dsb_patt_attrs[] = { >> NULL, >> }; >> +static struct attribute *tpdm_dsb_msr_attrs[] = { >> + DSB_MSR_ATTR(0), >> + DSB_MSR_ATTR(1), >> + DSB_MSR_ATTR(2), >> + DSB_MSR_ATTR(3), >> + DSB_MSR_ATTR(4), >> + DSB_MSR_ATTR(5), >> + DSB_MSR_ATTR(6), >> + DSB_MSR_ATTR(7), >> + DSB_MSR_ATTR(8), >> + DSB_MSR_ATTR(9), >> + DSB_MSR_ATTR(10), >> + DSB_MSR_ATTR(11), >> + DSB_MSR_ATTR(12), >> + DSB_MSR_ATTR(13), >> + DSB_MSR_ATTR(14), >> + DSB_MSR_ATTR(15), >> + DSB_MSR_ATTR(16), >> + DSB_MSR_ATTR(17), >> + DSB_MSR_ATTR(18), >> + DSB_MSR_ATTR(19), >> + DSB_MSR_ATTR(20), >> + DSB_MSR_ATTR(21), >> + DSB_MSR_ATTR(22), >> + DSB_MSR_ATTR(23), >> + DSB_MSR_ATTR(24), >> + DSB_MSR_ATTR(25), >> + DSB_MSR_ATTR(26), >> + DSB_MSR_ATTR(27), >> + DSB_MSR_ATTR(28), >> + DSB_MSR_ATTR(29), >> + DSB_MSR_ATTR(30), >> + DSB_MSR_ATTR(31), >> + NULL, >> +}; >> + >> static struct attribute *tpdm_dsb_attrs[] = { >> &dev_attr_dsb_mode.attr, >> &dev_attr_dsb_trig_ts.attr, >> @@ -769,12 +839,19 @@ static struct attribute_group tpdm_dsb_patt_grp >> = { >> .name = "dsb_patt", >> }; >> +static struct attribute_group tpdm_dsb_msr_grp = { >> + .attrs = tpdm_dsb_msr_attrs, >> + .is_visible = tpdm_dsb_msr_is_visible, >> + .name = "dsb_msr", >> +}; >> + >> static const struct attribute_group *tpdm_attr_grps[] = { >> &tpdm_attr_grp, >> &tpdm_dsb_attrs_grp, >> &tpdm_dsb_edge_grp, >> &tpdm_dsb_trig_patt_grp, >> &tpdm_dsb_patt_grp, >> + &tpdm_dsb_msr_grp, >> NULL, >> }; >> @@ -809,6 +886,10 @@ static int tpdm_probe(struct amba_device >> *adev, const struct amba_id *id) >> if (ret) >> return ret; >> + if (drvdata && tpdm_has_dsb_dataset(drvdata)) >> + of_property_read_u32(drvdata->dev->of_node, >> + "qcom,dsb_msr_num", &drvdata->dsb_msr_num); >> + >> /* Set up coresight component description */ >> desc.name = coresight_alloc_device_name(&tpdm_devs, dev); >> if (!desc.name) >> diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h >> b/drivers/hwtracing/coresight/coresight-tpdm.h >> index 891979d..4115b2a1 100644 >> --- a/drivers/hwtracing/coresight/coresight-tpdm.h >> +++ b/drivers/hwtracing/coresight/coresight-tpdm.h >> @@ -18,6 +18,7 @@ >> #define TPDM_DSB_XPMR(n) (0x7E8 + (n * 4)) >> #define TPDM_DSB_EDCR(n) (0x808 + (n * 4)) >> #define TPDM_DSB_EDCMR(n) (0x848 + (n * 4)) >> +#define TPDM_DSB_MSR(n) (0x980 + (n * 4)) >> /* Enable bit for DSB subunit */ >> #define TPDM_DSB_CR_ENA BIT(0) >> @@ -90,6 +91,8 @@ >> #define TPDM_DSB_MAX_EDCMR 8 >> /* MAX number of DSB pattern */ >> #define TPDM_DSB_MAX_PATT 8 >> +/* MAX number of DSB MSR */ >> +#define TPDM_DSB_MAX_MSR 32 >> #define tpdm_simple_dataset_ro(name, mem, idx) \ >> (&((struct tpdm_dataset_attribute[]) { \ >> @@ -134,6 +137,10 @@ >> tpdm_simple_dataset_rw(tpmr##nr, \ >> DSB_PATT_MASK, nr) >> +#define DSB_MSR_ATTR(nr) \ >> + tpdm_simple_dataset_rw(msr##nr, \ >> + DSB_MSR, nr) >> + >> /** >> * struct dsb_dataset - specifics associated to dsb dataset >> * @mode: DSB programming mode >> @@ -144,6 +151,7 @@ >> * @patt_mask: Save value for pattern mask >> * @trig_patt: Save value for trigger pattern >> * @trig_patt_mask: Save value for trigger pattern mask >> + * @msr Save value for MSR >> * @patt_ts: Enable/Disable pattern timestamp >> * @patt_type: Set pattern type >> * @trig_ts: Enable/Disable trigger timestamp. >> @@ -158,6 +166,7 @@ struct dsb_dataset { >> u32 patt_mask[TPDM_DSB_MAX_PATT]; >> u32 trig_patt[TPDM_DSB_MAX_PATT]; >> u32 trig_patt_mask[TPDM_DSB_MAX_PATT]; >> + u32 msr[TPDM_DSB_MAX_MSR]; >> bool patt_ts; >> bool patt_type; >> bool trig_ts; >> @@ -173,6 +182,7 @@ struct dsb_dataset { >> * @enable: enable status of the component. >> * @datasets: The datasets types present of the TPDM. >> * @dsb Specifics associated to TPDM DSB. >> + * @dsb_msr_num Number of MSR supported by DSB TPDM >> */ >> struct tpdm_drvdata { >> @@ -183,6 +193,7 @@ struct tpdm_drvdata { >> bool enable; >> unsigned long datasets; >> struct dsb_dataset *dsb; >> + u32 dsb_msr_num; >> }; >> /* Enumerate members of various datasets */ >> @@ -193,6 +204,7 @@ enum dataset_mem { >> DSB_TRIG_PATT_MASK, >> DSB_PATT, >> DSB_PATT_MASK, >> + DSB_MSR, >> }; >> /** >
On 9/26/2023 9:12 PM, Suzuki K Poulose wrote: > On 14/09/2023 06:43, Tao Zhang wrote: >> Introduction of TPDM DSB subunit >> DSB subunit is responsible for creating a dataset element, and is also >> optionally responsible for packing it to fit multiple elements on a >> single ATB transfer if possible in the configuration. The TPDM Core >> Datapath requests timestamps be stored by the TPDA and then delivering >> ATB sized data (depending on ATB width and element size, this could >> be smaller or larger than a dataset element) to the ATB Mast FSM. >> >> The DSB subunit must be configured prior to enablement. This series >> adds support for TPDM to configure the configure DSB subunit. >> >> Once this series patches are applied properly, the new tpdm nodes for >> should be observed at the tpdm path /sys/bus/coresight/devices/tpdm* >> which supports DSB subunit. >> e.g. >> root@qemuarm64:/sys/devices/platform/soc@0/6c08000.tpdm/tpdm1# ls -l >> drwxr-xr-x 2 root root 0 Jan 1 00:00 connections >> drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_edge >> -rw-r--r-- 1 root root 4096 Jan 1 00:00 dsb_mode >> drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_msr >> drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_patt >> -rw-r--r-- 1 root root 4096 Jan 1 00:00 dsb_patt_ts >> -rw-r--r-- 1 root root 4096 Jan 1 00:00 dsb_patt_type >> drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_trig_patt >> -rw-r--r-- 1 root root 4096 Jan 1 00:00 dsb_trig_ts >> -rw-r--r-- 1 root root 4096 Jan 1 00:00 dsb_trig_type >> -rw-r--r-- 1 root root 4096 Jan 1 00:02 enable_source >> --w------- 1 root root 4096 Jan 1 00:00 >> integration_test >> drwxr-xr-x 2 root root 0 Jan 1 00:00 power >> --w------- 1 root root 4096 Jan 1 00:02 reset_dataset >> lrwxrwxrwx 1 root root 0 Apr 5 2021 subsystem -> >> ../../../../../bus/coresight >> -rw-r--r-- 1 root root 4096 Apr 5 2021 uevent >> -r--r--r-- 1 root root 4096 Jan 1 00:00 >> waiting_for_supplier >> >> We can use the commands are similar to the below to configure the >> TPDMs which support DSB subunit. Enable coresight sink first. >> echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink >> echo 1 > /sys/bus/coresight/devices/tpdm1/reset_dataset >> echo 0x3 > /sys/bus/coresight/devices/tpdm1/dsb_edge/ctrl_idx >> echo 0x1 > /sys/bus/coresight/devices/tpdm1/dsb_edge/ctrl_mask >> echo 0x0 > /sys/bus/coresight/devices/tpdm1/dsb_edge/ctrl_val >> echo 1 > /sys/bus/coresight/devices/tpdm1/dsb_patt/enable_ts >> echo 1 > /sys/bus/coresight/devices/tpdm1/dsb_patt/set_type >> echo 0 > /sys/bus/coresight/devices/tpdm1/dsb_trig_ts >> echo 0xFFFFFFFF > /sys/bus/coresight/devices/tpdm1/dsb_patt/tpmr5 >> echo 0xFFFFFFFF > /sys/bus/coresight/devices/tpdm1/dsb_trig_patt/xpr2 >> echo 1 > /sys/bus/coresight/devices/tpdm1/enable_source >> > > I have reviewed this set, except for the last patch, rest looks fine. > If you could resend the series with the comments addressed, we could > queue this. That's great. Thanks for your review. I also want to make a minor change. Can I rename "tpdm_dsb_attrs_grp" to "tpdm_dsb_attr_grp" in the next patch series? Best, Tao > > Suzuki
On 27/09/2023 07:37, Tao Zhang wrote: > > On 9/26/2023 9:12 PM, Suzuki K Poulose wrote: >> On 14/09/2023 06:43, Tao Zhang wrote: >>> Introduction of TPDM DSB subunit >>> DSB subunit is responsible for creating a dataset element, and is also >>> optionally responsible for packing it to fit multiple elements on a >>> single ATB transfer if possible in the configuration. The TPDM Core >>> Datapath requests timestamps be stored by the TPDA and then delivering >>> ATB sized data (depending on ATB width and element size, this could >>> be smaller or larger than a dataset element) to the ATB Mast FSM. >>> >>> The DSB subunit must be configured prior to enablement. This series >>> adds support for TPDM to configure the configure DSB subunit. >>> >>> Once this series patches are applied properly, the new tpdm nodes for >>> should be observed at the tpdm path /sys/bus/coresight/devices/tpdm* >>> which supports DSB subunit. >>> e.g. >>> root@qemuarm64:/sys/devices/platform/soc@0/6c08000.tpdm/tpdm1# ls -l >>> drwxr-xr-x 2 root root 0 Jan 1 00:00 connections >>> drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_edge >>> -rw-r--r-- 1 root root 4096 Jan 1 00:00 dsb_mode >>> drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_msr >>> drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_patt >>> -rw-r--r-- 1 root root 4096 Jan 1 00:00 dsb_patt_ts >>> -rw-r--r-- 1 root root 4096 Jan 1 00:00 dsb_patt_type >>> drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_trig_patt >>> -rw-r--r-- 1 root root 4096 Jan 1 00:00 dsb_trig_ts >>> -rw-r--r-- 1 root root 4096 Jan 1 00:00 dsb_trig_type >>> -rw-r--r-- 1 root root 4096 Jan 1 00:02 enable_source >>> --w------- 1 root root 4096 Jan 1 00:00 >>> integration_test >>> drwxr-xr-x 2 root root 0 Jan 1 00:00 power >>> --w------- 1 root root 4096 Jan 1 00:02 reset_dataset >>> lrwxrwxrwx 1 root root 0 Apr 5 2021 subsystem -> >>> ../../../../../bus/coresight >>> -rw-r--r-- 1 root root 4096 Apr 5 2021 uevent >>> -r--r--r-- 1 root root 4096 Jan 1 00:00 >>> waiting_for_supplier >>> >>> We can use the commands are similar to the below to configure the >>> TPDMs which support DSB subunit. Enable coresight sink first. >>> echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink >>> echo 1 > /sys/bus/coresight/devices/tpdm1/reset_dataset >>> echo 0x3 > /sys/bus/coresight/devices/tpdm1/dsb_edge/ctrl_idx >>> echo 0x1 > /sys/bus/coresight/devices/tpdm1/dsb_edge/ctrl_mask >>> echo 0x0 > /sys/bus/coresight/devices/tpdm1/dsb_edge/ctrl_val >>> echo 1 > /sys/bus/coresight/devices/tpdm1/dsb_patt/enable_ts >>> echo 1 > /sys/bus/coresight/devices/tpdm1/dsb_patt/set_type >>> echo 0 > /sys/bus/coresight/devices/tpdm1/dsb_trig_ts >>> echo 0xFFFFFFFF > /sys/bus/coresight/devices/tpdm1/dsb_patt/tpmr5 >>> echo 0xFFFFFFFF > /sys/bus/coresight/devices/tpdm1/dsb_trig_patt/xpr2 >>> echo 1 > /sys/bus/coresight/devices/tpdm1/enable_source >>> >> >> I have reviewed this set, except for the last patch, rest looks fine. >> If you could resend the series with the comments addressed, we could >> queue this. > > That's great. Thanks for your review. > > I also want to make a minor change. > > Can I rename "tpdm_dsb_attrs_grp" to "tpdm_dsb_attr_grp" in the next Sure, that is fine. The proposed changes to the other patch look good too. Suzuki
Introduction of TPDM DSB subunit DSB subunit is responsible for creating a dataset element, and is also optionally responsible for packing it to fit multiple elements on a single ATB transfer if possible in the configuration. The TPDM Core Datapath requests timestamps be stored by the TPDA and then delivering ATB sized data (depending on ATB width and element size, this could be smaller or larger than a dataset element) to the ATB Mast FSM. The DSB subunit must be configured prior to enablement. This series adds support for TPDM to configure the configure DSB subunit. Once this series patches are applied properly, the new tpdm nodes for should be observed at the tpdm path /sys/bus/coresight/devices/tpdm* which supports DSB subunit. e.g. root@qemuarm64:/sys/devices/platform/soc@0/6c08000.tpdm/tpdm1# ls -l drwxr-xr-x 2 root root 0 Jan 1 00:00 connections drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_edge -rw-r--r-- 1 root root 4096 Jan 1 00:00 dsb_mode drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_msr drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_patt -rw-r--r-- 1 root root 4096 Jan 1 00:00 dsb_patt_ts -rw-r--r-- 1 root root 4096 Jan 1 00:00 dsb_patt_type drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_trig_patt -rw-r--r-- 1 root root 4096 Jan 1 00:00 dsb_trig_ts -rw-r--r-- 1 root root 4096 Jan 1 00:00 dsb_trig_type -rw-r--r-- 1 root root 4096 Jan 1 00:02 enable_source --w------- 1 root root 4096 Jan 1 00:00 integration_test drwxr-xr-x 2 root root 0 Jan 1 00:00 power --w------- 1 root root 4096 Jan 1 00:02 reset_dataset lrwxrwxrwx 1 root root 0 Apr 5 2021 subsystem -> ../../../../../bus/coresight -rw-r--r-- 1 root root 4096 Apr 5 2021 uevent -r--r--r-- 1 root root 4096 Jan 1 00:00 waiting_for_supplier We can use the commands are similar to the below to configure the TPDMs which support DSB subunit. Enable coresight sink first. echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink echo 1 > /sys/bus/coresight/devices/tpdm1/reset_dataset echo 0x3 > /sys/bus/coresight/devices/tpdm1/dsb_edge/ctrl_idx echo 0x1 > /sys/bus/coresight/devices/tpdm1/dsb_edge/ctrl_mask echo 0x0 > /sys/bus/coresight/devices/tpdm1/dsb_edge/ctrl_val echo 1 > /sys/bus/coresight/devices/tpdm1/dsb_patt/enable_ts echo 1 > /sys/bus/coresight/devices/tpdm1/dsb_patt/set_type echo 0 > /sys/bus/coresight/devices/tpdm1/dsb_trig_ts echo 0xFFFFFFFF > /sys/bus/coresight/devices/tpdm1/dsb_patt/tpmr5 echo 0xFFFFFFFF > /sys/bus/coresight/devices/tpdm1/dsb_trig_patt/xpr2 echo 1 > /sys/bus/coresight/devices/tpdm1/enable_source TPDM_DSB commit tree: https://git.codelinaro.org/clo/linux-kernel/coresight/-/tree/tpdm-dsb-v9 https://git.codelinaro.org/clo/linux-kernel/coresight/-/commits/tpdm-dsb-v9 Changes in V9: 1. Adjust the alignment for all the patches in this series. -- Suzuki K Poulose 2. Initialize the variable "ret" to 0 in the patch#4. -- Suzuki K Poulose 3. Change the kernel version to 6.7 for all the sysfs files in the documents for this patch series. -- Suzuki K Poulose 4. Remove the parameter "max" from the general read/write functions in the patch#9 and patch#10. -- Suzuki K Poulose 5. Avoid releasing the lock in two different places in the patch#10. -- Suzuki K Poulose 6. Rename "dsb_patt_ts" to "enable_ts", and rename "dsb_patt_type" to "set_type" in the patch#11. Move these two sysfs files to the folder "dsb_patt". -- Suzuki K Poulose 7. Clear the relevant fields first in the function "set_dsb_tier". -- Suzuki K Poulose 8. Reading/writing the TIER register in the function "set_dsb_tier". -- Suzuki K Poulose 9. Read the property "qcom,dsb_msr_num" during probe. -- Suzuki K Poulose 10. Move the variable "dsb_msr_num" to "drvdata". -- Suzuki K Poulose 11. Move the msr number check to simple tpdm sysfs API. -- Suzuki K Poulose 12. Remove the needless "msr number" check in the function "tpdm_reset_datasets" -- Suzuki K Poulose Changes in V8: 1. Refine the function "tpda_set_element_size" and rename it to "tpda_get_element_size" in the patch#4. -- Suzuki K Poulose 2. Refine the functioin "tpda_enable_port" in the patch#4. -- Suzuki K Poulose 3. Write a helper to check if the TPDM has DSB dataset in the patch#5. -- Suzuki K Poulose 4. Move the function "tpdm_reset_datasets" to "datasets_setup" to call in the patch#5. -- Suzuki K Poulose 5. Refine the comment of DSB in "tpdm_drvdata" in the patch#5. -- Suzuki K Poulose 6. Refine the comments in the documents for this patch series. -- Suzuki K Poulose 7. Adjust the code alignment in this patch series. -- Suzuki K Poulose 8. Combine the mode related functions to one in the patch#8. -- Suzuki K Poulose 9. Refine the R/W functions of "dsb_mode" in the patch#8. -- Suzuki K Poulose 10. Adjust the macros of mode in the TPDM header file in the patch#8. -- Suzuki K Poulose 11. Remove the unused code and fix the warnings in compiling for the patch#9. -- kernel test robot 12. Use the following sysfs nodes to read/set edge control related value in the patch#9. dsb_edge/ \- ctrl_idx -> Set the index number \- ctrl_val -> Set the edge control value \- ctrl_mask -> Set the edge control mask \- edcr0 ... edcr15 -> Read the edge control value \- edcmr0 ... edcmr7 -> Read the edge control mask -- Suzuki K Poulose 13. Use the following sysfs nodes to read/set DSB trigger pattern value and mask in the patch#10. dsb_trig_patt/ \- xpr0 ... xpr15 -> (RW) Set/Get the value \- xpmr0 ... xpmr7 -> (RW) Set/Get the mask -- Suzuki K Poulose 14. Use the following sysfs nodes to read/set DSB pattern value and mask in the patch#11. dsb_patt/ \- tpr0 ... tpr15 -> (RW) Set/Get the value \- tpmr0 ... tpmr7 -> (RW) Set/Get the mask -- Suzuki K Poulose 15. Add "Acked-by" tag to the patch#12. -- Rob Herring 16. Use the following sysfs nodes to read/set DSB MSR in the patch#13. dsb_msr/ \- msr0 ... msr31 -> (RW) Set/Get the value -- Suzuki K Poulose 17. Create the maximal number of DSB MSR sysfs nodes if the TPDM supports DSB MSR. Write the values set by user space to the DSB MSR according to the number of MSR supported by the TPDM. -- Suzuki K Poulose Changes in V7: 1. Since the "One value" limitation on SysFs file usage, add the nodes to read/write the index number for configuring the DSB TPDM. The following index number nodes are added. "dsb_edge_ctrl_idx" in the patch #9 "dsb_trig_patt_idx" in the patch #10 "dsb_patt_idx" in the patch #11 "dsb_msr_idx" in the patch #13 -- Suzuki K Poulose Changes in V6: 1. Align the code to fix the styling issue. -- Suzuki K Poulose Changes in V5: 1. Correct data type for DSB element size in dt-bindings patch. 2. Refine the recursive function "tpda_set_element_size". -- Suzuki K Poulose 3. Get return value of the function "__tpda_enable" in "tpda_enable". -- Suzuki K Poulose 4. Refine the comments on "dsb_esize". -- Suzuki K Poulose 5. Split the chage that introduce the subtype "SUBTYPE_SOURCE_TPDM" to Coresight driver. -- Suzuki K Poulose 6. Inline the trigger type setting to "tpdm_enable_dsb" simply. -- Suzuki K Poulose 7. Split the change that remove the needless CS_{UN,}LOCK in the function "tpdm_datasets_setup". -- Suzuki K Poulose 8. Remove the disablement step in the reset node. -- Suzuki K Poulose 9. Update the kernel version to 6.5 in the sysfs document. -- Suzuki K Poulose 10. Remove the needless check in "tpdm_dsb_is_visible". -- Suzuki K Poulose 11. Change the macro to mask the mode of DSB TPDM. -- Suzuki K Poulose 12. Add a check to make sure "sysfs_emit_at" calling will not cause overflow. -- Suzuki K Poulose 13. Change the macro to get "edge_ctrl" value. -- Suzuki K Poulose 14. Remove the needless comments in the sysfs document. -- Suzuki K Poulose 15. Replace "TPDM_DSB_MAX_PATT" with "drvdata->dsb->msr_num" in "dsb_msr_show". -- Suzuki K Poulose 16. Update the check of MSR number in "dsb_msr_store". -- Suzuki K Poulose 17. Write data to the MSR registers in the DSB TPDM enablement function. -- Suzuki K Poulose Changes in V4: 1. Change the range of the property "qcom,dsb-element-size", and change the type to enumeration. -- Suzuki K Poulose, Krzysztof Kozlowski 2. Change dsb_esize from 32 bits to 8 bits. -- Suzuki K Poulose 3. Update the function tpda_set_element_size since James has updated the dependency series. Meanwhile, it will send out a warning if it detects more than one TPDM from the same TPDA input port. -- Suzuki K Poulose 4. Add a source_sub_type for TPDM to distinguish TPDM from the other coresight source. -- Suzuki K Poulose 5. Return error if the element size is not configured on devicetree in TPDA enablement. -- Suzuki K Poulose 6. Move memory allocation from "tpdm_init_datasets" to "tpdm_datasets_setup". Rename "tpdm_init_datasets" as "tpdm_reset_datasets". -- Suzuki K Poulose 7. Replace "coresight_disable" with "coresight_disable_source" to disable the TPDM in resetting. -- Suzuki K Poulose 8. Make sure "drvdata" is not NULL pointer before using it. -- Suzuki K Poulose 9. Change "set_dsb_cycacc_mode" to "set_dsb_test_mode" since cycle accurate mode is not supported on the current targets. It is replaced by test mode. 10. Document the value of "dsb_mode". -- Suzuki K Poulose 11. Macros are used to replace the formulas on dsb edge control nodes. -- Suzuki K Poulose 12. Document the values of "dsb_trig_patt_val" and "dsb_trig_patt_mask". -- Suzuki K Poulose 13. Combine two pattern related loops to one. And move DSB TIER register configurations to the new function "set_dsb_tier". -- Suzuki K Poulose 14. Rename the property "qcom,dsb_msr_num" to "qcom,dsb-msrs-num". -- Suzuki K Poulose, Krzysztof Kozlowski Changes in V3: 1. Move the property "qcom,dsb-element-size" to TPDM devicetree and update the TPDM yaml file for this item. -- Suzuki K Poulose 2. Add the error message when the DSB element size is not set to 32-bit or 64-bit. -- Suzuki K Poulose 3. Add more information to the comments of patch #3 -- Suzuki K Poulose 4. Combine the value updates to the TPDM_DSB_CR for TPDM. -- Suzuki K Poulose 5. Remove the function "tpdm_datasets_alloc", and fold its code to a new function "tpdm_init_datasets". It will complete the initialization of TPDM. -- Suzuki K Poulose 6. Change the method of qualifying input values. -- Suzuki K Poulose 7. Add the documentation of the new sysfs handles. -- Suzuki K Poulose 8. Provide the separate handles for the "mode bits". -- Suzuki K Poulose Changes in V2: 1. Change the name of the property "qcom,dsb-elem-size" to "qcom,dsb-element-size" -- Suzuki K Poulose 2. Update the TPDA yaml file for the item "qcom,dsb-elem-size". -- Krzysztof Kozlowski 3. Add the full name of DSB in the description of the item "qcom,dsb-elem-size". -- Rob Herring Changes in V1: 1. Change the definition of the property "qcom,dsb-elem-size" from "uint32-array" to "uint32-matrix". -- Krzysztof Kozlowski 2. Add the full name of DSB. -- Rob Herring 3. Deal with 2 entries in an iteration in TPDA driver. -- Suzuki K Poulose 4. Divide the function "tpdm_datasets_alloc" into two functions, "tpdm_datasets_setup" and "tpdm_datasets_alloc". 5. Detecte the input string with the conventional semantics automatically, and constrain the size of the input value. -- Suzuki K Poulose 6. Use the hook function "is_visible()" to hide the DSB related knobs if the data sets are missing. -- Suzuki K Poulose 7. Use the macros "FIELD_GET" and "FIELD_PREP" to set the values. -- Suzuki K Poulose 8. Update the definition of the macros in TPDM driver. 9. Update the comments of the values for the nodes which are for DSB element creation and onfigure pattern match output. -- Suzuki K Poulose 10. Use API "sysfs_emit" to "replace scnprintf". -- Suzuki K Poulose Tao Zhang (13): coresight-tpdm: Remove the unnecessary lock dt-bindings: arm: Add support for DSB element size coresight-tpdm: Introduce TPDM subtype to TPDM driver coresight-tpda: Add DSB dataset support coresight-tpdm: Initialize DSB subunit configuration coresight-tpdm: Add reset node to TPDM node coresight-tpdm: Add nodes to set trigger timestamp and type coresight-tpdm: Add node to set dsb programming mode coresight-tpdm: Add nodes for dsb edge control coresight-tpdm: Add nodes to configure pattern match output coresight-tpdm: Add nodes for timestamp request dt-bindings: arm: Add support for DSB MSR register coresight-tpdm: Add nodes for dsb msr support .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 159 +++++ .../bindings/arm/qcom,coresight-tpdm.yaml | 20 + drivers/hwtracing/coresight/coresight-core.c | 3 + drivers/hwtracing/coresight/coresight-tpda.c | 126 +++- drivers/hwtracing/coresight/coresight-tpda.h | 2 + drivers/hwtracing/coresight/coresight-tpdm.c | 714 ++++++++++++++++++++- drivers/hwtracing/coresight/coresight-tpdm.h | 161 +++++ include/linux/coresight.h | 1 + 8 files changed, 1164 insertions(+), 22 deletions(-)