| Message ID | 1590564453-24499-1-git-send-email-dillon.minfei@gmail.com |
|---|---|
| Headers | show |
| Series | Enable ili9341 and l3gd20 on stm32f429-disco | expand |
Quoting dillon.minfei@gmail.com (2020-05-27 00:27:29) > From: dillon min <dillon.minfei@gmail.com> > > This is due to misuse \u2018PLL_VCO_SAI' and'PLL_SAI' in clk-stm32f4.c > 'PLL_SAI' is 2, 'PLL_VCO_SAI' is 7(defined in > include/dt-bindings/clock/stm32fx-clock.h). > > 'post_div' point to 'post_div_data[]', 'post_div->pll_num' > is PLL_I2S or PLL_SAI. > > 'clks[PLL_VCO_SAI]' has valid 'struct clk_hw* ' return > from stm32f4_rcc_register_pll() but, at line 1777 of > driver/clk/clk-stm32f4.c, use the 'clks[post_div->pll_num]', > equal to 'clks[PLL_SAI]', this is invalid array member at that time. > > Fixes: 517633ef630e ("clk: stm32f4: Add post divisor for I2S & SAI PLLs") > Signed-off-by: dillon min <dillon.minfei@gmail.com> > --- Acked-by: Stephen Boyd <sboyd@kernel.org>
Quoting dillon.minfei@gmail.com (2020-05-27 00:27:30) > From: dillon min <dillon.minfei@gmail.com> > > stm32's clk driver register two ltdc gate clk to clk core by > clk_hw_register_gate() and clk_hw_register_composite() > > first: 'stm32f429_gates[]', clk name is 'ltdc', which no user to use. > second: 'stm32f429_aux_clk[]', clk name is 'lcd-tft', used by ltdc driver > > both of them point to the same offset of stm32's RCC register. after > kernel enter console, clk core turn off ltdc's clk as 'stm32f429_gates[]' > is no one to use. but, actually 'stm32f429_aux_clk[]' is in use. > > Fixes: daf2d117cbca ("clk: stm32f4: Add lcd-tft clock") > Signed-off-by: dillon min <dillon.minfei@gmail.com> > --- Acked-by: Stephen Boyd <sboyd@kernel.org>
On Wed, May 27, 2020 at 03:27:32PM +0800, dillon.minfei@gmail.com wrote: > From: dillon min <dillon.minfei@gmail.com> > > in l3gd20 driver startup, there is a setup failed error return from > stm32 spi driver Please do not submit new versions of already applied patches, please submit incremental updates to the existing code. Modifying existing commits creates problems for other users building on top of those commits so it's best practice to only change pubished git commits if absolutely essential.
On Wed, May 27, 2020 at 5:51 PM Mark Brown <broonie@kernel.org> wrote: > > On Wed, May 27, 2020 at 03:27:32PM +0800, dillon.minfei@gmail.com wrote: > > From: dillon min <dillon.minfei@gmail.com> > > > > in l3gd20 driver startup, there is a setup failed error return from > > stm32 spi driver > > Please do not submit new versions of already applied patches, please > submit incremental updates to the existing code. Modifying existing > commits creates problems for other users building on top of those > commits so it's best practice to only change pubished git commits if > absolutely essential. Hi Mark, sorry, forget to remove these two patch from this submits, will not include it in later submits which ack other's review result. thanks. best regards Dillon,
On Wed, May 27, 2020 at 06:45:53PM +0800, dillon min wrote: > sorry, forget to remove these two patch from this submits, will not > include it in later submits > which ack other's review result. Ah, OK - no problem.
Hi Dillon, On 5/27/20 9:27 AM, dillon.minfei@gmail.com wrote: > From: dillon min <dillon.minfei@gmail.com> ... > dillon min (9): > ARM: dts: stm32: Add dma config for spi5 > ARM: dts: stm32: Add pin map for ltdc & spi5 on stm32f429-disco board > ARM: dts: stm32: enable ltdc binding with ili9341, gyro l3gd20 on > stm32429-disco board > dt-bindings: display: panel: Add ilitek ili9341 panel bindings > clk: stm32: Fix stm32f429's ltdc driver hang in set clock rate > clk: stm32: Fix ltdc's clock turn off by clk_disable_unused() after > kernel startup > drm/panel: Add ilitek ili9341 panel driver > spi: stm32: Add 'SPI_SIMPLEX_RX', 'SPI_3WIRE_RX' support for stm32f4 > spi: flags 'SPI_CONTROLLER_MUST_RX' and 'SPI_CONTROLLER_MUST_TX' can't > be coexit with 'SPI_3WIRE' mode > > .../bindings/display/panel/ilitek,ili9341.yaml | 69 ++ > arch/arm/boot/dts/stm32f4-pinctrl.dtsi | 67 + > arch/arm/boot/dts/stm32f429-disco.dts | 48 + > arch/arm/boot/dts/stm32f429.dtsi | 3 + > drivers/clk/clk-stm32f4.c | 7 +- > drivers/gpu/drm/panel/Kconfig | 12 + > drivers/gpu/drm/panel/Makefile | 1 + > drivers/gpu/drm/panel/panel-ilitek-ili9341.c | 1288 ++++++++++++++++++++ > drivers/spi/spi-stm32.c | 19 +- > drivers/spi/spi.c | 3 +- > 10 files changed, 1508 insertions(+), 9 deletions(-) > create mode 100644 Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml > create mode 100644 drivers/gpu/drm/panel/panel-ilitek-ili9341.c > DT patches (patch 1 to 3) applied on stm32-next. I assume that binding one will go with drm/panel driver patch. Thanks Alex
Hi Dillon On 5/27/20 9:27 AM, dillon.minfei@gmail.com wrote: > From: dillon min <dillon.minfei@gmail.com> > > This patch adds the pin configuration for ltdc and spi5 controller > on stm32f429-disco board. > > Signed-off-by: dillon min <dillon.minfei@gmail.com> > --- > arch/arm/boot/dts/stm32f4-pinctrl.dtsi | 67 ++++++++++++++++++++++++++++++++++ > 1 file changed, 67 insertions(+) > > diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi > index 392fa143ce07..0eb107f968cd 100644 > --- a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi > +++ b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi > @@ -316,6 +316,73 @@ > }; > }; > > + ltdc_pins_f429_disco: ltdc-1 { Sorry I missed this issue during review. I changed ltdc_pins_f429_disco by ltdc_pins_b when I applied your patch. Regards alex > + pins { > + pinmux = <STM32_PINMUX('C', 6, AF14)>, > + /* LCD_HSYNC */ > + <STM32_PINMUX('A', 4, AF14)>, > + /* LCD_VSYNC */ > + <STM32_PINMUX('G', 7, AF14)>, > + /* LCD_CLK */ > + <STM32_PINMUX('C', 10, AF14)>, > + /* LCD_R2 */ > + <STM32_PINMUX('B', 0, AF9)>, > + /* LCD_R3 */ > + <STM32_PINMUX('A', 11, AF14)>, > + /* LCD_R4 */ > + <STM32_PINMUX('A', 12, AF14)>, > + /* LCD_R5 */ > + <STM32_PINMUX('B', 1, AF9)>, > + /* LCD_R6*/ > + <STM32_PINMUX('G', 6, AF14)>, > + /* LCD_R7 */ > + <STM32_PINMUX('A', 6, AF14)>, > + /* LCD_G2 */ > + <STM32_PINMUX('G', 10, AF9)>, > + /* LCD_G3 */ > + <STM32_PINMUX('B', 10, AF14)>, > + /* LCD_G4 */ > + <STM32_PINMUX('D', 6, AF14)>, > + /* LCD_B2 */ > + <STM32_PINMUX('G', 11, AF14)>, > + /* LCD_B3*/ > + <STM32_PINMUX('B', 11, AF14)>, > + /* LCD_G5 */ > + <STM32_PINMUX('C', 7, AF14)>, > + /* LCD_G6 */ > + <STM32_PINMUX('D', 3, AF14)>, > + /* LCD_G7 */ > + <STM32_PINMUX('G', 12, AF9)>, > + /* LCD_B4 */ > + <STM32_PINMUX('A', 3, AF14)>, > + /* LCD_B5 */ > + <STM32_PINMUX('B', 8, AF14)>, > + /* LCD_B6 */ > + <STM32_PINMUX('B', 9, AF14)>, > + /* LCD_B7 */ > + <STM32_PINMUX('F', 10, AF14)>; > + /* LCD_DE */ > + slew-rate = <2>; > + }; > + }; > + > + spi5_pins: spi5-0 { > + pins1 { > + pinmux = <STM32_PINMUX('F', 7, AF5)>, > + /* SPI5_CLK */ > + <STM32_PINMUX('F', 9, AF5)>; > + /* SPI5_MOSI */ > + bias-disable; > + drive-push-pull; > + slew-rate = <0>; > + }; > + pins2 { > + pinmux = <STM32_PINMUX('F', 8, AF5)>; > + /* SPI5_MISO */ > + bias-disable; > + }; > + }; > + > dcmi_pins: dcmi-0 { > pins { > pinmux = <STM32_PINMUX('A', 4, AF13)>, /* DCMI_HSYNC */ >
On Mon, Jun 15, 2020 at 5:45 PM Alexandre Torgue <alexandre.torgue@st.com> wrote: > > Hi Dillon > > On 5/27/20 9:27 AM, dillon.minfei@gmail.com wrote: > > From: dillon min <dillon.minfei@gmail.com> > > > > This patch adds the pin configuration for ltdc and spi5 controller > > on stm32f429-disco board. > > > > Signed-off-by: dillon min <dillon.minfei@gmail.com> > > --- > > arch/arm/boot/dts/stm32f4-pinctrl.dtsi | 67 ++++++++++++++++++++++++++++++++++ > > 1 file changed, 67 insertions(+) > > > > diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi > > index 392fa143ce07..0eb107f968cd 100644 > > --- a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi > > +++ b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi > > @@ -316,6 +316,73 @@ > > }; > > }; > > > > + ltdc_pins_f429_disco: ltdc-1 { > > Sorry I missed this issue during review. I changed ltdc_pins_f429_disco > by ltdc_pins_b when I applied your patch. Okay, thanks for reviewing. Regrades, Dillon, > > > Regards > alex > > > + pins { > > + pinmux = <STM32_PINMUX('C', 6, AF14)>, > > + /* LCD_HSYNC */ > > + <STM32_PINMUX('A', 4, AF14)>, > > + /* LCD_VSYNC */ > > + <STM32_PINMUX('G', 7, AF14)>, > > + /* LCD_CLK */ > > + <STM32_PINMUX('C', 10, AF14)>, > > + /* LCD_R2 */ > > + <STM32_PINMUX('B', 0, AF9)>, > > + /* LCD_R3 */ > > + <STM32_PINMUX('A', 11, AF14)>, > > + /* LCD_R4 */ > > + <STM32_PINMUX('A', 12, AF14)>, > > + /* LCD_R5 */ > > + <STM32_PINMUX('B', 1, AF9)>, > > + /* LCD_R6*/ > > + <STM32_PINMUX('G', 6, AF14)>, > > + /* LCD_R7 */ > > + <STM32_PINMUX('A', 6, AF14)>, > > + /* LCD_G2 */ > > + <STM32_PINMUX('G', 10, AF9)>, > > + /* LCD_G3 */ > > + <STM32_PINMUX('B', 10, AF14)>, > > + /* LCD_G4 */ > > + <STM32_PINMUX('D', 6, AF14)>, > > + /* LCD_B2 */ > > + <STM32_PINMUX('G', 11, AF14)>, > > + /* LCD_B3*/ > > + <STM32_PINMUX('B', 11, AF14)>, > > + /* LCD_G5 */ > > + <STM32_PINMUX('C', 7, AF14)>, > > + /* LCD_G6 */ > > + <STM32_PINMUX('D', 3, AF14)>, > > + /* LCD_G7 */ > > + <STM32_PINMUX('G', 12, AF9)>, > > + /* LCD_B4 */ > > + <STM32_PINMUX('A', 3, AF14)>, > > + /* LCD_B5 */ > > + <STM32_PINMUX('B', 8, AF14)>, > > + /* LCD_B6 */ > > + <STM32_PINMUX('B', 9, AF14)>, > > + /* LCD_B7 */ > > + <STM32_PINMUX('F', 10, AF14)>; > > + /* LCD_DE */ > > + slew-rate = <2>; > > + }; > > + }; > > + > > + spi5_pins: spi5-0 { > > + pins1 { > > + pinmux = <STM32_PINMUX('F', 7, AF5)>, > > + /* SPI5_CLK */ > > + <STM32_PINMUX('F', 9, AF5)>; > > + /* SPI5_MOSI */ > > + bias-disable; > > + drive-push-pull; > > + slew-rate = <0>; > > + }; > > + pins2 { > > + pinmux = <STM32_PINMUX('F', 8, AF5)>; > > + /* SPI5_MISO */ > > + bias-disable; > > + }; > > + }; > > + > > dcmi_pins: dcmi-0 { > > pins { > > pinmux = <STM32_PINMUX('A', 4, AF13)>, /* DCMI_HSYNC */ > >
still need more expert to review, so just a gentle ping for this patch On Wed, May 27, 2020 at 4:35 PM Stephen Boyd <sboyd@kernel.org> wrote: > > Quoting dillon.minfei@gmail.com (2020-05-27 00:27:29) > > From: dillon min <dillon.minfei@gmail.com> > > > > This is due to misuse \u2018PLL_VCO_SAI' and'PLL_SAI' in clk-stm32f4.c > > 'PLL_SAI' is 2, 'PLL_VCO_SAI' is 7(defined in > > include/dt-bindings/clock/stm32fx-clock.h). > > > > 'post_div' point to 'post_div_data[]', 'post_div->pll_num' > > is PLL_I2S or PLL_SAI. > > > > 'clks[PLL_VCO_SAI]' has valid 'struct clk_hw* ' return > > from stm32f4_rcc_register_pll() but, at line 1777 of > > driver/clk/clk-stm32f4.c, use the 'clks[post_div->pll_num]', > > equal to 'clks[PLL_SAI]', this is invalid array member at that time. > > > > Fixes: 517633ef630e ("clk: stm32f4: Add post divisor for I2S & SAI PLLs") > > Signed-off-by: dillon min <dillon.minfei@gmail.com> > > --- > > Acked-by: Stephen Boyd <sboyd@kernel.org>
still need more expert to review, so just a gentle ping for this patch On Wed, May 27, 2020 at 4:35 PM Stephen Boyd <sboyd@kernel.org> wrote: > > Quoting dillon.minfei@gmail.com (2020-05-27 00:27:30) > > From: dillon min <dillon.minfei@gmail.com> > > > > stm32's clk driver register two ltdc gate clk to clk core by > > clk_hw_register_gate() and clk_hw_register_composite() > > > > first: 'stm32f429_gates[]', clk name is 'ltdc', which no user to use. > > second: 'stm32f429_aux_clk[]', clk name is 'lcd-tft', used by ltdc driver > > > > both of them point to the same offset of stm32's RCC register. after > > kernel enter console, clk core turn off ltdc's clk as 'stm32f429_gates[]' > > is no one to use. but, actually 'stm32f429_aux_clk[]' is in use. > > > > Fixes: daf2d117cbca ("clk: stm32f4: Add lcd-tft clock") > > Signed-off-by: dillon min <dillon.minfei@gmail.com> > > --- > > Acked-by: Stephen Boyd <sboyd@kernel.org>
From: dillon min <dillon.minfei@gmail.com> V6: 1 separate '[PATCH v5 5/8]' patchs to two, each one has a Fixes tags according to Stephen Boyd's suggestion 2 fix panel-ilitek-ili9341 compile warning 'warning: Function parameter or member xxx not described in xxx' with W=1 V5's update based on Mark Brown's suggestion, use 'SPI_MASTER_MUST_RX' for SPI_SIMPLEX_RX mode on stm32 spi controller. V5: 1 instead of add send dummy data out under SIMPLEX_RX mode, add flags 'SPI_CONTROLLER_MUST_TX' for stm32 spi driver 2 bypass 'SPI_CONTROLLER_MUST_TX' and 'SPI_CONTROLLER_MUST_RX' under 'SPI_3WIRE' mode V4: According to alexandre torgue's suggestion, combine ili9341 and l3gd20's modification on stm32f429-disco board to one patchset. Changes: ili9341: 1 update ili9341 panel driver according to Linus's suggestion 2 drop V1's No.5 patch, sumbit new changes for clk-stm32f4 3 merge l3gd20's change to this patchset V3: 1 merge original tiny/ili9341.c driver to panel/panel-ilitek-ili9341.c to support serial spi & parallel rgb interface in one driver. 2 update ilitek,ili9341.yaml dts binding documentation. 3 update stm32f429-disco dts binding V2: 1 verify ilitek,ili9341.yaml with make O=../linux-stm32 dt_binding_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/display/panel/ ilitek,ili9341.yaml V1: 1 add ili9341 drm panel driver 2 add ltdc, spi5 controller for stm32f429-disco 3 add ltdc, spi5 pin map for stm32f429-disco 4 add docs about ili9341 5 fix ltdc driver loading hang in clk set rate bug L3gd20: V3: 1 merge stm32f429-disco dtbs binding with ili9341 part V2: 1 insert blank line at stm32f420-disco.dts line 143 2 add more description for l3gd20 in commit message V1: 1 enable spi5 controller on stm32f429-disco (dts) 2 add spi5 pinmap for stm32f429-disco (dts) 3 add SPI_SIMPLEX_RX, SPI_3WIRE_RX support for stm32f4 dillon min (9): ARM: dts: stm32: Add dma config for spi5 ARM: dts: stm32: Add pin map for ltdc & spi5 on stm32f429-disco board ARM: dts: stm32: enable ltdc binding with ili9341, gyro l3gd20 on stm32429-disco board dt-bindings: display: panel: Add ilitek ili9341 panel bindings clk: stm32: Fix stm32f429's ltdc driver hang in set clock rate clk: stm32: Fix ltdc's clock turn off by clk_disable_unused() after kernel startup drm/panel: Add ilitek ili9341 panel driver spi: stm32: Add 'SPI_SIMPLEX_RX', 'SPI_3WIRE_RX' support for stm32f4 spi: flags 'SPI_CONTROLLER_MUST_RX' and 'SPI_CONTROLLER_MUST_TX' can't be coexit with 'SPI_3WIRE' mode .../bindings/display/panel/ilitek,ili9341.yaml | 69 ++ arch/arm/boot/dts/stm32f4-pinctrl.dtsi | 67 + arch/arm/boot/dts/stm32f429-disco.dts | 48 + arch/arm/boot/dts/stm32f429.dtsi | 3 + drivers/clk/clk-stm32f4.c | 7 +- drivers/gpu/drm/panel/Kconfig | 12 + drivers/gpu/drm/panel/Makefile | 1 + drivers/gpu/drm/panel/panel-ilitek-ili9341.c | 1288 ++++++++++++++++++++ drivers/spi/spi-stm32.c | 19 +- drivers/spi/spi.c | 3 +- 10 files changed, 1508 insertions(+), 9 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml create mode 100644 drivers/gpu/drm/panel/panel-ilitek-ili9341.c