[v2,00/11] Move PMC clocks into Tegra PMC driver

Tegra PMC has clk_out_1, clk_out_2, clk_out_3 and blink controls which
are currently registered by Tegra clock driver using clk_regiser_mux and
clk_register_gate which performs direct Tegra PMC register access.

When Tegra PMC is in secure mode, any access from non-secure world will
not go through.

This patch series adds these Tegra PMC clocks and blink controls to Tegra
PMC driver with PMC as clock provider and removed them from Tegra clock
driver. This also adds PMC specific clock id's to use in device tree and
removed clock ids of PMC clock from Tegra clock driver.

This series also includes patch to update clock provider from tegra_car
to pmc in the device tree tegra210-smaug.dts that uses clk_out_2 from PMC.

[v2]:	Changes between v1 and v2 are
	- v2 includes patches for adding clk_out_1, clk_out_2, clk_out_3,
	  blink controls to Tegra PMC driver and removing clk-tegra-pmc.
	- feedback related to pmc clocks in Tegra PMC driver from v1
	- Removed patches for WB0 PLLM overrides and PLLE IDDQ PMC programming
	  by the clock driver using helper functions from Tegra PMC.

 	  Note:
	  To use helper functions from PMC driver, PMC early init need to
	  happen prior to using helper functions and these helper functions are
	  for PLLM Override and PLLE IDDQ programming in PMC during PLLM/PLLE
	  clock registration which happen in clock_init prior to Tegra PMC
	  probe.
	  Moving PLLM/PLLE clocks registration to happen after Tegra PMC
	  impacts other clocks EMC, MC and corresponding tegra_emc_init and
	  tegra_mc_init.
	  This implementation of configuring PMC registers thru helper
	  functions in clock driver needs proper changes across PMC, Clock,
	  EMC and MC inits to have it work across all Tegra platforms.

	  Currently PLLM Override is not enabled in the bootloader so proper
	  patches for this fix will be taken care separately.

[v1]:	v1 includes patches for below fixes.
	- adding clk_out_1, clk_out_2, clk_out_3, blink controls to Tegra PMC
	  driver and removing clk-tegra-pmc.
	- updated clock provider from tegra_car to pmc in the device tree
	  tegra210-smaug.dts that uses clk_out_2.
	- Added helper functions in PMC driver for WB0 PLLM overrides and PLLE
	  IDDQ programming to use by clock driver and updated clock driver to
	  use these helper functions and removed direct PMC access from clock
	  driver and all pmc base address references in clock driver.


Sowjanya Komatineni (11):
  dt-bindings: soc: tegra-pmc: Add Tegra PMC clock ids
  soc: tegra: Add Tegra PMC clock registrations into PMC driver
  dt-bindings: soc: tegra-pmc: Add id for Tegra PMC blink control
  soc: pmc: Add blink output clock registration to Tegra PMC
  clk: tegra: Remove tegra_pmc_clk_init along with clk ids
  dt-bindings: clock: tegra: Remove pmc clock ids from clock dt-bindings
  arm: tegra: Add clock-cells property to Tegra PMC
  arm64: tegra: Add clock-cells property to Tegra pmc
  dt-bindings: Add Tegra PMC clock configuration bindings
  arm64: tegra: smaug: Change clk_out_2 provider from tegra_car to pmc
  ASoC: nau8825: change Tegra clk_out_2 provider from tegra_car to pmc

 .../bindings/arm/tegra/nvidia,tegra20-pmc.txt      |  45 ++-
 .../devicetree/bindings/sound/nau8825.txt          |   2 +-
 arch/arm/boot/dts/tegra114.dtsi                    |   4 +-
 arch/arm/boot/dts/tegra124.dtsi                    |   4 +-
 arch/arm/boot/dts/tegra20.dtsi                     |   4 +-
 arch/arm/boot/dts/tegra30.dtsi                     |   4 +-
 arch/arm64/boot/dts/nvidia/tegra132.dtsi           |   4 +-
 arch/arm64/boot/dts/nvidia/tegra186.dtsi           |   2 +
 arch/arm64/boot/dts/nvidia/tegra194.dtsi           |   2 +
 arch/arm64/boot/dts/nvidia/tegra210-smaug.dts      |   2 +-
 arch/arm64/boot/dts/nvidia/tegra210.dtsi           |   2 +
 drivers/clk/tegra/Makefile                         |   1 -
 drivers/clk/tegra/clk-id.h                         |   7 -
 drivers/clk/tegra/clk-tegra-pmc.c                  | 122 -------
 drivers/clk/tegra/clk-tegra114.c                   |  11 -
 drivers/clk/tegra/clk-tegra124.c                   |  27 +-
 drivers/clk/tegra/clk-tegra20.c                    |   4 -
 drivers/clk/tegra/clk-tegra210.c                   |  11 -
 drivers/clk/tegra/clk-tegra30.c                    |  12 -
 drivers/clk/tegra/clk.h                            |   1 -
 drivers/soc/tegra/pmc.c                            | 379 +++++++++++++++++++++
 include/dt-bindings/clock/tegra114-car.h           |  14 +-
 include/dt-bindings/clock/tegra124-car-common.h    |  14 +-
 include/dt-bindings/clock/tegra20-car.h            |   2 +-
 include/dt-bindings/clock/tegra210-car.h           |  14 +-
 include/dt-bindings/clock/tegra30-car.h            |  14 +-
 include/dt-bindings/soc/tegra-pmc.h                |  19 ++
 27 files changed, 501 insertions(+), 226 deletions(-)
 delete mode 100644 drivers/clk/tegra/clk-tegra-pmc.c
 create mode 100644 include/dt-bindings/soc/tegra-pmc.h

27.11.2019 07:59, Sowjanya Komatineni пишет:
> Tegra PMC has clk_out_1, clk_out_2, clk_out_3 and blink controls which
> are currently registered by Tegra clock driver using clk_regiser_mux and
> clk_register_gate which performs direct Tegra PMC register access.
> 
> When Tegra PMC is in secure mode, any access from non-secure world will
> not go through.
> 
> This patch series adds these Tegra PMC clocks and blink controls to Tegra
> PMC driver with PMC as clock provider and removed them from Tegra clock
> driver. This also adds PMC specific clock id's to use in device tree and
> removed clock ids of PMC clock from Tegra clock driver.
> 
> This series also includes patch to update clock provider from tegra_car
> to pmc in the device tree tegra210-smaug.dts that uses clk_out_2 from PMC.
> 
> [v2]:	Changes between v1 and v2 are
> 	- v2 includes patches for adding clk_out_1, clk_out_2, clk_out_3,
> 	  blink controls to Tegra PMC driver and removing clk-tegra-pmc.
> 	- feedback related to pmc clocks in Tegra PMC driver from v1
> 	- Removed patches for WB0 PLLM overrides and PLLE IDDQ PMC programming
> 	  by the clock driver using helper functions from Tegra PMC.
> 
>  	  Note:
> 	  To use helper functions from PMC driver, PMC early init need to
> 	  happen prior to using helper functions and these helper functions are
> 	  for PLLM Override and PLLE IDDQ programming in PMC during PLLM/PLLE
> 	  clock registration which happen in clock_init prior to Tegra PMC
> 	  probe.
> 	  Moving PLLM/PLLE clocks registration to happen after Tegra PMC
> 	  impacts other clocks EMC, MC and corresponding tegra_emc_init and
> 	  tegra_mc_init.
> 	  This implementation of configuring PMC registers thru helper
> 	  functions in clock driver needs proper changes across PMC, Clock,
> 	  EMC and MC inits to have it work across all Tegra platforms.
> 
> 	  Currently PLLM Override is not enabled in the bootloader so proper
> 	  patches for this fix will be taken care separately.

Hello Sowjanya,

Could you please clarify what do you mean by "PLLM Override not enabled
in bootloader"?

There is T124 Nyan Big Chromebook which is supported in upstream kernel,
it has PLLM Override set by bootloader. I also have T30 Nexus 7 tablet
which has the PLLM Override set by bootloader as well. It's not clear to
me whether this patch series is supposed to break these devices. If the
breakage is the case here, then I'm afraid you can't postpone supporting
the PLLM Override and a full-featured implementation is needed.

I briefly tried to test this series on T30 and this time it doesn't hang
on boot, but somehow WiFi MMC card detection is broken. AFAIK, the WiFi
chip uses the Blink clock source and the clock should be enabled by the
MMC core because this is how DT part looks like:

brcm_wifi_pwrseq: wifi-pwrseq {
	compatible = "mmc-pwrseq-simple";
	clocks = <&pmc TEGRA_PMC_CLK_BLINK>;
	clock-names = "ext_clock";
	reset-gpios =  <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>;
	post-power-on-delay-ms = <300>;
	power-off-delay-us = <300>;
};

BTW, I  tried this series on a T20 device which also uses the Blink
clock for WiFi card and it works. So looks like this patchset has some
problem in regards to the T30 PMC clocks implementation.

[snip]

27.11.2019 07:59, Sowjanya Komatineni пишет:
> Tegra210 and prior Tegra PMC has clk_out_1, clk_out_2, clk_out_3 with
> mux and gate for each of these clocks.
> 
> Currently these PMC clocks are registered by Tegra clock driver using
> clk_register_mux and clk_register_gate by passing PMC base address
> and register offsets and PMC programming for these clocks happens
> through direct PMC access by the clock driver.
> 
> With this, when PMC is in secure mode any direct PMC access from the
> non-secure world does not go through and these clocks will not be
> functional.
> 
> This patch adds these clocks registration with PMC as a clock provider
> for these clocks. clk_ops callback implementations for these clocks
> uses tegra_pmc_readl and tegra_pmc_writel which supports PMC programming
> in secure mode and non-secure mode.
> 
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
>  drivers/soc/tegra/pmc.c | 330 ++++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 330 insertions(+)
> 
> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
> index ea0e11a09c12..a353f6d0a832 100644
> --- a/drivers/soc/tegra/pmc.c
> +++ b/drivers/soc/tegra/pmc.c
> @@ -13,6 +13,9 @@
>  
>  #include <linux/arm-smccc.h>
>  #include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/clkdev.h>
> +#include <linux/clk/clk-conf.h>
>  #include <linux/clk/tegra.h>
>  #include <linux/debugfs.h>
>  #include <linux/delay.h>
> @@ -48,6 +51,7 @@
>  #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
>  #include <dt-bindings/gpio/tegra186-gpio.h>
>  #include <dt-bindings/gpio/tegra194-gpio.h>
> +#include <dt-bindings/soc/tegra-pmc.h>
>  
>  #define PMC_CNTRL			0x0
>  #define  PMC_CNTRL_INTR_POLARITY	BIT(17) /* inverts INTR polarity */
> @@ -100,6 +104,7 @@
>  #define PMC_WAKE2_STATUS		0x168
>  #define PMC_SW_WAKE2_STATUS		0x16c
>  
> +#define PMC_CLK_OUT_CNTRL		0x1a8
>  #define PMC_SENSOR_CTRL			0x1b0
>  #define  PMC_SENSOR_CTRL_SCRATCH_WRITE	BIT(2)
>  #define  PMC_SENSOR_CTRL_ENABLE_RST	BIT(1)
> @@ -155,6 +160,91 @@
>  #define  TEGRA_SMC_PMC_READ	0xaa
>  #define  TEGRA_SMC_PMC_WRITE	0xbb
>  
> +struct pmc_clk_mux {
> +	struct clk_hw	hw;
> +	unsigned long	offs;
> +	u32		mask;
> +	u32		shift;
> +};
> +
> +#define to_pmc_clk_mux(_hw) container_of(_hw, struct pmc_clk_mux, hw)
> +
> +struct pmc_clk_gate {
> +	struct clk_hw	hw;
> +	unsigned long	offs;
> +	u32		shift;
> +};
> +
> +#define to_pmc_clk_gate(_hw) container_of(_hw, struct pmc_clk_gate, hw)
> +
> +struct pmc_clk_init_data {
> +	char *mux_name;
> +	char *gate_name;
> +	const char **parents;
> +	int num_parents;
> +	int mux_id;
> +	int gate_id;
> +	char *dev_name;
> +	u8 mux_shift;
> +	u8 gate_shift;
> +	u8 init_parent_index;
> +	int init_state;
> +};
> +
> +static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2",
> +	"clk_m_div4", "extern1",
> +};
> +
> +static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2",
> +	"clk_m_div4", "extern2",
> +};
> +
> +static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2",
> +	"clk_m_div4", "extern3",
> +};
> +
> +static struct pmc_clk_init_data tegra_pmc_clks_data[] = {

const?

[snip]

27.11.2019 07:59, Sowjanya Komatineni пишет:
> Tegra210 and prior Tegra PMC has clk_out_1, clk_out_2, clk_out_3 with
> mux and gate for each of these clocks.
> 
> Currently these PMC clocks are registered by Tegra clock driver using
> clk_register_mux and clk_register_gate by passing PMC base address
> and register offsets and PMC programming for these clocks happens
> through direct PMC access by the clock driver.
> 
> With this, when PMC is in secure mode any direct PMC access from the
> non-secure world does not go through and these clocks will not be
> functional.
> 
> This patch adds these clocks registration with PMC as a clock provider
> for these clocks. clk_ops callback implementations for these clocks
> uses tegra_pmc_readl and tegra_pmc_writel which supports PMC programming
> in secure mode and non-secure mode.
> 
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
>  drivers/soc/tegra/pmc.c | 330 ++++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 330 insertions(+)
> 
> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
> index ea0e11a09c12..a353f6d0a832 100644
> --- a/drivers/soc/tegra/pmc.c
> +++ b/drivers/soc/tegra/pmc.c
> @@ -13,6 +13,9 @@
>  
>  #include <linux/arm-smccc.h>
>  #include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/clkdev.h>
> +#include <linux/clk/clk-conf.h>
>  #include <linux/clk/tegra.h>
>  #include <linux/debugfs.h>
>  #include <linux/delay.h>
> @@ -48,6 +51,7 @@
>  #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
>  #include <dt-bindings/gpio/tegra186-gpio.h>
>  #include <dt-bindings/gpio/tegra194-gpio.h>
> +#include <dt-bindings/soc/tegra-pmc.h>
>  
>  #define PMC_CNTRL			0x0
>  #define  PMC_CNTRL_INTR_POLARITY	BIT(17) /* inverts INTR polarity */
> @@ -100,6 +104,7 @@
>  #define PMC_WAKE2_STATUS		0x168
>  #define PMC_SW_WAKE2_STATUS		0x16c
>  
> +#define PMC_CLK_OUT_CNTRL		0x1a8
>  #define PMC_SENSOR_CTRL			0x1b0
>  #define  PMC_SENSOR_CTRL_SCRATCH_WRITE	BIT(2)
>  #define  PMC_SENSOR_CTRL_ENABLE_RST	BIT(1)
> @@ -155,6 +160,91 @@
>  #define  TEGRA_SMC_PMC_READ	0xaa
>  #define  TEGRA_SMC_PMC_WRITE	0xbb
>  
> +struct pmc_clk_mux {
> +	struct clk_hw	hw;
> +	unsigned long	offs;
> +	u32		mask;
> +	u32		shift;
> +};
> +
> +#define to_pmc_clk_mux(_hw) container_of(_hw, struct pmc_clk_mux, hw)
> +
> +struct pmc_clk_gate {
> +	struct clk_hw	hw;
> +	unsigned long	offs;
> +	u32		shift;
> +};
> +
> +#define to_pmc_clk_gate(_hw) container_of(_hw, struct pmc_clk_gate, hw)
> +
> +struct pmc_clk_init_data {
> +	char *mux_name;
> +	char *gate_name;
> +	const char **parents;
> +	int num_parents;
> +	int mux_id;
> +	int gate_id;
> +	char *dev_name;
> +	u8 mux_shift;
> +	u8 gate_shift;
> +	u8 init_parent_index;
> +	int init_state;
> +};
> +
> +static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2",
> +	"clk_m_div4", "extern1",
> +};
> +
> +static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2",
> +	"clk_m_div4", "extern2",
> +};
> +
> +static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2",
> +	"clk_m_div4", "extern3",
> +};
> +
> +static struct pmc_clk_init_data tegra_pmc_clks_data[] = {
> +	{
> +		.mux_name = "clk_out_1_mux",
> +		.gate_name = "clk_out_1",
> +		.parents = clk_out1_parents,
> +		.num_parents = ARRAY_SIZE(clk_out1_parents),
> +		.mux_id = TEGRA_PMC_CLK_OUT_1_MUX,
> +		.gate_id = TEGRA_PMC_CLK_OUT_1,
> +		.dev_name = "extern1",
> +		.mux_shift = 6,
> +		.gate_shift = 2,
> +		.init_parent_index = 3,
> +		.init_state = 1,
> +	},
> +	{
> +		.mux_name = "clk_out_2_mux",
> +		.gate_name = "clk_out_2",
> +		.parents = clk_out2_parents,
> +		.num_parents = ARRAY_SIZE(clk_out2_parents),
> +		.mux_id = TEGRA_PMC_CLK_OUT_2_MUX,
> +		.gate_id = TEGRA_PMC_CLK_OUT_2,
> +		.dev_name = "extern2",
> +		.mux_shift = 14,
> +		.gate_shift = 10,
> +		.init_parent_index = 0,
> +		.init_state = 0,
> +	},
> +	{
> +		.mux_name = "clk_out_3_mux",
> +		.gate_name = "clk_out_3",
> +		.parents = clk_out3_parents,
> +		.num_parents = ARRAY_SIZE(clk_out3_parents),
> +		.mux_id = TEGRA_PMC_CLK_OUT_3_MUX,
> +		.gate_id = TEGRA_PMC_CLK_OUT_3,
> +		.dev_name = "extern3",
> +		.mux_shift = 22,
> +		.gate_shift = 18,
> +		.init_parent_index = 0,
> +		.init_state = 0,
> +	},
> +};
> +
>  struct tegra_powergate {
>  	struct generic_pm_domain genpd;
>  	struct tegra_pmc *pmc;
> @@ -254,6 +344,9 @@ struct tegra_pmc_soc {
>  	 */
>  	const struct tegra_wake_event *wake_events;
>  	unsigned int num_wake_events;
> +
> +	struct pmc_clk_init_data *pmc_clks_data;
> +	unsigned int num_pmc_clks;
>  };
>  
>  static const char * const tegra186_reset_sources[] = {
> @@ -2163,6 +2256,228 @@ static int tegra_pmc_clk_notify_cb(struct notifier_block *nb,
>  	return NOTIFY_OK;
>  }
>  
> +static void pmc_clk_fence_udelay(u32 offset)
> +{
> +	tegra_pmc_readl(pmc, offset);
> +	/* pmc clk propagation delay 2 us */
> +	udelay(2);
> +}
> +
> +static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
> +{
> +	struct pmc_clk_mux *mux = to_pmc_clk_mux(hw);
> +	int num_parents = clk_hw_get_num_parents(hw);
> +	u32 val;
> +
> +	val = tegra_pmc_readl(pmc, mux->offs) >> mux->shift;
> +	val &= mux->mask;
> +
> +	if (val >= num_parents)
> +		return -EINVAL;
> +
> +	return val;
> +}
> +
> +static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
> +{
> +	struct pmc_clk_mux *mux = to_pmc_clk_mux(hw);
> +	u32 val;
> +
> +	val = tegra_pmc_readl(pmc, mux->offs);
> +	val &= ~(mux->mask << mux->shift);
> +	val |= index << mux->shift;
> +	tegra_pmc_writel(pmc, val, mux->offs);
> +	pmc_clk_fence_udelay(mux->offs);
> +
> +	return 0;
> +}
> +
> +static const struct clk_ops pmc_clk_mux_ops = {
> +	.get_parent = pmc_clk_mux_get_parent,
> +	.set_parent = pmc_clk_mux_set_parent,
> +	.determine_rate = __clk_mux_determine_rate,
> +};
> +
> +static struct clk *
> +tegra_pmc_clk_mux_register(const char *name, const char * const *parent_names,
> +			   int num_parents, unsigned long flags,
> +			   unsigned long offset, u32 shift, u32 mask)
> +{
> +	struct clk_init_data init;
> +	struct pmc_clk_mux *mux;
> +
> +	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
> +	if (!mux)
> +		return ERR_PTR(-ENOMEM);
> +
> +	init.name = name;
> +	init.ops = &pmc_clk_mux_ops;
> +	init.parent_names = parent_names;
> +	init.num_parents = num_parents;
> +	init.flags = flags;
> +
> +	mux->hw.init = &init;
> +	mux->offs = offset;
> +	mux->mask = mask;
> +	mux->shift = shift;
> +
> +	return clk_register(NULL, &mux->hw);
> +}
> +
> +static int pmc_clk_is_enabled(struct clk_hw *hw)
> +{
> +	struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
> +
> +	return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0;
> +}
> +
> +static void pmc_clk_set_state(struct clk_hw *hw, int state)
> +{
> +	struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
> +	u32 val;
> +
> +	val = tegra_pmc_readl(pmc, gate->offs);
> +	val = state ? (val | BIT(gate->shift)) : (val & ~BIT(gate->shift));
> +	tegra_pmc_writel(pmc, val, gate->offs);
> +	pmc_clk_fence_udelay(gate->offs);
> +}
> +
> +static int pmc_clk_enable(struct clk_hw *hw)
> +{
> +	pmc_clk_set_state(hw, 1);
> +
> +	return 0;
> +}
> +
> +static void pmc_clk_disable(struct clk_hw *hw)
> +{
> +	pmc_clk_set_state(hw, 0);
> +}
> +
> +static const struct clk_ops pmc_clk_gate_ops = {
> +	.is_enabled = pmc_clk_is_enabled,
> +	.enable = pmc_clk_enable,
> +	.disable = pmc_clk_disable,
> +};
> +
> +static struct clk *
> +tegra_pmc_clk_gate_register(const char *name, const char *parent_name,
> +			    unsigned long flags, unsigned long offset,
> +			    u32 shift)
> +{
> +	struct clk_init_data init;
> +	struct pmc_clk_gate *gate;
> +
> +	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
> +	if (!gate)
> +		return ERR_PTR(-ENOMEM);
> +
> +	init.name = name;
> +	init.ops = &pmc_clk_gate_ops;
> +	init.parent_names = &parent_name;
> +	init.num_parents = 1;
> +	init.flags = flags;
> +
> +	gate->hw.init = &init;
> +	gate->offs = offset;
> +	gate->shift = shift;
> +
> +	return clk_register(NULL, &gate->hw);
> +}
> +
> +static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
> +				     struct device_node *np)
> +{
> +	struct clk *clkmux, *clk, *parent;
> +	struct clk_onecell_data *clk_data;
> +	unsigned int num_clks;
> +	int i, ret;
> +
> +	/* each pmc clock output has a mux and a gate */
> +	num_clks = pmc->soc->num_pmc_clks * 2;
> +
> +	if (!num_clks)
> +		return;
> +
> +	clk_data = kmalloc(sizeof(*clk_data), GFP_KERNEL);
> +	if (!clk_data)
> +		return;
> +
> +	clk_data->clks = kcalloc(TEGRA_PMC_CLK_MAX, sizeof(*clk_data->clks),
> +				 GFP_KERNEL);
> +	if (!clk_data->clks)
> +		goto free_clkdata;
> +
> +	clk_data->clk_num = num_clks;
> +
> +	for (i = 0; i < pmc->soc->num_pmc_clks; i++) {
> +		struct pmc_clk_init_data *data;
> +
> +		data = pmc->soc->pmc_clks_data + i;
> +
> +		clkmux = tegra_pmc_clk_mux_register(data->mux_name,
> +						    data->parents,
> +						    data->num_parents,
> +						    CLK_SET_RATE_NO_REPARENT |
> +						    CLK_SET_RATE_PARENT,
> +						    PMC_CLK_OUT_CNTRL,
> +						    data->mux_shift, 3);
> +		if (IS_ERR(clkmux))
> +			goto free_clks;
> +
> +		clk_data->clks[data->mux_id] = clkmux;
> +
> +		clk = tegra_pmc_clk_gate_register(data->gate_name,
> +						  data->mux_name,
> +						  CLK_SET_RATE_PARENT,
> +						  PMC_CLK_OUT_CNTRL,
> +						  data->gate_shift);
> +		if (IS_ERR(clk))
> +			goto free_clks;
> +
> +		clk_data->clks[data->gate_id] = clk;
> +
> +		ret = clk_set_parent(clk, clkmux);
> +		if (ret < 0) {
> +			pr_err("failed to set parent of %s to %s\n",
> +			       __func__, __clk_get_name(clk),
> +			       __clk_get_name(clkmux));
> +		}
> +
> +		clk_register_clkdev(clk, data->dev_name, data->gate_name);
> +
> +		/* configure initial clock parent and state */
> +		parent = clk_get_sys(data->gate_name,
> +				     data->parents[data->init_parent_index]);
> +		if (!IS_ERR(parent)) {
> +			ret = clk_set_parent(clkmux, parent);
> +			if (ret < 0) {
> +				pr_err("failed to set parent of %s to %s\n",
> +				       __func__, __clk_get_name(clkmux),
> +				       __clk_get_name(parent));
> +				WARN_ON(1);
> +			}
> +		}
> +
> +		if (data->init_state) {
> +			if (clk_prepare_enable(clk)) {
> +				pr_err("failed to enable %s\n", __func__,
> +				       __clk_get_name(clk));
> +				WARN_ON(1);
> +			}
> +		}
> +	}

In file included from ./include/linux/printk.h:7,
                 from ./include/linux/kernel.h:15,
                 from ./include/linux/clk.h:13,
                 from drivers/soc/tegra/pmc.c:15:
drivers/soc/tegra/pmc.c: In function ‘tegra_pmc_clock_register’:
./include/linux/kern_levels.h:5:18: warning: too many arguments for
format [-Wformat-extra-args]
    5 | #define KERN_SOH "\001"  /* ASCII Start Of Header */
      |                  ^~~~~~
./include/linux/kern_levels.h:11:18: note: in expansion of macro ‘KERN_SOH’
   11 | #define KERN_ERR KERN_SOH "3" /* error conditions */
      |                  ^~~~~~~~
./include/linux/printk.h:304:9: note: in expansion of macro ‘KERN_ERR’
  304 |  printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__)
      |         ^~~~~~~~
drivers/soc/tegra/pmc.c:2451:4: note: in expansion of macro ‘pr_err’
 2451 |    pr_err("failed to set parent of %s to %s\n",
      |    ^~~~~~
./include/linux/kern_levels.h:5:18: warning: too many arguments for
format [-Wformat-extra-args]
    5 | #define KERN_SOH "\001"  /* ASCII Start Of Header */
      |                  ^~~~~~
./include/linux/kern_levels.h:11:18: note: in expansion of macro ‘KERN_SOH’
   11 | #define KERN_ERR KERN_SOH "3" /* error conditions */
      |                  ^~~~~~~~
./include/linux/printk.h:304:9: note: in expansion of macro ‘KERN_ERR’
  304 |  printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__)
      |         ^~~~~~~~
drivers/soc/tegra/pmc.c:2464:5: note: in expansion of macro ‘pr_err’
 2464 |     pr_err("failed to set parent of %s to %s\n",
      |     ^~~~~~
./include/linux/kern_levels.h:5:18: warning: too many arguments for
format [-Wformat-extra-args]
    5 | #define KERN_SOH "\001"  /* ASCII Start Of Header */
      |                  ^~~~~~
./include/linux/kern_levels.h:11:18: note: in expansion of macro ‘KERN_SOH’
   11 | #define KERN_ERR KERN_SOH "3" /* error conditions */
      |                  ^~~~~~~~
./include/linux/printk.h:304:9: note: in expansion of macro ‘KERN_ERR’
  304 |  printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__)
      |         ^~~~~~~~
drivers/soc/tegra/pmc.c:2473:5: note: in expansion of macro ‘pr_err’
 2473 |     pr_err("failed to enable %s\n", __func__,
      |

27.11.2019 07:59, Sowjanya Komatineni пишет:
> Tegra210 and prior Tegra PMC has clk_out_1, clk_out_2, clk_out_3 with
> mux and gate for each of these clocks.
> 
> Currently these PMC clocks are registered by Tegra clock driver using
> clk_register_mux and clk_register_gate by passing PMC base address
> and register offsets and PMC programming for these clocks happens
> through direct PMC access by the clock driver.
> 
> With this, when PMC is in secure mode any direct PMC access from the
> non-secure world does not go through and these clocks will not be
> functional.
> 
> This patch adds these clocks registration with PMC as a clock provider
> for these clocks. clk_ops callback implementations for these clocks
> uses tegra_pmc_readl and tegra_pmc_writel which supports PMC programming
> in secure mode and non-secure mode.
> 
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
>  drivers/soc/tegra/pmc.c | 330 ++++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 330 insertions(+)
> 
> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
> index ea0e11a09c12..a353f6d0a832 100644
> --- a/drivers/soc/tegra/pmc.c
> +++ b/drivers/soc/tegra/pmc.c
> @@ -13,6 +13,9 @@
>  
>  #include <linux/arm-smccc.h>
>  #include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/clkdev.h>
> +#include <linux/clk/clk-conf.h>
>  #include <linux/clk/tegra.h>
>  #include <linux/debugfs.h>
>  #include <linux/delay.h>
> @@ -48,6 +51,7 @@
>  #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
>  #include <dt-bindings/gpio/tegra186-gpio.h>
>  #include <dt-bindings/gpio/tegra194-gpio.h>
> +#include <dt-bindings/soc/tegra-pmc.h>
>  
>  #define PMC_CNTRL			0x0
>  #define  PMC_CNTRL_INTR_POLARITY	BIT(17) /* inverts INTR polarity */
> @@ -100,6 +104,7 @@
>  #define PMC_WAKE2_STATUS		0x168
>  #define PMC_SW_WAKE2_STATUS		0x16c
>  
> +#define PMC_CLK_OUT_CNTRL		0x1a8
>  #define PMC_SENSOR_CTRL			0x1b0
>  #define  PMC_SENSOR_CTRL_SCRATCH_WRITE	BIT(2)
>  #define  PMC_SENSOR_CTRL_ENABLE_RST	BIT(1)
> @@ -155,6 +160,91 @@
>  #define  TEGRA_SMC_PMC_READ	0xaa
>  #define  TEGRA_SMC_PMC_WRITE	0xbb
>  
> +struct pmc_clk_mux {
> +	struct clk_hw	hw;
> +	unsigned long	offs;
> +	u32		mask;
> +	u32		shift;
> +};
> +
> +#define to_pmc_clk_mux(_hw) container_of(_hw, struct pmc_clk_mux, hw)
> +
> +struct pmc_clk_gate {
> +	struct clk_hw	hw;
> +	unsigned long	offs;
> +	u32		shift;
> +};
> +
> +#define to_pmc_clk_gate(_hw) container_of(_hw, struct pmc_clk_gate, hw)
> +
> +struct pmc_clk_init_data {
> +	char *mux_name;
> +	char *gate_name;
> +	const char **parents;
> +	int num_parents;
> +	int mux_id;
> +	int gate_id;
> +	char *dev_name;
> +	u8 mux_shift;
> +	u8 gate_shift;
> +	u8 init_parent_index;
> +	int init_state;
> +};
> +
> +static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2",
> +	"clk_m_div4", "extern1",
> +};
> +
> +static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2",
> +	"clk_m_div4", "extern2",
> +};
> +
> +static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2",
> +	"clk_m_div4", "extern3",
> +};
> +
> +static struct pmc_clk_init_data tegra_pmc_clks_data[] = {
> +	{
> +		.mux_name = "clk_out_1_mux",
> +		.gate_name = "clk_out_1",
> +		.parents = clk_out1_parents,
> +		.num_parents = ARRAY_SIZE(clk_out1_parents),
> +		.mux_id = TEGRA_PMC_CLK_OUT_1_MUX,
> +		.gate_id = TEGRA_PMC_CLK_OUT_1,
> +		.dev_name = "extern1",
> +		.mux_shift = 6,
> +		.gate_shift = 2,
> +		.init_parent_index = 3,
> +		.init_state = 1,
> +	},
> +	{
> +		.mux_name = "clk_out_2_mux",
> +		.gate_name = "clk_out_2",
> +		.parents = clk_out2_parents,
> +		.num_parents = ARRAY_SIZE(clk_out2_parents),
> +		.mux_id = TEGRA_PMC_CLK_OUT_2_MUX,
> +		.gate_id = TEGRA_PMC_CLK_OUT_2,
> +		.dev_name = "extern2",
> +		.mux_shift = 14,
> +		.gate_shift = 10,
> +		.init_parent_index = 0,
> +		.init_state = 0,
> +	},
> +	{
> +		.mux_name = "clk_out_3_mux",
> +		.gate_name = "clk_out_3",
> +		.parents = clk_out3_parents,
> +		.num_parents = ARRAY_SIZE(clk_out3_parents),
> +		.mux_id = TEGRA_PMC_CLK_OUT_3_MUX,
> +		.gate_id = TEGRA_PMC_CLK_OUT_3,
> +		.dev_name = "extern3",
> +		.mux_shift = 22,
> +		.gate_shift = 18,
> +		.init_parent_index = 0,
> +		.init_state = 0,
> +	},
> +};
> +
>  struct tegra_powergate {
>  	struct generic_pm_domain genpd;
>  	struct tegra_pmc *pmc;
> @@ -254,6 +344,9 @@ struct tegra_pmc_soc {
>  	 */
>  	const struct tegra_wake_event *wake_events;
>  	unsigned int num_wake_events;
> +
> +	struct pmc_clk_init_data *pmc_clks_data;
> +	unsigned int num_pmc_clks;
>  };
>  
>  static const char * const tegra186_reset_sources[] = {
> @@ -2163,6 +2256,228 @@ static int tegra_pmc_clk_notify_cb(struct notifier_block *nb,
>  	return NOTIFY_OK;
>  }
>  
> +static void pmc_clk_fence_udelay(u32 offset)
> +{
> +	tegra_pmc_readl(pmc, offset);
> +	/* pmc clk propagation delay 2 us */
> +	udelay(2);
> +}
> +
> +static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
> +{
> +	struct pmc_clk_mux *mux = to_pmc_clk_mux(hw);
> +	int num_parents = clk_hw_get_num_parents(hw);
> +	u32 val;
> +
> +	val = tegra_pmc_readl(pmc, mux->offs) >> mux->shift;
> +	val &= mux->mask;
> +
> +	if (val >= num_parents)
> +		return -EINVAL;
> +
> +	return val;
> +}
> +
> +static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
> +{
> +	struct pmc_clk_mux *mux = to_pmc_clk_mux(hw);
> +	u32 val;
> +
> +	val = tegra_pmc_readl(pmc, mux->offs);
> +	val &= ~(mux->mask << mux->shift);
> +	val |= index << mux->shift;
> +	tegra_pmc_writel(pmc, val, mux->offs);
> +	pmc_clk_fence_udelay(mux->offs);
> +
> +	return 0;
> +}
> +
> +static const struct clk_ops pmc_clk_mux_ops = {
> +	.get_parent = pmc_clk_mux_get_parent,
> +	.set_parent = pmc_clk_mux_set_parent,
> +	.determine_rate = __clk_mux_determine_rate,
> +};
> +
> +static struct clk *
> +tegra_pmc_clk_mux_register(const char *name, const char * const *parent_names,
> +			   int num_parents, unsigned long flags,
> +			   unsigned long offset, u32 shift, u32 mask)
> +{
> +	struct clk_init_data init;
> +	struct pmc_clk_mux *mux;
> +
> +	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
> +	if (!mux)
> +		return ERR_PTR(-ENOMEM);
> +
> +	init.name = name;
> +	init.ops = &pmc_clk_mux_ops;
> +	init.parent_names = parent_names;
> +	init.num_parents = num_parents;
> +	init.flags = flags;
> +
> +	mux->hw.init = &init;
> +	mux->offs = offset;
> +	mux->mask = mask;
> +	mux->shift = shift;
> +
> +	return clk_register(NULL, &mux->hw);
> +}
> +
> +static int pmc_clk_is_enabled(struct clk_hw *hw)
> +{
> +	struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
> +
> +	return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0;
> +}
> +
> +static void pmc_clk_set_state(struct clk_hw *hw, int state)
> +{
> +	struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
> +	u32 val;
> +
> +	val = tegra_pmc_readl(pmc, gate->offs);
> +	val = state ? (val | BIT(gate->shift)) : (val & ~BIT(gate->shift));
> +	tegra_pmc_writel(pmc, val, gate->offs);
> +	pmc_clk_fence_udelay(gate->offs);
> +}
> +
> +static int pmc_clk_enable(struct clk_hw *hw)
> +{
> +	pmc_clk_set_state(hw, 1);
> +
> +	return 0;
> +}
> +
> +static void pmc_clk_disable(struct clk_hw *hw)
> +{
> +	pmc_clk_set_state(hw, 0);
> +}
> +
> +static const struct clk_ops pmc_clk_gate_ops = {
> +	.is_enabled = pmc_clk_is_enabled,
> +	.enable = pmc_clk_enable,
> +	.disable = pmc_clk_disable,
> +};
> +
> +static struct clk *
> +tegra_pmc_clk_gate_register(const char *name, const char *parent_name,
> +			    unsigned long flags, unsigned long offset,
> +			    u32 shift)
> +{
> +	struct clk_init_data init;
> +	struct pmc_clk_gate *gate;
> +
> +	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
> +	if (!gate)
> +		return ERR_PTR(-ENOMEM);
> +
> +	init.name = name;
> +	init.ops = &pmc_clk_gate_ops;
> +	init.parent_names = &parent_name;
> +	init.num_parents = 1;
> +	init.flags = flags;
> +
> +	gate->hw.init = &init;
> +	gate->offs = offset;
> +	gate->shift = shift;
> +
> +	return clk_register(NULL, &gate->hw);
> +}
> +
> +static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
> +				     struct device_node *np)
> +{
> +	struct clk *clkmux, *clk, *parent;
> +	struct clk_onecell_data *clk_data;
> +	unsigned int num_clks;
> +	int i, ret;
> +
> +	/* each pmc clock output has a mux and a gate */
> +	num_clks = pmc->soc->num_pmc_clks * 2;
> +
> +	if (!num_clks)
> +		return;
> +
> +	clk_data = kmalloc(sizeof(*clk_data), GFP_KERNEL);
> +	if (!clk_data)
> +		return;
> +
> +	clk_data->clks = kcalloc(TEGRA_PMC_CLK_MAX, sizeof(*clk_data->clks),
> +				 GFP_KERNEL);
> +	if (!clk_data->clks)
> +		goto free_clkdata;
> +
> +	clk_data->clk_num = num_clks;
> +
> +	for (i = 0; i < pmc->soc->num_pmc_clks; i++) {
> +		struct pmc_clk_init_data *data;
> +
> +		data = pmc->soc->pmc_clks_data + i;
> +
> +		clkmux = tegra_pmc_clk_mux_register(data->mux_name,
> +						    data->parents,
> +						    data->num_parents,
> +						    CLK_SET_RATE_NO_REPARENT |
> +						    CLK_SET_RATE_PARENT,
> +						    PMC_CLK_OUT_CNTRL,
> +						    data->mux_shift, 3);
> +		if (IS_ERR(clkmux))
> +			goto free_clks;
> +
> +		clk_data->clks[data->mux_id] = clkmux;
> +
> +		clk = tegra_pmc_clk_gate_register(data->gate_name,
> +						  data->mux_name,
> +						  CLK_SET_RATE_PARENT,
> +						  PMC_CLK_OUT_CNTRL,
> +						  data->gate_shift);
> +		if (IS_ERR(clk))
> +			goto free_clks;
> +
> +		clk_data->clks[data->gate_id] = clk;
> +
> +		ret = clk_set_parent(clk, clkmux);
> +		if (ret < 0) {
> +			pr_err("failed to set parent of %s to %s\n",
> +			       __func__, __clk_get_name(clk),
> +			       __clk_get_name(clkmux));
> +		}
> +
> +		clk_register_clkdev(clk, data->dev_name, data->gate_name);
> +
> +		/* configure initial clock parent and state */
> +		parent = clk_get_sys(data->gate_name,
> +				     data->parents[data->init_parent_index]);
> +		if (!IS_ERR(parent)) {
> +			ret = clk_set_parent(clkmux, parent);
> +			if (ret < 0) {
> +				pr_err("failed to set parent of %s to %s\n",
> +				       __func__, __clk_get_name(clkmux),
> +				       __clk_get_name(parent));
> +				WARN_ON(1);
> +			}
> +		}
> +
> +		if (data->init_state) {
> +			if (clk_prepare_enable(clk)) {
> +				pr_err("failed to enable %s\n", __func__,
> +				       __clk_get_name(clk));
> +				WARN_ON(1);

Should be a bit better to move the WARN_ON to the end of errors handling
in order to catch all possible errors:

@@ -2510,6 +2510,7 @@ static void tegra_pmc_clock_register(struct
tegra_pmc *pmc,
        return;

 free_clks:
+       WARN_ON(1);
        kfree(clk_data->clks);
 free_clkdata:
        kfree(clk_data);

On 11/27/19 6:31 AM, Dmitry Osipenko wrote:
> 27.11.2019 07:59, Sowjanya Komatineni пишет:
>> Tegra PMC has clk_out_1, clk_out_2, clk_out_3 and blink controls which
>> are currently registered by Tegra clock driver using clk_regiser_mux and
>> clk_register_gate which performs direct Tegra PMC register access.
>>
>> When Tegra PMC is in secure mode, any access from non-secure world will
>> not go through.
>>
>> This patch series adds these Tegra PMC clocks and blink controls to Tegra
>> PMC driver with PMC as clock provider and removed them from Tegra clock
>> driver. This also adds PMC specific clock id's to use in device tree and
>> removed clock ids of PMC clock from Tegra clock driver.
>>
>> This series also includes patch to update clock provider from tegra_car
>> to pmc in the device tree tegra210-smaug.dts that uses clk_out_2 from PMC.
>>
>> [v2]:	Changes between v1 and v2 are
>> 	- v2 includes patches for adding clk_out_1, clk_out_2, clk_out_3,
>> 	  blink controls to Tegra PMC driver and removing clk-tegra-pmc.
>> 	- feedback related to pmc clocks in Tegra PMC driver from v1
>> 	- Removed patches for WB0 PLLM overrides and PLLE IDDQ PMC programming
>> 	  by the clock driver using helper functions from Tegra PMC.
>>
>>   	  Note:
>> 	  To use helper functions from PMC driver, PMC early init need to
>> 	  happen prior to using helper functions and these helper functions are
>> 	  for PLLM Override and PLLE IDDQ programming in PMC during PLLM/PLLE
>> 	  clock registration which happen in clock_init prior to Tegra PMC
>> 	  probe.
>> 	  Moving PLLM/PLLE clocks registration to happen after Tegra PMC
>> 	  impacts other clocks EMC, MC and corresponding tegra_emc_init and
>> 	  tegra_mc_init.
>> 	  This implementation of configuring PMC registers thru helper
>> 	  functions in clock driver needs proper changes across PMC, Clock,
>> 	  EMC and MC inits to have it work across all Tegra platforms.
>>
>> 	  Currently PLLM Override is not enabled in the bootloader so proper
>> 	  patches for this fix will be taken care separately.
> Hello Sowjanya,
>
> Could you please clarify what do you mean by "PLLM Override not enabled
> in bootloader"?
>
> There is T124 Nyan Big Chromebook which is supported in upstream kernel,
> it has PLLM Override set by bootloader. I also have T30 Nexus 7 tablet
> which has the PLLM Override set by bootloader as well. It's not clear to
> me whether this patch series is supposed to break these devices. If the
> breakage is the case here, then I'm afraid you can't postpone supporting
> the PLLM Override and a full-featured implementation is needed.

Hi Dmitry,

Secure boot currently is enabled only on Tegra210 and Tegra210 
bootloader doesn't enable PLLM override.

So PLLM override/PLLE IDDQ being in clock driver currently will not 
break on any of existing Tegra platforms.

>
> I briefly tried to test this series on T30 and this time it doesn't hang
> on boot, but somehow WiFi MMC card detection is broken. AFAIK, the WiFi
> chip uses the Blink clock source and the clock should be enabled by the
> MMC core because this is how DT part looks like:
>
> brcm_wifi_pwrseq: wifi-pwrseq {
> 	compatible = "mmc-pwrseq-simple";
> 	clocks = <&pmc TEGRA_PMC_CLK_BLINK>;
> 	clock-names = "ext_clock";
> 	reset-gpios =  <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>;
> 	post-power-on-delay-ms = <300>;
> 	power-off-delay-us = <300>;
> };
>
> BTW, I  tried this series on a T20 device which also uses the Blink
> clock for WiFi card and it works. So looks like this patchset has some
> problem in regards to the T30 PMC clocks implementation.
>
> [snip]

Blink init state is set to true for both Tegra20 and Tegra30 and all go 
through the same blink programming sequence.

Will try to add more debug messages to dump registers and will test 
blink through device tree on T30 and will get back...

On 11/27/19 9:02 AM, Sowjanya Komatineni wrote:
>
> On 11/27/19 6:31 AM, Dmitry Osipenko wrote:
>> 27.11.2019 07:59, Sowjanya Komatineni пишет:
>>> Tegra PMC has clk_out_1, clk_out_2, clk_out_3 and blink controls which
>>> are currently registered by Tegra clock driver using clk_regiser_mux 
>>> and
>>> clk_register_gate which performs direct Tegra PMC register access.
>>>
>>> When Tegra PMC is in secure mode, any access from non-secure world will
>>> not go through.
>>>
>>> This patch series adds these Tegra PMC clocks and blink controls to 
>>> Tegra
>>> PMC driver with PMC as clock provider and removed them from Tegra clock
>>> driver. This also adds PMC specific clock id's to use in device tree 
>>> and
>>> removed clock ids of PMC clock from Tegra clock driver.
>>>
>>> This series also includes patch to update clock provider from tegra_car
>>> to pmc in the device tree tegra210-smaug.dts that uses clk_out_2 
>>> from PMC.
>>>
>>> [v2]:    Changes between v1 and v2 are
>>>     - v2 includes patches for adding clk_out_1, clk_out_2, clk_out_3,
>>>       blink controls to Tegra PMC driver and removing clk-tegra-pmc.
>>>     - feedback related to pmc clocks in Tegra PMC driver from v1
>>>     - Removed patches for WB0 PLLM overrides and PLLE IDDQ PMC 
>>> programming
>>>       by the clock driver using helper functions from Tegra PMC.
>>>
>>>         Note:
>>>       To use helper functions from PMC driver, PMC early init need to
>>>       happen prior to using helper functions and these helper 
>>> functions are
>>>       for PLLM Override and PLLE IDDQ programming in PMC during 
>>> PLLM/PLLE
>>>       clock registration which happen in clock_init prior to Tegra PMC
>>>       probe.
>>>       Moving PLLM/PLLE clocks registration to happen after Tegra PMC
>>>       impacts other clocks EMC, MC and corresponding tegra_emc_init and
>>>       tegra_mc_init.
>>>       This implementation of configuring PMC registers thru helper
>>>       functions in clock driver needs proper changes across PMC, Clock,
>>>       EMC and MC inits to have it work across all Tegra platforms.
>>>
>>>       Currently PLLM Override is not enabled in the bootloader so 
>>> proper
>>>       patches for this fix will be taken care separately.
>> Hello Sowjanya,
>>
>> Could you please clarify what do you mean by "PLLM Override not enabled
>> in bootloader"?
>>
>> There is T124 Nyan Big Chromebook which is supported in upstream kernel,
>> it has PLLM Override set by bootloader. I also have T30 Nexus 7 tablet
>> which has the PLLM Override set by bootloader as well. It's not clear to
>> me whether this patch series is supposed to break these devices. If the
>> breakage is the case here, then I'm afraid you can't postpone supporting
>> the PLLM Override and a full-featured implementation is needed.
>
> Hi Dmitry,
>
> Secure boot currently is enabled only on Tegra210 and Tegra210 
> bootloader doesn't enable PLLM override.
>
> So PLLM override/PLLE IDDQ being in clock driver currently will not 
> break on any of existing Tegra platforms.
>
>>
>> I briefly tried to test this series on T30 and this time it doesn't hang
>> on boot, but somehow WiFi MMC card detection is broken. AFAIK, the WiFi
>> chip uses the Blink clock source and the clock should be enabled by the
>> MMC core because this is how DT part looks like:
>>
>> brcm_wifi_pwrseq: wifi-pwrseq {
>>     compatible = "mmc-pwrseq-simple";
>>     clocks = <&pmc TEGRA_PMC_CLK_BLINK>;
>>     clock-names = "ext_clock";
>>     reset-gpios =  <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>;
>>     post-power-on-delay-ms = <300>;
>>     power-off-delay-us = <300>;
>> };
>>
>> BTW, I  tried this series on a T20 device which also uses the Blink
>> clock for WiFi card and it works. So looks like this patchset has some
>> problem in regards to the T30 PMC clocks implementation.
>>
>> [snip]
>
> Blink init state is set to true for both Tegra20 and Tegra30 and all 
> go through the same blink programming sequence.
>
> Will try to add more debug messages to dump registers and will test 
> blink through device tree on T30 and will get back...
>
>
define value for BLINK uses BIT macro instead of just position. Will fix 
this in v3.

On 11/27/19 7:14 AM, Dmitry Osipenko wrote:
> 27.11.2019 07:59, Sowjanya Komatineni пишет:
>> Tegra210 and prior Tegra PMC has clk_out_1, clk_out_2, clk_out_3 with
>> mux and gate for each of these clocks.
>>
>> Currently these PMC clocks are registered by Tegra clock driver using
>> clk_register_mux and clk_register_gate by passing PMC base address
>> and register offsets and PMC programming for these clocks happens
>> through direct PMC access by the clock driver.
>>
>> With this, when PMC is in secure mode any direct PMC access from the
>> non-secure world does not go through and these clocks will not be
>> functional.
>>
>> This patch adds these clocks registration with PMC as a clock provider
>> for these clocks. clk_ops callback implementations for these clocks
>> uses tegra_pmc_readl and tegra_pmc_writel which supports PMC programming
>> in secure mode and non-secure mode.
>>
>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>> ---
>>   drivers/soc/tegra/pmc.c | 330 ++++++++++++++++++++++++++++++++++++++++++++++++
>>   1 file changed, 330 insertions(+)
>>
>> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
>> index ea0e11a09c12..a353f6d0a832 100644
>> --- a/drivers/soc/tegra/pmc.c
>> +++ b/drivers/soc/tegra/pmc.c
>> @@ -13,6 +13,9 @@
>>   
>>   #include <linux/arm-smccc.h>
>>   #include <linux/clk.h>
>> +#include <linux/clk-provider.h>
>> +#include <linux/clkdev.h>
>> +#include <linux/clk/clk-conf.h>
>>   #include <linux/clk/tegra.h>
>>   #include <linux/debugfs.h>
>>   #include <linux/delay.h>
>> @@ -48,6 +51,7 @@
>>   #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
>>   #include <dt-bindings/gpio/tegra186-gpio.h>
>>   #include <dt-bindings/gpio/tegra194-gpio.h>
>> +#include <dt-bindings/soc/tegra-pmc.h>
>>   
>>   #define PMC_CNTRL			0x0
>>   #define  PMC_CNTRL_INTR_POLARITY	BIT(17) /* inverts INTR polarity */
>> @@ -100,6 +104,7 @@
>>   #define PMC_WAKE2_STATUS		0x168
>>   #define PMC_SW_WAKE2_STATUS		0x16c
>>   
>> +#define PMC_CLK_OUT_CNTRL		0x1a8
>>   #define PMC_SENSOR_CTRL			0x1b0
>>   #define  PMC_SENSOR_CTRL_SCRATCH_WRITE	BIT(2)
>>   #define  PMC_SENSOR_CTRL_ENABLE_RST	BIT(1)
>> @@ -155,6 +160,91 @@
>>   #define  TEGRA_SMC_PMC_READ	0xaa
>>   #define  TEGRA_SMC_PMC_WRITE	0xbb
>>   
>> +struct pmc_clk_mux {
>> +	struct clk_hw	hw;
>> +	unsigned long	offs;
>> +	u32		mask;
>> +	u32		shift;
>> +};
>> +
>> +#define to_pmc_clk_mux(_hw) container_of(_hw, struct pmc_clk_mux, hw)
>> +
>> +struct pmc_clk_gate {
>> +	struct clk_hw	hw;
>> +	unsigned long	offs;
>> +	u32		shift;
>> +};
>> +
>> +#define to_pmc_clk_gate(_hw) container_of(_hw, struct pmc_clk_gate, hw)
>> +
>> +struct pmc_clk_init_data {
>> +	char *mux_name;
>> +	char *gate_name;
>> +	const char **parents;
>> +	int num_parents;
>> +	int mux_id;
>> +	int gate_id;
>> +	char *dev_name;
>> +	u8 mux_shift;
>> +	u8 gate_shift;
>> +	u8 init_parent_index;
>> +	int init_state;
>> +};
>> +
>> +static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2",
>> +	"clk_m_div4", "extern1",
>> +};
>> +
>> +static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2",
>> +	"clk_m_div4", "extern2",
>> +};
>> +
>> +static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2",
>> +	"clk_m_div4", "extern3",
>> +};
>> +
>> +static struct pmc_clk_init_data tegra_pmc_clks_data[] = {
>> +	{
>> +		.mux_name = "clk_out_1_mux",
>> +		.gate_name = "clk_out_1",
>> +		.parents = clk_out1_parents,
>> +		.num_parents = ARRAY_SIZE(clk_out1_parents),
>> +		.mux_id = TEGRA_PMC_CLK_OUT_1_MUX,
>> +		.gate_id = TEGRA_PMC_CLK_OUT_1,
>> +		.dev_name = "extern1",
>> +		.mux_shift = 6,
>> +		.gate_shift = 2,
>> +		.init_parent_index = 3,
>> +		.init_state = 1,
>> +	},
>> +	{
>> +		.mux_name = "clk_out_2_mux",
>> +		.gate_name = "clk_out_2",
>> +		.parents = clk_out2_parents,
>> +		.num_parents = ARRAY_SIZE(clk_out2_parents),
>> +		.mux_id = TEGRA_PMC_CLK_OUT_2_MUX,
>> +		.gate_id = TEGRA_PMC_CLK_OUT_2,
>> +		.dev_name = "extern2",
>> +		.mux_shift = 14,
>> +		.gate_shift = 10,
>> +		.init_parent_index = 0,
>> +		.init_state = 0,
>> +	},
>> +	{
>> +		.mux_name = "clk_out_3_mux",
>> +		.gate_name = "clk_out_3",
>> +		.parents = clk_out3_parents,
>> +		.num_parents = ARRAY_SIZE(clk_out3_parents),
>> +		.mux_id = TEGRA_PMC_CLK_OUT_3_MUX,
>> +		.gate_id = TEGRA_PMC_CLK_OUT_3,
>> +		.dev_name = "extern3",
>> +		.mux_shift = 22,
>> +		.gate_shift = 18,
>> +		.init_parent_index = 0,
>> +		.init_state = 0,
>> +	},
>> +};
>> +
>>   struct tegra_powergate {
>>   	struct generic_pm_domain genpd;
>>   	struct tegra_pmc *pmc;
>> @@ -254,6 +344,9 @@ struct tegra_pmc_soc {
>>   	 */
>>   	const struct tegra_wake_event *wake_events;
>>   	unsigned int num_wake_events;
>> +
>> +	struct pmc_clk_init_data *pmc_clks_data;
>> +	unsigned int num_pmc_clks;
>>   };
>>   
>>   static const char * const tegra186_reset_sources[] = {
>> @@ -2163,6 +2256,228 @@ static int tegra_pmc_clk_notify_cb(struct notifier_block *nb,
>>   	return NOTIFY_OK;
>>   }
>>   
>> +static void pmc_clk_fence_udelay(u32 offset)
>> +{
>> +	tegra_pmc_readl(pmc, offset);
>> +	/* pmc clk propagation delay 2 us */
>> +	udelay(2);
>> +}
>> +
>> +static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
>> +{
>> +	struct pmc_clk_mux *mux = to_pmc_clk_mux(hw);
>> +	int num_parents = clk_hw_get_num_parents(hw);
>> +	u32 val;
>> +
>> +	val = tegra_pmc_readl(pmc, mux->offs) >> mux->shift;
>> +	val &= mux->mask;
>> +
>> +	if (val >= num_parents)
>> +		return -EINVAL;
>> +
>> +	return val;
>> +}
>> +
>> +static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
>> +{
>> +	struct pmc_clk_mux *mux = to_pmc_clk_mux(hw);
>> +	u32 val;
>> +
>> +	val = tegra_pmc_readl(pmc, mux->offs);
>> +	val &= ~(mux->mask << mux->shift);
>> +	val |= index << mux->shift;
>> +	tegra_pmc_writel(pmc, val, mux->offs);
>> +	pmc_clk_fence_udelay(mux->offs);
>> +
>> +	return 0;
>> +}
>> +
>> +static const struct clk_ops pmc_clk_mux_ops = {
>> +	.get_parent = pmc_clk_mux_get_parent,
>> +	.set_parent = pmc_clk_mux_set_parent,
>> +	.determine_rate = __clk_mux_determine_rate,
>> +};
>> +
>> +static struct clk *
>> +tegra_pmc_clk_mux_register(const char *name, const char * const *parent_names,
>> +			   int num_parents, unsigned long flags,
>> +			   unsigned long offset, u32 shift, u32 mask)
>> +{
>> +	struct clk_init_data init;
>> +	struct pmc_clk_mux *mux;
>> +
>> +	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
>> +	if (!mux)
>> +		return ERR_PTR(-ENOMEM);
>> +
>> +	init.name = name;
>> +	init.ops = &pmc_clk_mux_ops;
>> +	init.parent_names = parent_names;
>> +	init.num_parents = num_parents;
>> +	init.flags = flags;
>> +
>> +	mux->hw.init = &init;
>> +	mux->offs = offset;
>> +	mux->mask = mask;
>> +	mux->shift = shift;
>> +
>> +	return clk_register(NULL, &mux->hw);
>> +}
>> +
>> +static int pmc_clk_is_enabled(struct clk_hw *hw)
>> +{
>> +	struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
>> +
>> +	return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0;
>> +}
>> +
>> +static void pmc_clk_set_state(struct clk_hw *hw, int state)
>> +{
>> +	struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
>> +	u32 val;
>> +
>> +	val = tegra_pmc_readl(pmc, gate->offs);
>> +	val = state ? (val | BIT(gate->shift)) : (val & ~BIT(gate->shift));
>> +	tegra_pmc_writel(pmc, val, gate->offs);
>> +	pmc_clk_fence_udelay(gate->offs);
>> +}
>> +
>> +static int pmc_clk_enable(struct clk_hw *hw)
>> +{
>> +	pmc_clk_set_state(hw, 1);
>> +
>> +	return 0;
>> +}
>> +
>> +static void pmc_clk_disable(struct clk_hw *hw)
>> +{
>> +	pmc_clk_set_state(hw, 0);
>> +}
>> +
>> +static const struct clk_ops pmc_clk_gate_ops = {
>> +	.is_enabled = pmc_clk_is_enabled,
>> +	.enable = pmc_clk_enable,
>> +	.disable = pmc_clk_disable,
>> +};
>> +
>> +static struct clk *
>> +tegra_pmc_clk_gate_register(const char *name, const char *parent_name,
>> +			    unsigned long flags, unsigned long offset,
>> +			    u32 shift)
>> +{
>> +	struct clk_init_data init;
>> +	struct pmc_clk_gate *gate;
>> +
>> +	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
>> +	if (!gate)
>> +		return ERR_PTR(-ENOMEM);
>> +
>> +	init.name = name;
>> +	init.ops = &pmc_clk_gate_ops;
>> +	init.parent_names = &parent_name;
>> +	init.num_parents = 1;
>> +	init.flags = flags;
>> +
>> +	gate->hw.init = &init;
>> +	gate->offs = offset;
>> +	gate->shift = shift;
>> +
>> +	return clk_register(NULL, &gate->hw);
>> +}
>> +
>> +static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
>> +				     struct device_node *np)
>> +{
>> +	struct clk *clkmux, *clk, *parent;
>> +	struct clk_onecell_data *clk_data;
>> +	unsigned int num_clks;
>> +	int i, ret;
>> +
>> +	/* each pmc clock output has a mux and a gate */
>> +	num_clks = pmc->soc->num_pmc_clks * 2;
>> +
>> +	if (!num_clks)
>> +		return;
>> +
>> +	clk_data = kmalloc(sizeof(*clk_data), GFP_KERNEL);
>> +	if (!clk_data)
>> +		return;
>> +
>> +	clk_data->clks = kcalloc(TEGRA_PMC_CLK_MAX, sizeof(*clk_data->clks),
>> +				 GFP_KERNEL);
>> +	if (!clk_data->clks)
>> +		goto free_clkdata;
>> +
>> +	clk_data->clk_num = num_clks;
>> +
>> +	for (i = 0; i < pmc->soc->num_pmc_clks; i++) {
>> +		struct pmc_clk_init_data *data;
>> +
>> +		data = pmc->soc->pmc_clks_data + i;
>> +
>> +		clkmux = tegra_pmc_clk_mux_register(data->mux_name,
>> +						    data->parents,
>> +						    data->num_parents,
>> +						    CLK_SET_RATE_NO_REPARENT |
>> +						    CLK_SET_RATE_PARENT,
>> +						    PMC_CLK_OUT_CNTRL,
>> +						    data->mux_shift, 3);
>> +		if (IS_ERR(clkmux))
>> +			goto free_clks;
>> +
>> +		clk_data->clks[data->mux_id] = clkmux;
>> +
>> +		clk = tegra_pmc_clk_gate_register(data->gate_name,
>> +						  data->mux_name,
>> +						  CLK_SET_RATE_PARENT,
>> +						  PMC_CLK_OUT_CNTRL,
>> +						  data->gate_shift);
>> +		if (IS_ERR(clk))
>> +			goto free_clks;
>> +
>> +		clk_data->clks[data->gate_id] = clk;
>> +
>> +		ret = clk_set_parent(clk, clkmux);
>> +		if (ret < 0) {
>> +			pr_err("failed to set parent of %s to %s\n",
>> +			       __func__, __clk_get_name(clk),
>> +			       __clk_get_name(clkmux));
>> +		}
>> +
>> +		clk_register_clkdev(clk, data->dev_name, data->gate_name);
>> +
>> +		/* configure initial clock parent and state */
>> +		parent = clk_get_sys(data->gate_name,
>> +				     data->parents[data->init_parent_index]);
>> +		if (!IS_ERR(parent)) {
>> +			ret = clk_set_parent(clkmux, parent);
>> +			if (ret < 0) {
>> +				pr_err("failed to set parent of %s to %s\n",
>> +				       __func__, __clk_get_name(clkmux),
>> +				       __clk_get_name(parent));
>> +				WARN_ON(1);
>> +			}
>> +		}
>> +
>> +		if (data->init_state) {
>> +			if (clk_prepare_enable(clk)) {
>> +				pr_err("failed to enable %s\n", __func__,
>> +				       __clk_get_name(clk));
>> +				WARN_ON(1);
> Should be a bit better to move the WARN_ON to the end of errors handling
> in order to catch all possible errors:
>
> @@ -2510,6 +2510,7 @@ static void tegra_pmc_clock_register(struct
> tegra_pmc *pmc,
>          return;
>
>   free_clks:
> +       WARN_ON(1);
>          kfree(clk_data->clks);
>   free_clkdata:
>          kfree(clk_data);

Reason I had WARN_ON right during clk_set_parent failure is to have the 
loop continue for subsequence pmc clocks registration instead of 
terminating all pmc clocks registration.

On Wed, Nov 27, 2019 at 05:31:34PM +0300, Dmitry Osipenko wrote:
> 27.11.2019 07:59, Sowjanya Komatineni пишет:
> > Tegra PMC has clk_out_1, clk_out_2, clk_out_3 and blink controls which
> > are currently registered by Tegra clock driver using clk_regiser_mux and
> > clk_register_gate which performs direct Tegra PMC register access.
> > 
> > When Tegra PMC is in secure mode, any access from non-secure world will
> > not go through.
> > 
> > This patch series adds these Tegra PMC clocks and blink controls to Tegra
> > PMC driver with PMC as clock provider and removed them from Tegra clock
> > driver. This also adds PMC specific clock id's to use in device tree and
> > removed clock ids of PMC clock from Tegra clock driver.
> > 
> > This series also includes patch to update clock provider from tegra_car
> > to pmc in the device tree tegra210-smaug.dts that uses clk_out_2 from PMC.
> > 
> > [v2]:	Changes between v1 and v2 are
> > 	- v2 includes patches for adding clk_out_1, clk_out_2, clk_out_3,
> > 	  blink controls to Tegra PMC driver and removing clk-tegra-pmc.
> > 	- feedback related to pmc clocks in Tegra PMC driver from v1
> > 	- Removed patches for WB0 PLLM overrides and PLLE IDDQ PMC programming
> > 	  by the clock driver using helper functions from Tegra PMC.
> > 
> >  	  Note:
> > 	  To use helper functions from PMC driver, PMC early init need to
> > 	  happen prior to using helper functions and these helper functions are
> > 	  for PLLM Override and PLLE IDDQ programming in PMC during PLLM/PLLE
> > 	  clock registration which happen in clock_init prior to Tegra PMC
> > 	  probe.
> > 	  Moving PLLM/PLLE clocks registration to happen after Tegra PMC
> > 	  impacts other clocks EMC, MC and corresponding tegra_emc_init and
> > 	  tegra_mc_init.
> > 	  This implementation of configuring PMC registers thru helper
> > 	  functions in clock driver needs proper changes across PMC, Clock,
> > 	  EMC and MC inits to have it work across all Tegra platforms.
> > 
> > 	  Currently PLLM Override is not enabled in the bootloader so proper
> > 	  patches for this fix will be taken care separately.
> 
> Hello Sowjanya,
> 
> Could you please clarify what do you mean by "PLLM Override not enabled
> in bootloader"?
> 
> There is T124 Nyan Big Chromebook which is supported in upstream kernel,
> it has PLLM Override set by bootloader. I also have T30 Nexus 7 tablet
> which has the PLLM Override set by bootloader as well. It's not clear to
> me whether this patch series is supposed to break these devices. If the
> breakage is the case here, then I'm afraid you can't postpone supporting
> the PLLM Override and a full-featured implementation is needed.

For some more background on why we chose to take this shortcut for now:
Sowjanya was looking at the full-featured implementation and that ended
up being a can of worms. The problem is that there are various inter-
dependencies between the PLLM override and the MC/EMC clocks.

Unfortunately we depend a lot on the explicit ordering of driver probe,
especially during early boot, so this started to get very complicated,
very quickly.

The bottom line was basically that we would need to move a whole bunch
of clocks to register at a very late point in time and support deferred
probe throughout in order to make it all work together nicely. Sowjanya
had a crack at that, and while the system ended up booting, there were a
number of errors from the MC and IOMMU drivers.

At the end, we decided to take a look at that separately because, as was
mentioned earlier, the PLLM override is not used on platforms where the
PMC is locked down, so the existing PLLM override code is going to
continue to work fine on the platforms where it's currently used.

Thierry

> I briefly tried to test this series on T30 and this time it doesn't hang
> on boot, but somehow WiFi MMC card detection is broken. AFAIK, the WiFi
> chip uses the Blink clock source and the clock should be enabled by the
> MMC core because this is how DT part looks like:
> 
> brcm_wifi_pwrseq: wifi-pwrseq {
> 	compatible = "mmc-pwrseq-simple";
> 	clocks = <&pmc TEGRA_PMC_CLK_BLINK>;
> 	clock-names = "ext_clock";
> 	reset-gpios =  <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>;
> 	post-power-on-delay-ms = <300>;
> 	power-off-delay-us = <300>;
> };
> 
> BTW, I  tried this series on a T20 device which also uses the Blink
> clock for WiFi card and it works. So looks like this patchset has some
> problem in regards to the T30 PMC clocks implementation.
> 
> [snip]

28.11.2019 00:38, Sowjanya Komatineni пишет:
> 
> On 11/27/19 9:02 AM, Sowjanya Komatineni wrote:
>>
>> On 11/27/19 6:31 AM, Dmitry Osipenko wrote:
>>> 27.11.2019 07:59, Sowjanya Komatineni пишет:
>>>> Tegra PMC has clk_out_1, clk_out_2, clk_out_3 and blink controls which
>>>> are currently registered by Tegra clock driver using clk_regiser_mux
>>>> and
>>>> clk_register_gate which performs direct Tegra PMC register access.
>>>>
>>>> When Tegra PMC is in secure mode, any access from non-secure world will
>>>> not go through.
>>>>
>>>> This patch series adds these Tegra PMC clocks and blink controls to
>>>> Tegra
>>>> PMC driver with PMC as clock provider and removed them from Tegra clock
>>>> driver. This also adds PMC specific clock id's to use in device tree
>>>> and
>>>> removed clock ids of PMC clock from Tegra clock driver.
>>>>
>>>> This series also includes patch to update clock provider from tegra_car
>>>> to pmc in the device tree tegra210-smaug.dts that uses clk_out_2
>>>> from PMC.
>>>>
>>>> [v2]:    Changes between v1 and v2 are
>>>>     - v2 includes patches for adding clk_out_1, clk_out_2, clk_out_3,
>>>>       blink controls to Tegra PMC driver and removing clk-tegra-pmc.
>>>>     - feedback related to pmc clocks in Tegra PMC driver from v1
>>>>     - Removed patches for WB0 PLLM overrides and PLLE IDDQ PMC
>>>> programming
>>>>       by the clock driver using helper functions from Tegra PMC.
>>>>
>>>>         Note:
>>>>       To use helper functions from PMC driver, PMC early init need to
>>>>       happen prior to using helper functions and these helper
>>>> functions are
>>>>       for PLLM Override and PLLE IDDQ programming in PMC during
>>>> PLLM/PLLE
>>>>       clock registration which happen in clock_init prior to Tegra PMC
>>>>       probe.
>>>>       Moving PLLM/PLLE clocks registration to happen after Tegra PMC
>>>>       impacts other clocks EMC, MC and corresponding tegra_emc_init and
>>>>       tegra_mc_init.
>>>>       This implementation of configuring PMC registers thru helper
>>>>       functions in clock driver needs proper changes across PMC, Clock,
>>>>       EMC and MC inits to have it work across all Tegra platforms.
>>>>
>>>>       Currently PLLM Override is not enabled in the bootloader so
>>>> proper
>>>>       patches for this fix will be taken care separately.
>>> Hello Sowjanya,
>>>
>>> Could you please clarify what do you mean by "PLLM Override not enabled
>>> in bootloader"?
>>>
>>> There is T124 Nyan Big Chromebook which is supported in upstream kernel,
>>> it has PLLM Override set by bootloader. I also have T30 Nexus 7 tablet
>>> which has the PLLM Override set by bootloader as well. It's not clear to
>>> me whether this patch series is supposed to break these devices. If the
>>> breakage is the case here, then I'm afraid you can't postpone supporting
>>> the PLLM Override and a full-featured implementation is needed.
>>
>> Hi Dmitry,
>>
>> Secure boot currently is enabled only on Tegra210 and Tegra210
>> bootloader doesn't enable PLLM override.
>>
>> So PLLM override/PLLE IDDQ being in clock driver currently will not
>> break on any of existing Tegra platforms.
>>
>>>
>>> I briefly tried to test this series on T30 and this time it doesn't hang
>>> on boot, but somehow WiFi MMC card detection is broken. AFAIK, the WiFi
>>> chip uses the Blink clock source and the clock should be enabled by the
>>> MMC core because this is how DT part looks like:
>>>
>>> brcm_wifi_pwrseq: wifi-pwrseq {
>>>     compatible = "mmc-pwrseq-simple";
>>>     clocks = <&pmc TEGRA_PMC_CLK_BLINK>;
>>>     clock-names = "ext_clock";
>>>     reset-gpios =  <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>;
>>>     post-power-on-delay-ms = <300>;
>>>     power-off-delay-us = <300>;
>>> };
>>>
>>> BTW, I  tried this series on a T20 device which also uses the Blink
>>> clock for WiFi card and it works. So looks like this patchset has some
>>> problem in regards to the T30 PMC clocks implementation.
>>>
>>> [snip]
>>
>> Blink init state is set to true for both Tegra20 and Tegra30 and all
>> go through the same blink programming sequence.
>>
>> Will try to add more debug messages to dump registers and will test
>> blink through device tree on T30 and will get back...
>>
>>
> define value for BLINK uses BIT macro instead of just position. Will fix
> this in v3.

Thanks, will try v3 once it will be ready.

I took a look through the T20 board's schematics and seems it doesn't
use the Blink clock for the WiFi, instead it uses 32k source directly
from PMU. While T30 board schematics tells that  32k comes out from the
Tegra chip.

BTW, I'm curious what's the reason for having Blink clock always-ON on
T20/30, any insights? Looks like it's just some relic from old clk
driver and it should be safe to drop the always-ON.

27.11.2019 07:59, Sowjanya Komatineni пишет:
> Tegra PMC has blink control to output 32 Khz clock out to Tegra
> blink pin. Blink pad DPD state and enable controls are part of
> Tegra PMC register space.
> 
> Currently Tegra clock driver registers blink control by passing
> PMC address and register offset to clk_register_gate which performs
> direct PMC access during clk_ops and with this when PMC is in secure
> mode, any access from non-secure world does not go through.
> 
> This patch adds blink control registration to the Tegra PMC driver
> using PMC specific clock gate operations that use tegra_pmc_readl
> and tegra_pmc_writel to support both secure mode and non-secure
> mode PMC register access.
> 
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
>  drivers/soc/tegra/pmc.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 49 insertions(+)
> 
> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
> index a353f6d0a832..1cfb7797dbd5 100644
> --- a/drivers/soc/tegra/pmc.c
> +++ b/drivers/soc/tegra/pmc.c
> @@ -61,12 +61,15 @@
>  #define  PMC_CNTRL_SYSCLK_OE		BIT(11) /* system clock enable */
>  #define  PMC_CNTRL_SYSCLK_POLARITY	BIT(10) /* sys clk polarity */
>  #define  PMC_CNTRL_PWRREQ_POLARITY	BIT(8)
> +#define  PMC_CNTRL_BLINK_EN		BIT(7)
>  #define  PMC_CNTRL_MAIN_RST		BIT(4)
>  
>  #define PMC_WAKE_MASK			0x0c
>  #define PMC_WAKE_LEVEL			0x10
>  #define PMC_WAKE_STATUS			0x14
>  #define PMC_SW_WAKE_STATUS		0x18
> +#define PMC_DPD_PADS_ORIDE		0x1c
> +#define  PMC_DPD_PADS_ORIDE_BLINK	BIT(20)
>  
>  #define DPD_SAMPLE			0x020
>  #define  DPD_SAMPLE_ENABLE		BIT(0)
> @@ -79,6 +82,7 @@
>  
>  #define PWRGATE_STATUS			0x38
>  
> +#define TEGRA210_PMC_BLINK_TIMER	0x40

This register is common for all Tegra SoCs, therefore TEGRA210_ prefix
isn't needed.

28.11.2019 15:26, Thierry Reding пишет:
> On Wed, Nov 27, 2019 at 05:31:34PM +0300, Dmitry Osipenko wrote:
>> 27.11.2019 07:59, Sowjanya Komatineni пишет:
>>> Tegra PMC has clk_out_1, clk_out_2, clk_out_3 and blink controls which
>>> are currently registered by Tegra clock driver using clk_regiser_mux and
>>> clk_register_gate which performs direct Tegra PMC register access.
>>>
>>> When Tegra PMC is in secure mode, any access from non-secure world will
>>> not go through.
>>>
>>> This patch series adds these Tegra PMC clocks and blink controls to Tegra
>>> PMC driver with PMC as clock provider and removed them from Tegra clock
>>> driver. This also adds PMC specific clock id's to use in device tree and
>>> removed clock ids of PMC clock from Tegra clock driver.
>>>
>>> This series also includes patch to update clock provider from tegra_car
>>> to pmc in the device tree tegra210-smaug.dts that uses clk_out_2 from PMC.
>>>
>>> [v2]:	Changes between v1 and v2 are
>>> 	- v2 includes patches for adding clk_out_1, clk_out_2, clk_out_3,
>>> 	  blink controls to Tegra PMC driver and removing clk-tegra-pmc.
>>> 	- feedback related to pmc clocks in Tegra PMC driver from v1
>>> 	- Removed patches for WB0 PLLM overrides and PLLE IDDQ PMC programming
>>> 	  by the clock driver using helper functions from Tegra PMC.
>>>
>>>  	  Note:
>>> 	  To use helper functions from PMC driver, PMC early init need to
>>> 	  happen prior to using helper functions and these helper functions are
>>> 	  for PLLM Override and PLLE IDDQ programming in PMC during PLLM/PLLE
>>> 	  clock registration which happen in clock_init prior to Tegra PMC
>>> 	  probe.
>>> 	  Moving PLLM/PLLE clocks registration to happen after Tegra PMC
>>> 	  impacts other clocks EMC, MC and corresponding tegra_emc_init and
>>> 	  tegra_mc_init.
>>> 	  This implementation of configuring PMC registers thru helper
>>> 	  functions in clock driver needs proper changes across PMC, Clock,
>>> 	  EMC and MC inits to have it work across all Tegra platforms.
>>>
>>> 	  Currently PLLM Override is not enabled in the bootloader so proper
>>> 	  patches for this fix will be taken care separately.
>>
>> Hello Sowjanya,
>>
>> Could you please clarify what do you mean by "PLLM Override not enabled
>> in bootloader"?
>>
>> There is T124 Nyan Big Chromebook which is supported in upstream kernel,
>> it has PLLM Override set by bootloader. I also have T30 Nexus 7 tablet
>> which has the PLLM Override set by bootloader as well. It's not clear to
>> me whether this patch series is supposed to break these devices. If the
>> breakage is the case here, then I'm afraid you can't postpone supporting
>> the PLLM Override and a full-featured implementation is needed.
> 
> For some more background on why we chose to take this shortcut for now:
> Sowjanya was looking at the full-featured implementation and that ended
> up being a can of worms. The problem is that there are various inter-
> dependencies between the PLLM override and the MC/EMC clocks.
> 
> Unfortunately we depend a lot on the explicit ordering of driver probe,
> especially during early boot, so this started to get very complicated,
> very quickly.
> 
> The bottom line was basically that we would need to move a whole bunch
> of clocks to register at a very late point in time and support deferred
> probe throughout in order to make it all work together nicely. Sowjanya
> had a crack at that, and while the system ended up booting, there were a
> number of errors from the MC and IOMMU drivers.
> 
> At the end, we decided to take a look at that separately because, as was
> mentioned earlier, the PLLM override is not used on platforms where the
> PMC is locked down, so the existing PLLM override code is going to
> continue to work fine on the platforms where it's currently used.
> 
> Thierry

Thank you and Sowjanya for the clarification.

[snip]

28.11.2019 01:57, Sowjanya Komatineni пишет:
> 
> On 11/27/19 7:14 AM, Dmitry Osipenko wrote:
>> 27.11.2019 07:59, Sowjanya Komatineni пишет:
>>> Tegra210 and prior Tegra PMC has clk_out_1, clk_out_2, clk_out_3 with
>>> mux and gate for each of these clocks.
>>>
>>> Currently these PMC clocks are registered by Tegra clock driver using
>>> clk_register_mux and clk_register_gate by passing PMC base address
>>> and register offsets and PMC programming for these clocks happens
>>> through direct PMC access by the clock driver.
>>>
>>> With this, when PMC is in secure mode any direct PMC access from the
>>> non-secure world does not go through and these clocks will not be
>>> functional.
>>>
>>> This patch adds these clocks registration with PMC as a clock provider
>>> for these clocks. clk_ops callback implementations for these clocks
>>> uses tegra_pmc_readl and tegra_pmc_writel which supports PMC programming
>>> in secure mode and non-secure mode.
>>>
>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>> ---
>>>   drivers/soc/tegra/pmc.c | 330
>>> ++++++++++++++++++++++++++++++++++++++++++++++++
>>>   1 file changed, 330 insertions(+)
>>>
>>> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
>>> index ea0e11a09c12..a353f6d0a832 100644
>>> --- a/drivers/soc/tegra/pmc.c
>>> +++ b/drivers/soc/tegra/pmc.c
>>> @@ -13,6 +13,9 @@
>>>     #include <linux/arm-smccc.h>
>>>   #include <linux/clk.h>
>>> +#include <linux/clk-provider.h>
>>> +#include <linux/clkdev.h>
>>> +#include <linux/clk/clk-conf.h>
>>>   #include <linux/clk/tegra.h>
>>>   #include <linux/debugfs.h>
>>>   #include <linux/delay.h>
>>> @@ -48,6 +51,7 @@
>>>   #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
>>>   #include <dt-bindings/gpio/tegra186-gpio.h>
>>>   #include <dt-bindings/gpio/tegra194-gpio.h>
>>> +#include <dt-bindings/soc/tegra-pmc.h>
>>>     #define PMC_CNTRL            0x0
>>>   #define  PMC_CNTRL_INTR_POLARITY    BIT(17) /* inverts INTR
>>> polarity */
>>> @@ -100,6 +104,7 @@
>>>   #define PMC_WAKE2_STATUS        0x168
>>>   #define PMC_SW_WAKE2_STATUS        0x16c
>>>   +#define PMC_CLK_OUT_CNTRL        0x1a8
>>>   #define PMC_SENSOR_CTRL            0x1b0
>>>   #define  PMC_SENSOR_CTRL_SCRATCH_WRITE    BIT(2)
>>>   #define  PMC_SENSOR_CTRL_ENABLE_RST    BIT(1)
>>> @@ -155,6 +160,91 @@
>>>   #define  TEGRA_SMC_PMC_READ    0xaa
>>>   #define  TEGRA_SMC_PMC_WRITE    0xbb
>>>   +struct pmc_clk_mux {
>>> +    struct clk_hw    hw;
>>> +    unsigned long    offs;
>>> +    u32        mask;
>>> +    u32        shift;
>>> +};
>>> +
>>> +#define to_pmc_clk_mux(_hw) container_of(_hw, struct pmc_clk_mux, hw)
>>> +
>>> +struct pmc_clk_gate {
>>> +    struct clk_hw    hw;
>>> +    unsigned long    offs;
>>> +    u32        shift;
>>> +};
>>> +
>>> +#define to_pmc_clk_gate(_hw) container_of(_hw, struct pmc_clk_gate, hw)
>>> +
>>> +struct pmc_clk_init_data {
>>> +    char *mux_name;
>>> +    char *gate_name;
>>> +    const char **parents;
>>> +    int num_parents;
>>> +    int mux_id;
>>> +    int gate_id;
>>> +    char *dev_name;
>>> +    u8 mux_shift;
>>> +    u8 gate_shift;
>>> +    u8 init_parent_index;
>>> +    int init_state;
>>> +};
>>> +
>>> +static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2",
>>> +    "clk_m_div4", "extern1",
>>> +};
>>> +
>>> +static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2",
>>> +    "clk_m_div4", "extern2",
>>> +};
>>> +
>>> +static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2",
>>> +    "clk_m_div4", "extern3",
>>> +};
>>> +
>>> +static struct pmc_clk_init_data tegra_pmc_clks_data[] = {
>>> +    {
>>> +        .mux_name = "clk_out_1_mux",
>>> +        .gate_name = "clk_out_1",
>>> +        .parents = clk_out1_parents,
>>> +        .num_parents = ARRAY_SIZE(clk_out1_parents),
>>> +        .mux_id = TEGRA_PMC_CLK_OUT_1_MUX,
>>> +        .gate_id = TEGRA_PMC_CLK_OUT_1,
>>> +        .dev_name = "extern1",
>>> +        .mux_shift = 6,
>>> +        .gate_shift = 2,
>>> +        .init_parent_index = 3,
>>> +        .init_state = 1,
>>> +    },
>>> +    {
>>> +        .mux_name = "clk_out_2_mux",
>>> +        .gate_name = "clk_out_2",
>>> +        .parents = clk_out2_parents,
>>> +        .num_parents = ARRAY_SIZE(clk_out2_parents),
>>> +        .mux_id = TEGRA_PMC_CLK_OUT_2_MUX,
>>> +        .gate_id = TEGRA_PMC_CLK_OUT_2,
>>> +        .dev_name = "extern2",
>>> +        .mux_shift = 14,
>>> +        .gate_shift = 10,
>>> +        .init_parent_index = 0,
>>> +        .init_state = 0,
>>> +    },
>>> +    {
>>> +        .mux_name = "clk_out_3_mux",
>>> +        .gate_name = "clk_out_3",
>>> +        .parents = clk_out3_parents,
>>> +        .num_parents = ARRAY_SIZE(clk_out3_parents),
>>> +        .mux_id = TEGRA_PMC_CLK_OUT_3_MUX,
>>> +        .gate_id = TEGRA_PMC_CLK_OUT_3,
>>> +        .dev_name = "extern3",
>>> +        .mux_shift = 22,
>>> +        .gate_shift = 18,
>>> +        .init_parent_index = 0,
>>> +        .init_state = 0,
>>> +    },
>>> +};
>>> +
>>>   struct tegra_powergate {
>>>       struct generic_pm_domain genpd;
>>>       struct tegra_pmc *pmc;
>>> @@ -254,6 +344,9 @@ struct tegra_pmc_soc {
>>>        */
>>>       const struct tegra_wake_event *wake_events;
>>>       unsigned int num_wake_events;
>>> +
>>> +    struct pmc_clk_init_data *pmc_clks_data;
>>> +    unsigned int num_pmc_clks;
>>>   };
>>>     static const char * const tegra186_reset_sources[] = {
>>> @@ -2163,6 +2256,228 @@ static int tegra_pmc_clk_notify_cb(struct
>>> notifier_block *nb,
>>>       return NOTIFY_OK;
>>>   }
>>>   +static void pmc_clk_fence_udelay(u32 offset)
>>> +{
>>> +    tegra_pmc_readl(pmc, offset);
>>> +    /* pmc clk propagation delay 2 us */
>>> +    udelay(2);
>>> +}
>>> +
>>> +static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
>>> +{
>>> +    struct pmc_clk_mux *mux = to_pmc_clk_mux(hw);
>>> +    int num_parents = clk_hw_get_num_parents(hw);
>>> +    u32 val;
>>> +
>>> +    val = tegra_pmc_readl(pmc, mux->offs) >> mux->shift;
>>> +    val &= mux->mask;
>>> +
>>> +    if (val >= num_parents)
>>> +        return -EINVAL;
>>> +
>>> +    return val;
>>> +}
>>> +
>>> +static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
>>> +{
>>> +    struct pmc_clk_mux *mux = to_pmc_clk_mux(hw);
>>> +    u32 val;
>>> +
>>> +    val = tegra_pmc_readl(pmc, mux->offs);
>>> +    val &= ~(mux->mask << mux->shift);
>>> +    val |= index << mux->shift;
>>> +    tegra_pmc_writel(pmc, val, mux->offs);
>>> +    pmc_clk_fence_udelay(mux->offs);
>>> +
>>> +    return 0;
>>> +}
>>> +
>>> +static const struct clk_ops pmc_clk_mux_ops = {
>>> +    .get_parent = pmc_clk_mux_get_parent,
>>> +    .set_parent = pmc_clk_mux_set_parent,
>>> +    .determine_rate = __clk_mux_determine_rate,
>>> +};
>>> +
>>> +static struct clk *
>>> +tegra_pmc_clk_mux_register(const char *name, const char * const
>>> *parent_names,
>>> +               int num_parents, unsigned long flags,
>>> +               unsigned long offset, u32 shift, u32 mask)
>>> +{
>>> +    struct clk_init_data init;
>>> +    struct pmc_clk_mux *mux;
>>> +
>>> +    mux = kzalloc(sizeof(*mux), GFP_KERNEL);
>>> +    if (!mux)
>>> +        return ERR_PTR(-ENOMEM);
>>> +
>>> +    init.name = name;
>>> +    init.ops = &pmc_clk_mux_ops;
>>> +    init.parent_names = parent_names;
>>> +    init.num_parents = num_parents;
>>> +    init.flags = flags;
>>> +
>>> +    mux->hw.init = &init;
>>> +    mux->offs = offset;
>>> +    mux->mask = mask;
>>> +    mux->shift = shift;
>>> +
>>> +    return clk_register(NULL, &mux->hw);
>>> +}
>>> +
>>> +static int pmc_clk_is_enabled(struct clk_hw *hw)
>>> +{
>>> +    struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
>>> +
>>> +    return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0;
>>> +}
>>> +
>>> +static void pmc_clk_set_state(struct clk_hw *hw, int state)
>>> +{
>>> +    struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
>>> +    u32 val;
>>> +
>>> +    val = tegra_pmc_readl(pmc, gate->offs);
>>> +    val = state ? (val | BIT(gate->shift)) : (val & ~BIT(gate->shift));
>>> +    tegra_pmc_writel(pmc, val, gate->offs);
>>> +    pmc_clk_fence_udelay(gate->offs);
>>> +}
>>> +
>>> +static int pmc_clk_enable(struct clk_hw *hw)
>>> +{
>>> +    pmc_clk_set_state(hw, 1);
>>> +
>>> +    return 0;
>>> +}
>>> +
>>> +static void pmc_clk_disable(struct clk_hw *hw)
>>> +{
>>> +    pmc_clk_set_state(hw, 0);
>>> +}
>>> +
>>> +static const struct clk_ops pmc_clk_gate_ops = {
>>> +    .is_enabled = pmc_clk_is_enabled,
>>> +    .enable = pmc_clk_enable,
>>> +    .disable = pmc_clk_disable,
>>> +};
>>> +
>>> +static struct clk *
>>> +tegra_pmc_clk_gate_register(const char *name, const char *parent_name,
>>> +                unsigned long flags, unsigned long offset,
>>> +                u32 shift)
>>> +{
>>> +    struct clk_init_data init;
>>> +    struct pmc_clk_gate *gate;
>>> +
>>> +    gate = kzalloc(sizeof(*gate), GFP_KERNEL);
>>> +    if (!gate)
>>> +        return ERR_PTR(-ENOMEM);
>>> +
>>> +    init.name = name;
>>> +    init.ops = &pmc_clk_gate_ops;
>>> +    init.parent_names = &parent_name;
>>> +    init.num_parents = 1;
>>> +    init.flags = flags;
>>> +
>>> +    gate->hw.init = &init;
>>> +    gate->offs = offset;
>>> +    gate->shift = shift;
>>> +
>>> +    return clk_register(NULL, &gate->hw);
>>> +}
>>> +
>>> +static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
>>> +                     struct device_node *np)
>>> +{
>>> +    struct clk *clkmux, *clk, *parent;
>>> +    struct clk_onecell_data *clk_data;
>>> +    unsigned int num_clks;
>>> +    int i, ret;
>>> +
>>> +    /* each pmc clock output has a mux and a gate */
>>> +    num_clks = pmc->soc->num_pmc_clks * 2;
>>> +
>>> +    if (!num_clks)
>>> +        return;
>>> +
>>> +    clk_data = kmalloc(sizeof(*clk_data), GFP_KERNEL);
>>> +    if (!clk_data)
>>> +        return;
>>> +
>>> +    clk_data->clks = kcalloc(TEGRA_PMC_CLK_MAX,
>>> sizeof(*clk_data->clks),
>>> +                 GFP_KERNEL);
>>> +    if (!clk_data->clks)
>>> +        goto free_clkdata;
>>> +
>>> +    clk_data->clk_num = num_clks;
>>> +
>>> +    for (i = 0; i < pmc->soc->num_pmc_clks; i++) {
>>> +        struct pmc_clk_init_data *data;
>>> +
>>> +        data = pmc->soc->pmc_clks_data + i;
>>> +
>>> +        clkmux = tegra_pmc_clk_mux_register(data->mux_name,
>>> +                            data->parents,
>>> +                            data->num_parents,
>>> +                            CLK_SET_RATE_NO_REPARENT |
>>> +                            CLK_SET_RATE_PARENT,
>>> +                            PMC_CLK_OUT_CNTRL,
>>> +                            data->mux_shift, 3);
>>> +        if (IS_ERR(clkmux))
>>> +            goto free_clks;
>>> +
>>> +        clk_data->clks[data->mux_id] = clkmux;
>>> +
>>> +        clk = tegra_pmc_clk_gate_register(data->gate_name,
>>> +                          data->mux_name,
>>> +                          CLK_SET_RATE_PARENT,
>>> +                          PMC_CLK_OUT_CNTRL,
>>> +                          data->gate_shift);
>>> +        if (IS_ERR(clk))
>>> +            goto free_clks;
>>> +
>>> +        clk_data->clks[data->gate_id] = clk;
>>> +
>>> +        ret = clk_set_parent(clk, clkmux);
>>> +        if (ret < 0) {
>>> +            pr_err("failed to set parent of %s to %s\n",
>>> +                   __func__, __clk_get_name(clk),
>>> +                   __clk_get_name(clkmux));
>>> +        }
>>> +
>>> +        clk_register_clkdev(clk, data->dev_name, data->gate_name);
>>> +
>>> +        /* configure initial clock parent and state */
>>> +        parent = clk_get_sys(data->gate_name,
>>> +                     data->parents[data->init_parent_index]);
>>> +        if (!IS_ERR(parent)) {
>>> +            ret = clk_set_parent(clkmux, parent);
>>> +            if (ret < 0) {
>>> +                pr_err("failed to set parent of %s to %s\n",
>>> +                       __func__, __clk_get_name(clkmux),
>>> +                       __clk_get_name(parent));
>>> +                WARN_ON(1);
>>> +            }
>>> +        }
>>> +
>>> +        if (data->init_state) {
>>> +            if (clk_prepare_enable(clk)) {
>>> +                pr_err("failed to enable %s\n", __func__,
>>> +                       __clk_get_name(clk));
>>> +                WARN_ON(1);

Alternatively you could write it like this:

	err = clk_prepare_enable(clk);

	WARN_ON(err, "failed to enable %s: %d\n",
		__clk_get_name(clk), err);

>> Should be a bit better to move the WARN_ON to the end of errors handling
>> in order to catch all possible errors:
>>
>> @@ -2510,6 +2510,7 @@ static void tegra_pmc_clock_register(struct
>> tegra_pmc *pmc,
>>          return;
>>
>>   free_clks:
>> +       WARN_ON(1);
>>          kfree(clk_data->clks);
>>   free_clkdata:
>>          kfree(clk_data);
> 
> Reason I had WARN_ON right during clk_set_parent failure is to have the
> loop continue for subsequence pmc clocks registration instead of
> terminating all pmc clocks registration.

Ah, okay. Nevertheless this WARN_ON in the end shouldn't be the least (IMO).

28.11.2019 16:06, Dmitry Osipenko пишет:
> 28.11.2019 00:38, Sowjanya Komatineni пишет:
>>
>> On 11/27/19 9:02 AM, Sowjanya Komatineni wrote:
>>>
>>> On 11/27/19 6:31 AM, Dmitry Osipenko wrote:
>>>> 27.11.2019 07:59, Sowjanya Komatineni пишет:
>>>>> Tegra PMC has clk_out_1, clk_out_2, clk_out_3 and blink controls which
>>>>> are currently registered by Tegra clock driver using clk_regiser_mux
>>>>> and
>>>>> clk_register_gate which performs direct Tegra PMC register access.
>>>>>
>>>>> When Tegra PMC is in secure mode, any access from non-secure world will
>>>>> not go through.
>>>>>
>>>>> This patch series adds these Tegra PMC clocks and blink controls to
>>>>> Tegra
>>>>> PMC driver with PMC as clock provider and removed them from Tegra clock
>>>>> driver. This also adds PMC specific clock id's to use in device tree
>>>>> and
>>>>> removed clock ids of PMC clock from Tegra clock driver.
>>>>>
>>>>> This series also includes patch to update clock provider from tegra_car
>>>>> to pmc in the device tree tegra210-smaug.dts that uses clk_out_2
>>>>> from PMC.
>>>>>
>>>>> [v2]:    Changes between v1 and v2 are
>>>>>     - v2 includes patches for adding clk_out_1, clk_out_2, clk_out_3,
>>>>>       blink controls to Tegra PMC driver and removing clk-tegra-pmc.
>>>>>     - feedback related to pmc clocks in Tegra PMC driver from v1
>>>>>     - Removed patches for WB0 PLLM overrides and PLLE IDDQ PMC
>>>>> programming
>>>>>       by the clock driver using helper functions from Tegra PMC.
>>>>>
>>>>>         Note:
>>>>>       To use helper functions from PMC driver, PMC early init need to
>>>>>       happen prior to using helper functions and these helper
>>>>> functions are
>>>>>       for PLLM Override and PLLE IDDQ programming in PMC during
>>>>> PLLM/PLLE
>>>>>       clock registration which happen in clock_init prior to Tegra PMC
>>>>>       probe.
>>>>>       Moving PLLM/PLLE clocks registration to happen after Tegra PMC
>>>>>       impacts other clocks EMC, MC and corresponding tegra_emc_init and
>>>>>       tegra_mc_init.
>>>>>       This implementation of configuring PMC registers thru helper
>>>>>       functions in clock driver needs proper changes across PMC, Clock,
>>>>>       EMC and MC inits to have it work across all Tegra platforms.
>>>>>
>>>>>       Currently PLLM Override is not enabled in the bootloader so
>>>>> proper
>>>>>       patches for this fix will be taken care separately.
>>>> Hello Sowjanya,
>>>>
>>>> Could you please clarify what do you mean by "PLLM Override not enabled
>>>> in bootloader"?
>>>>
>>>> There is T124 Nyan Big Chromebook which is supported in upstream kernel,
>>>> it has PLLM Override set by bootloader. I also have T30 Nexus 7 tablet
>>>> which has the PLLM Override set by bootloader as well. It's not clear to
>>>> me whether this patch series is supposed to break these devices. If the
>>>> breakage is the case here, then I'm afraid you can't postpone supporting
>>>> the PLLM Override and a full-featured implementation is needed.
>>>
>>> Hi Dmitry,
>>>
>>> Secure boot currently is enabled only on Tegra210 and Tegra210
>>> bootloader doesn't enable PLLM override.
>>>
>>> So PLLM override/PLLE IDDQ being in clock driver currently will not
>>> break on any of existing Tegra platforms.
>>>
>>>>
>>>> I briefly tried to test this series on T30 and this time it doesn't hang
>>>> on boot, but somehow WiFi MMC card detection is broken. AFAIK, the WiFi
>>>> chip uses the Blink clock source and the clock should be enabled by the
>>>> MMC core because this is how DT part looks like:
>>>>
>>>> brcm_wifi_pwrseq: wifi-pwrseq {
>>>>     compatible = "mmc-pwrseq-simple";
>>>>     clocks = <&pmc TEGRA_PMC_CLK_BLINK>;
>>>>     clock-names = "ext_clock";
>>>>     reset-gpios =  <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>;
>>>>     post-power-on-delay-ms = <300>;
>>>>     power-off-delay-us = <300>;
>>>> };
>>>>
>>>> BTW, I  tried this series on a T20 device which also uses the Blink
>>>> clock for WiFi card and it works. So looks like this patchset has some
>>>> problem in regards to the T30 PMC clocks implementation.
>>>>
>>>> [snip]
>>>
>>> Blink init state is set to true for both Tegra20 and Tegra30 and all
>>> go through the same blink programming sequence.
>>>
>>> Will try to add more debug messages to dump registers and will test
>>> blink through device tree on T30 and will get back...
>>>
>>>
>> define value for BLINK uses BIT macro instead of just position. Will fix
>> this in v3.
> 
> Thanks, will try v3 once it will be ready.
> 
> I took a look through the T20 board's schematics and seems it doesn't
> use the Blink clock for the WiFi, instead it uses 32k source directly
> from PMU. While T30 board schematics tells that  32k comes out from the
> Tegra chip.

That was wrong, both T20 and T30 are identical in regards to the clk32k
wiring. I'm not sure what's difference between T20 and T30 that made
WiFi card not to work without the blink clock on T30, maybe it's a WiFi
chip difference.

> BTW, I'm curious what's the reason for having Blink clock always-ON on
> T20/30, any insights? Looks like it's just some relic from old clk
> driver and it should be safe to drop the always-ON.
>

On 11/28/19 5:06 AM, Dmitry Osipenko wrote:
> 28.11.2019 00:38, Sowjanya Komatineni пишет:
>> On 11/27/19 9:02 AM, Sowjanya Komatineni wrote:
>>> On 11/27/19 6:31 AM, Dmitry Osipenko wrote:
>>>> 27.11.2019 07:59, Sowjanya Komatineni пишет:
>>>>> Tegra PMC has clk_out_1, clk_out_2, clk_out_3 and blink controls which
>>>>> are currently registered by Tegra clock driver using clk_regiser_mux
>>>>> and
>>>>> clk_register_gate which performs direct Tegra PMC register access.
>>>>>
>>>>> When Tegra PMC is in secure mode, any access from non-secure world will
>>>>> not go through.
>>>>>
>>>>> This patch series adds these Tegra PMC clocks and blink controls to
>>>>> Tegra
>>>>> PMC driver with PMC as clock provider and removed them from Tegra clock
>>>>> driver. This also adds PMC specific clock id's to use in device tree
>>>>> and
>>>>> removed clock ids of PMC clock from Tegra clock driver.
>>>>>
>>>>> This series also includes patch to update clock provider from tegra_car
>>>>> to pmc in the device tree tegra210-smaug.dts that uses clk_out_2
>>>>> from PMC.
>>>>>
>>>>> [v2]:    Changes between v1 and v2 are
>>>>>      - v2 includes patches for adding clk_out_1, clk_out_2, clk_out_3,
>>>>>        blink controls to Tegra PMC driver and removing clk-tegra-pmc.
>>>>>      - feedback related to pmc clocks in Tegra PMC driver from v1
>>>>>      - Removed patches for WB0 PLLM overrides and PLLE IDDQ PMC
>>>>> programming
>>>>>        by the clock driver using helper functions from Tegra PMC.
>>>>>
>>>>>          Note:
>>>>>        To use helper functions from PMC driver, PMC early init need to
>>>>>        happen prior to using helper functions and these helper
>>>>> functions are
>>>>>        for PLLM Override and PLLE IDDQ programming in PMC during
>>>>> PLLM/PLLE
>>>>>        clock registration which happen in clock_init prior to Tegra PMC
>>>>>        probe.
>>>>>        Moving PLLM/PLLE clocks registration to happen after Tegra PMC
>>>>>        impacts other clocks EMC, MC and corresponding tegra_emc_init and
>>>>>        tegra_mc_init.
>>>>>        This implementation of configuring PMC registers thru helper
>>>>>        functions in clock driver needs proper changes across PMC, Clock,
>>>>>        EMC and MC inits to have it work across all Tegra platforms.
>>>>>
>>>>>        Currently PLLM Override is not enabled in the bootloader so
>>>>> proper
>>>>>        patches for this fix will be taken care separately.
>>>> Hello Sowjanya,
>>>>
>>>> Could you please clarify what do you mean by "PLLM Override not enabled
>>>> in bootloader"?
>>>>
>>>> There is T124 Nyan Big Chromebook which is supported in upstream kernel,
>>>> it has PLLM Override set by bootloader. I also have T30 Nexus 7 tablet
>>>> which has the PLLM Override set by bootloader as well. It's not clear to
>>>> me whether this patch series is supposed to break these devices. If the
>>>> breakage is the case here, then I'm afraid you can't postpone supporting
>>>> the PLLM Override and a full-featured implementation is needed.
>>> Hi Dmitry,
>>>
>>> Secure boot currently is enabled only on Tegra210 and Tegra210
>>> bootloader doesn't enable PLLM override.
>>>
>>> So PLLM override/PLLE IDDQ being in clock driver currently will not
>>> break on any of existing Tegra platforms.
>>>
>>>> I briefly tried to test this series on T30 and this time it doesn't hang
>>>> on boot, but somehow WiFi MMC card detection is broken. AFAIK, the WiFi
>>>> chip uses the Blink clock source and the clock should be enabled by the
>>>> MMC core because this is how DT part looks like:
>>>>
>>>> brcm_wifi_pwrseq: wifi-pwrseq {
>>>>      compatible = "mmc-pwrseq-simple";
>>>>      clocks = <&pmc TEGRA_PMC_CLK_BLINK>;
>>>>      clock-names = "ext_clock";
>>>>      reset-gpios =  <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>;
>>>>      post-power-on-delay-ms = <300>;
>>>>      power-off-delay-us = <300>;
>>>> };
>>>>
>>>> BTW, I  tried this series on a T20 device which also uses the Blink
>>>> clock for WiFi card and it works. So looks like this patchset has some
>>>> problem in regards to the T30 PMC clocks implementation.
>>>>
>>>> [snip]
>>> Blink init state is set to true for both Tegra20 and Tegra30 and all
>>> go through the same blink programming sequence.
>>>
>>> Will try to add more debug messages to dump registers and will test
>>> blink through device tree on T30 and will get back...
>>>
>>>
>> define value for BLINK uses BIT macro instead of just position. Will fix
>> this in v3.
> Thanks, will try v3 once it will be ready.
>
> I took a look through the T20 board's schematics and seems it doesn't
> use the Blink clock for the WiFi, instead it uses 32k source directly
> from PMU. While T30 board schematics tells that  32k comes out from the
> Tegra chip.
>
> BTW, I'm curious what's the reason for having Blink clock always-ON on
> T20/30, any insights? Looks like it's just some relic from old clk
> driver and it should be safe to drop the always-ON.

T30 cardhu uses 32K from Tegra to WIFI but its only needed to be on 
during WIFI power up sequence and not required to be on during boot.

I had it enabled as existing clock driver enables it default and dont 
want to break things if it was left ON intentionally.

Peter/Thierry, Any reason 32K from Blink is enabled to be ON during 
clock init for T20/T30 in clock-tegra-pmc driver?

Based on the design T30 uses this for WIFI and WIFI driver should be 
handling this clock enable/disable during power up/down sequence,

so we don't have to enable it default during boot right?

On 11/28/19 5:25 AM, Dmitry Osipenko wrote:
> 28.11.2019 01:57, Sowjanya Komatineni пишет:
>> On 11/27/19 7:14 AM, Dmitry Osipenko wrote:
>>> 27.11.2019 07:59, Sowjanya Komatineni пишет:
>>>> Tegra210 and prior Tegra PMC has clk_out_1, clk_out_2, clk_out_3 with
>>>> mux and gate for each of these clocks.
>>>>
>>>> Currently these PMC clocks are registered by Tegra clock driver using
>>>> clk_register_mux and clk_register_gate by passing PMC base address
>>>> and register offsets and PMC programming for these clocks happens
>>>> through direct PMC access by the clock driver.
>>>>
>>>> With this, when PMC is in secure mode any direct PMC access from the
>>>> non-secure world does not go through and these clocks will not be
>>>> functional.
>>>>
>>>> This patch adds these clocks registration with PMC as a clock provider
>>>> for these clocks. clk_ops callback implementations for these clocks
>>>> uses tegra_pmc_readl and tegra_pmc_writel which supports PMC programming
>>>> in secure mode and non-secure mode.
>>>>
>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>> ---
>>>>    drivers/soc/tegra/pmc.c | 330
>>>> ++++++++++++++++++++++++++++++++++++++++++++++++
>>>>    1 file changed, 330 insertions(+)
>>>>
>>>> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
>>>> index ea0e11a09c12..a353f6d0a832 100644
>>>> --- a/drivers/soc/tegra/pmc.c
>>>> +++ b/drivers/soc/tegra/pmc.c
>>>> @@ -13,6 +13,9 @@
>>>>      #include <linux/arm-smccc.h>
>>>>    #include <linux/clk.h>
>>>> +#include <linux/clk-provider.h>
>>>> +#include <linux/clkdev.h>
>>>> +#include <linux/clk/clk-conf.h>
>>>>    #include <linux/clk/tegra.h>
>>>>    #include <linux/debugfs.h>
>>>>    #include <linux/delay.h>
>>>> @@ -48,6 +51,7 @@
>>>>    #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
>>>>    #include <dt-bindings/gpio/tegra186-gpio.h>
>>>>    #include <dt-bindings/gpio/tegra194-gpio.h>
>>>> +#include <dt-bindings/soc/tegra-pmc.h>
>>>>      #define PMC_CNTRL            0x0
>>>>    #define  PMC_CNTRL_INTR_POLARITY    BIT(17) /* inverts INTR
>>>> polarity */
>>>> @@ -100,6 +104,7 @@
>>>>    #define PMC_WAKE2_STATUS        0x168
>>>>    #define PMC_SW_WAKE2_STATUS        0x16c
>>>>    +#define PMC_CLK_OUT_CNTRL        0x1a8
>>>>    #define PMC_SENSOR_CTRL            0x1b0
>>>>    #define  PMC_SENSOR_CTRL_SCRATCH_WRITE    BIT(2)
>>>>    #define  PMC_SENSOR_CTRL_ENABLE_RST    BIT(1)
>>>> @@ -155,6 +160,91 @@
>>>>    #define  TEGRA_SMC_PMC_READ    0xaa
>>>>    #define  TEGRA_SMC_PMC_WRITE    0xbb
>>>>    +struct pmc_clk_mux {
>>>> +    struct clk_hw    hw;
>>>> +    unsigned long    offs;
>>>> +    u32        mask;
>>>> +    u32        shift;
>>>> +};
>>>> +
>>>> +#define to_pmc_clk_mux(_hw) container_of(_hw, struct pmc_clk_mux, hw)
>>>> +
>>>> +struct pmc_clk_gate {
>>>> +    struct clk_hw    hw;
>>>> +    unsigned long    offs;
>>>> +    u32        shift;
>>>> +};
>>>> +
>>>> +#define to_pmc_clk_gate(_hw) container_of(_hw, struct pmc_clk_gate, hw)
>>>> +
>>>> +struct pmc_clk_init_data {
>>>> +    char *mux_name;
>>>> +    char *gate_name;
>>>> +    const char **parents;
>>>> +    int num_parents;
>>>> +    int mux_id;
>>>> +    int gate_id;
>>>> +    char *dev_name;
>>>> +    u8 mux_shift;
>>>> +    u8 gate_shift;
>>>> +    u8 init_parent_index;
>>>> +    int init_state;
>>>> +};
>>>> +
>>>> +static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2",
>>>> +    "clk_m_div4", "extern1",
>>>> +};
>>>> +
>>>> +static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2",
>>>> +    "clk_m_div4", "extern2",
>>>> +};
>>>> +
>>>> +static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2",
>>>> +    "clk_m_div4", "extern3",
>>>> +};
>>>> +
>>>> +static struct pmc_clk_init_data tegra_pmc_clks_data[] = {
>>>> +    {
>>>> +        .mux_name = "clk_out_1_mux",
>>>> +        .gate_name = "clk_out_1",
>>>> +        .parents = clk_out1_parents,
>>>> +        .num_parents = ARRAY_SIZE(clk_out1_parents),
>>>> +        .mux_id = TEGRA_PMC_CLK_OUT_1_MUX,
>>>> +        .gate_id = TEGRA_PMC_CLK_OUT_1,
>>>> +        .dev_name = "extern1",
>>>> +        .mux_shift = 6,
>>>> +        .gate_shift = 2,
>>>> +        .init_parent_index = 3,
>>>> +        .init_state = 1,
>>>> +    },
>>>> +    {
>>>> +        .mux_name = "clk_out_2_mux",
>>>> +        .gate_name = "clk_out_2",
>>>> +        .parents = clk_out2_parents,
>>>> +        .num_parents = ARRAY_SIZE(clk_out2_parents),
>>>> +        .mux_id = TEGRA_PMC_CLK_OUT_2_MUX,
>>>> +        .gate_id = TEGRA_PMC_CLK_OUT_2,
>>>> +        .dev_name = "extern2",
>>>> +        .mux_shift = 14,
>>>> +        .gate_shift = 10,
>>>> +        .init_parent_index = 0,
>>>> +        .init_state = 0,
>>>> +    },
>>>> +    {
>>>> +        .mux_name = "clk_out_3_mux",
>>>> +        .gate_name = "clk_out_3",
>>>> +        .parents = clk_out3_parents,
>>>> +        .num_parents = ARRAY_SIZE(clk_out3_parents),
>>>> +        .mux_id = TEGRA_PMC_CLK_OUT_3_MUX,
>>>> +        .gate_id = TEGRA_PMC_CLK_OUT_3,
>>>> +        .dev_name = "extern3",
>>>> +        .mux_shift = 22,
>>>> +        .gate_shift = 18,
>>>> +        .init_parent_index = 0,
>>>> +        .init_state = 0,
>>>> +    },
>>>> +};
>>>> +
>>>>    struct tegra_powergate {
>>>>        struct generic_pm_domain genpd;
>>>>        struct tegra_pmc *pmc;
>>>> @@ -254,6 +344,9 @@ struct tegra_pmc_soc {
>>>>         */
>>>>        const struct tegra_wake_event *wake_events;
>>>>        unsigned int num_wake_events;
>>>> +
>>>> +    struct pmc_clk_init_data *pmc_clks_data;
>>>> +    unsigned int num_pmc_clks;
>>>>    };
>>>>      static const char * const tegra186_reset_sources[] = {
>>>> @@ -2163,6 +2256,228 @@ static int tegra_pmc_clk_notify_cb(struct
>>>> notifier_block *nb,
>>>>        return NOTIFY_OK;
>>>>    }
>>>>    +static void pmc_clk_fence_udelay(u32 offset)
>>>> +{
>>>> +    tegra_pmc_readl(pmc, offset);
>>>> +    /* pmc clk propagation delay 2 us */
>>>> +    udelay(2);
>>>> +}
>>>> +
>>>> +static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
>>>> +{
>>>> +    struct pmc_clk_mux *mux = to_pmc_clk_mux(hw);
>>>> +    int num_parents = clk_hw_get_num_parents(hw);
>>>> +    u32 val;
>>>> +
>>>> +    val = tegra_pmc_readl(pmc, mux->offs) >> mux->shift;
>>>> +    val &= mux->mask;
>>>> +
>>>> +    if (val >= num_parents)
>>>> +        return -EINVAL;
>>>> +
>>>> +    return val;
>>>> +}
>>>> +
>>>> +static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
>>>> +{
>>>> +    struct pmc_clk_mux *mux = to_pmc_clk_mux(hw);
>>>> +    u32 val;
>>>> +
>>>> +    val = tegra_pmc_readl(pmc, mux->offs);
>>>> +    val &= ~(mux->mask << mux->shift);
>>>> +    val |= index << mux->shift;
>>>> +    tegra_pmc_writel(pmc, val, mux->offs);
>>>> +    pmc_clk_fence_udelay(mux->offs);
>>>> +
>>>> +    return 0;
>>>> +}
>>>> +
>>>> +static const struct clk_ops pmc_clk_mux_ops = {
>>>> +    .get_parent = pmc_clk_mux_get_parent,
>>>> +    .set_parent = pmc_clk_mux_set_parent,
>>>> +    .determine_rate = __clk_mux_determine_rate,
>>>> +};
>>>> +
>>>> +static struct clk *
>>>> +tegra_pmc_clk_mux_register(const char *name, const char * const
>>>> *parent_names,
>>>> +               int num_parents, unsigned long flags,
>>>> +               unsigned long offset, u32 shift, u32 mask)
>>>> +{
>>>> +    struct clk_init_data init;
>>>> +    struct pmc_clk_mux *mux;
>>>> +
>>>> +    mux = kzalloc(sizeof(*mux), GFP_KERNEL);
>>>> +    if (!mux)
>>>> +        return ERR_PTR(-ENOMEM);
>>>> +
>>>> +    init.name = name;
>>>> +    init.ops = &pmc_clk_mux_ops;
>>>> +    init.parent_names = parent_names;
>>>> +    init.num_parents = num_parents;
>>>> +    init.flags = flags;
>>>> +
>>>> +    mux->hw.init = &init;
>>>> +    mux->offs = offset;
>>>> +    mux->mask = mask;
>>>> +    mux->shift = shift;
>>>> +
>>>> +    return clk_register(NULL, &mux->hw);
>>>> +}
>>>> +
>>>> +static int pmc_clk_is_enabled(struct clk_hw *hw)
>>>> +{
>>>> +    struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
>>>> +
>>>> +    return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0;
>>>> +}
>>>> +
>>>> +static void pmc_clk_set_state(struct clk_hw *hw, int state)
>>>> +{
>>>> +    struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
>>>> +    u32 val;
>>>> +
>>>> +    val = tegra_pmc_readl(pmc, gate->offs);
>>>> +    val = state ? (val | BIT(gate->shift)) : (val & ~BIT(gate->shift));
>>>> +    tegra_pmc_writel(pmc, val, gate->offs);
>>>> +    pmc_clk_fence_udelay(gate->offs);
>>>> +}
>>>> +
>>>> +static int pmc_clk_enable(struct clk_hw *hw)
>>>> +{
>>>> +    pmc_clk_set_state(hw, 1);
>>>> +
>>>> +    return 0;
>>>> +}
>>>> +
>>>> +static void pmc_clk_disable(struct clk_hw *hw)
>>>> +{
>>>> +    pmc_clk_set_state(hw, 0);
>>>> +}
>>>> +
>>>> +static const struct clk_ops pmc_clk_gate_ops = {
>>>> +    .is_enabled = pmc_clk_is_enabled,
>>>> +    .enable = pmc_clk_enable,
>>>> +    .disable = pmc_clk_disable,
>>>> +};
>>>> +
>>>> +static struct clk *
>>>> +tegra_pmc_clk_gate_register(const char *name, const char *parent_name,
>>>> +                unsigned long flags, unsigned long offset,
>>>> +                u32 shift)
>>>> +{
>>>> +    struct clk_init_data init;
>>>> +    struct pmc_clk_gate *gate;
>>>> +
>>>> +    gate = kzalloc(sizeof(*gate), GFP_KERNEL);
>>>> +    if (!gate)
>>>> +        return ERR_PTR(-ENOMEM);
>>>> +
>>>> +    init.name = name;
>>>> +    init.ops = &pmc_clk_gate_ops;
>>>> +    init.parent_names = &parent_name;
>>>> +    init.num_parents = 1;
>>>> +    init.flags = flags;
>>>> +
>>>> +    gate->hw.init = &init;
>>>> +    gate->offs = offset;
>>>> +    gate->shift = shift;
>>>> +
>>>> +    return clk_register(NULL, &gate->hw);
>>>> +}
>>>> +
>>>> +static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
>>>> +                     struct device_node *np)
>>>> +{
>>>> +    struct clk *clkmux, *clk, *parent;
>>>> +    struct clk_onecell_data *clk_data;
>>>> +    unsigned int num_clks;
>>>> +    int i, ret;
>>>> +
>>>> +    /* each pmc clock output has a mux and a gate */
>>>> +    num_clks = pmc->soc->num_pmc_clks * 2;
>>>> +
>>>> +    if (!num_clks)
>>>> +        return;
>>>> +
>>>> +    clk_data = kmalloc(sizeof(*clk_data), GFP_KERNEL);
>>>> +    if (!clk_data)
>>>> +        return;
>>>> +
>>>> +    clk_data->clks = kcalloc(TEGRA_PMC_CLK_MAX,
>>>> sizeof(*clk_data->clks),
>>>> +                 GFP_KERNEL);
>>>> +    if (!clk_data->clks)
>>>> +        goto free_clkdata;
>>>> +
>>>> +    clk_data->clk_num = num_clks;
>>>> +
>>>> +    for (i = 0; i < pmc->soc->num_pmc_clks; i++) {
>>>> +        struct pmc_clk_init_data *data;
>>>> +
>>>> +        data = pmc->soc->pmc_clks_data + i;
>>>> +
>>>> +        clkmux = tegra_pmc_clk_mux_register(data->mux_name,
>>>> +                            data->parents,
>>>> +                            data->num_parents,
>>>> +                            CLK_SET_RATE_NO_REPARENT |
>>>> +                            CLK_SET_RATE_PARENT,
>>>> +                            PMC_CLK_OUT_CNTRL,
>>>> +                            data->mux_shift, 3);
>>>> +        if (IS_ERR(clkmux))
>>>> +            goto free_clks;
>>>> +
>>>> +        clk_data->clks[data->mux_id] = clkmux;
>>>> +
>>>> +        clk = tegra_pmc_clk_gate_register(data->gate_name,
>>>> +                          data->mux_name,
>>>> +                          CLK_SET_RATE_PARENT,
>>>> +                          PMC_CLK_OUT_CNTRL,
>>>> +                          data->gate_shift);
>>>> +        if (IS_ERR(clk))
>>>> +            goto free_clks;
>>>> +
>>>> +        clk_data->clks[data->gate_id] = clk;
>>>> +
>>>> +        ret = clk_set_parent(clk, clkmux);
>>>> +        if (ret < 0) {
>>>> +            pr_err("failed to set parent of %s to %s\n",
>>>> +                   __func__, __clk_get_name(clk),
>>>> +                   __clk_get_name(clkmux));
>>>> +        }
>>>> +
>>>> +        clk_register_clkdev(clk, data->dev_name, data->gate_name);
>>>> +
>>>> +        /* configure initial clock parent and state */
>>>> +        parent = clk_get_sys(data->gate_name,
>>>> +                     data->parents[data->init_parent_index]);
>>>> +        if (!IS_ERR(parent)) {
>>>> +            ret = clk_set_parent(clkmux, parent);
>>>> +            if (ret < 0) {
>>>> +                pr_err("failed to set parent of %s to %s\n",
>>>> +                       __func__, __clk_get_name(clkmux),
>>>> +                       __clk_get_name(parent));
>>>> +                WARN_ON(1);
>>>> +            }
>>>> +        }
>>>> +
>>>> +        if (data->init_state) {
>>>> +            if (clk_prepare_enable(clk)) {
>>>> +                pr_err("failed to enable %s\n", __func__,
>>>> +                       __clk_get_name(clk));
>>>> +                WARN_ON(1);
> Alternatively you could write it like this:
>
> 	err = clk_prepare_enable(clk);
>
> 	WARN_ON(err, "failed to enable %s: %d\n",
> 		__clk_get_name(clk), err);
>
>>> Should be a bit better to move the WARN_ON to the end of errors handling
>>> in order to catch all possible errors:
>>>
>>> @@ -2510,6 +2510,7 @@ static void tegra_pmc_clock_register(struct
>>> tegra_pmc *pmc,
>>>           return;
>>>
>>>    free_clks:
>>> +       WARN_ON(1);
>>>           kfree(clk_data->clks);
>>>    free_clkdata:
>>>           kfree(clk_data);
>> Reason I had WARN_ON right during clk_set_parent failure is to have the
>> loop continue for subsequence pmc clocks registration instead of
>> terminating all pmc clocks registration.
> Ah, okay. Nevertheless this WARN_ON in the end shouldn't be the least (IMO).

Hi Dmitry, Just want to be clear on the above comment. Are you 
suggesting to add additional WARN_ON at the end?

Thought WARN_ON right during corresponding clock failure with warn 
message showing clock names will be clear and also other clocks still 
should be registered.

To add additional WARN_ON at the end need to track status of each clock 
and use that to as warn condition.

02.12.2019 23:09, Sowjanya Komatineni пишет:
> 
> On 11/28/19 5:25 AM, Dmitry Osipenko wrote:
>> 28.11.2019 01:57, Sowjanya Komatineni пишет:
>>> On 11/27/19 7:14 AM, Dmitry Osipenko wrote:
>>>> 27.11.2019 07:59, Sowjanya Komatineni пишет:
>>>>> Tegra210 and prior Tegra PMC has clk_out_1, clk_out_2, clk_out_3 with
>>>>> mux and gate for each of these clocks.
>>>>>
>>>>> Currently these PMC clocks are registered by Tegra clock driver using
>>>>> clk_register_mux and clk_register_gate by passing PMC base address
>>>>> and register offsets and PMC programming for these clocks happens
>>>>> through direct PMC access by the clock driver.
>>>>>
>>>>> With this, when PMC is in secure mode any direct PMC access from the
>>>>> non-secure world does not go through and these clocks will not be
>>>>> functional.
>>>>>
>>>>> This patch adds these clocks registration with PMC as a clock provider
>>>>> for these clocks. clk_ops callback implementations for these clocks
>>>>> uses tegra_pmc_readl and tegra_pmc_writel which supports PMC
>>>>> programming
>>>>> in secure mode and non-secure mode.
>>>>>
>>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>>> ---
>>>>>    drivers/soc/tegra/pmc.c | 330
>>>>> ++++++++++++++++++++++++++++++++++++++++++++++++
>>>>>    1 file changed, 330 insertions(+)
>>>>>
>>>>> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
>>>>> index ea0e11a09c12..a353f6d0a832 100644
>>>>> --- a/drivers/soc/tegra/pmc.c
>>>>> +++ b/drivers/soc/tegra/pmc.c
>>>>> @@ -13,6 +13,9 @@
>>>>>      #include <linux/arm-smccc.h>
>>>>>    #include <linux/clk.h>
>>>>> +#include <linux/clk-provider.h>
>>>>> +#include <linux/clkdev.h>
>>>>> +#include <linux/clk/clk-conf.h>
>>>>>    #include <linux/clk/tegra.h>
>>>>>    #include <linux/debugfs.h>
>>>>>    #include <linux/delay.h>
>>>>> @@ -48,6 +51,7 @@
>>>>>    #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
>>>>>    #include <dt-bindings/gpio/tegra186-gpio.h>
>>>>>    #include <dt-bindings/gpio/tegra194-gpio.h>
>>>>> +#include <dt-bindings/soc/tegra-pmc.h>
>>>>>      #define PMC_CNTRL            0x0
>>>>>    #define  PMC_CNTRL_INTR_POLARITY    BIT(17) /* inverts INTR
>>>>> polarity */
>>>>> @@ -100,6 +104,7 @@
>>>>>    #define PMC_WAKE2_STATUS        0x168
>>>>>    #define PMC_SW_WAKE2_STATUS        0x16c
>>>>>    +#define PMC_CLK_OUT_CNTRL        0x1a8
>>>>>    #define PMC_SENSOR_CTRL            0x1b0
>>>>>    #define  PMC_SENSOR_CTRL_SCRATCH_WRITE    BIT(2)
>>>>>    #define  PMC_SENSOR_CTRL_ENABLE_RST    BIT(1)
>>>>> @@ -155,6 +160,91 @@
>>>>>    #define  TEGRA_SMC_PMC_READ    0xaa
>>>>>    #define  TEGRA_SMC_PMC_WRITE    0xbb
>>>>>    +struct pmc_clk_mux {
>>>>> +    struct clk_hw    hw;
>>>>> +    unsigned long    offs;
>>>>> +    u32        mask;
>>>>> +    u32        shift;
>>>>> +};
>>>>> +
>>>>> +#define to_pmc_clk_mux(_hw) container_of(_hw, struct pmc_clk_mux, hw)
>>>>> +
>>>>> +struct pmc_clk_gate {
>>>>> +    struct clk_hw    hw;
>>>>> +    unsigned long    offs;
>>>>> +    u32        shift;
>>>>> +};
>>>>> +
>>>>> +#define to_pmc_clk_gate(_hw) container_of(_hw, struct
>>>>> pmc_clk_gate, hw)
>>>>> +
>>>>> +struct pmc_clk_init_data {
>>>>> +    char *mux_name;
>>>>> +    char *gate_name;
>>>>> +    const char **parents;
>>>>> +    int num_parents;
>>>>> +    int mux_id;
>>>>> +    int gate_id;
>>>>> +    char *dev_name;
>>>>> +    u8 mux_shift;
>>>>> +    u8 gate_shift;
>>>>> +    u8 init_parent_index;
>>>>> +    int init_state;
>>>>> +};
>>>>> +
>>>>> +static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2",
>>>>> +    "clk_m_div4", "extern1",
>>>>> +};
>>>>> +
>>>>> +static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2",
>>>>> +    "clk_m_div4", "extern2",
>>>>> +};
>>>>> +
>>>>> +static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2",
>>>>> +    "clk_m_div4", "extern3",
>>>>> +};
>>>>> +
>>>>> +static struct pmc_clk_init_data tegra_pmc_clks_data[] = {
>>>>> +    {
>>>>> +        .mux_name = "clk_out_1_mux",
>>>>> +        .gate_name = "clk_out_1",
>>>>> +        .parents = clk_out1_parents,
>>>>> +        .num_parents = ARRAY_SIZE(clk_out1_parents),
>>>>> +        .mux_id = TEGRA_PMC_CLK_OUT_1_MUX,
>>>>> +        .gate_id = TEGRA_PMC_CLK_OUT_1,
>>>>> +        .dev_name = "extern1",
>>>>> +        .mux_shift = 6,
>>>>> +        .gate_shift = 2,
>>>>> +        .init_parent_index = 3,
>>>>> +        .init_state = 1,
>>>>> +    },
>>>>> +    {
>>>>> +        .mux_name = "clk_out_2_mux",
>>>>> +        .gate_name = "clk_out_2",
>>>>> +        .parents = clk_out2_parents,
>>>>> +        .num_parents = ARRAY_SIZE(clk_out2_parents),
>>>>> +        .mux_id = TEGRA_PMC_CLK_OUT_2_MUX,
>>>>> +        .gate_id = TEGRA_PMC_CLK_OUT_2,
>>>>> +        .dev_name = "extern2",
>>>>> +        .mux_shift = 14,
>>>>> +        .gate_shift = 10,
>>>>> +        .init_parent_index = 0,
>>>>> +        .init_state = 0,
>>>>> +    },
>>>>> +    {
>>>>> +        .mux_name = "clk_out_3_mux",
>>>>> +        .gate_name = "clk_out_3",
>>>>> +        .parents = clk_out3_parents,
>>>>> +        .num_parents = ARRAY_SIZE(clk_out3_parents),
>>>>> +        .mux_id = TEGRA_PMC_CLK_OUT_3_MUX,
>>>>> +        .gate_id = TEGRA_PMC_CLK_OUT_3,
>>>>> +        .dev_name = "extern3",
>>>>> +        .mux_shift = 22,
>>>>> +        .gate_shift = 18,
>>>>> +        .init_parent_index = 0,
>>>>> +        .init_state = 0,
>>>>> +    },
>>>>> +};
>>>>> +
>>>>>    struct tegra_powergate {
>>>>>        struct generic_pm_domain genpd;
>>>>>        struct tegra_pmc *pmc;
>>>>> @@ -254,6 +344,9 @@ struct tegra_pmc_soc {
>>>>>         */
>>>>>        const struct tegra_wake_event *wake_events;
>>>>>        unsigned int num_wake_events;
>>>>> +
>>>>> +    struct pmc_clk_init_data *pmc_clks_data;
>>>>> +    unsigned int num_pmc_clks;
>>>>>    };
>>>>>      static const char * const tegra186_reset_sources[] = {
>>>>> @@ -2163,6 +2256,228 @@ static int tegra_pmc_clk_notify_cb(struct
>>>>> notifier_block *nb,
>>>>>        return NOTIFY_OK;
>>>>>    }
>>>>>    +static void pmc_clk_fence_udelay(u32 offset)
>>>>> +{
>>>>> +    tegra_pmc_readl(pmc, offset);
>>>>> +    /* pmc clk propagation delay 2 us */
>>>>> +    udelay(2);
>>>>> +}
>>>>> +
>>>>> +static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
>>>>> +{
>>>>> +    struct pmc_clk_mux *mux = to_pmc_clk_mux(hw);
>>>>> +    int num_parents = clk_hw_get_num_parents(hw);
>>>>> +    u32 val;
>>>>> +
>>>>> +    val = tegra_pmc_readl(pmc, mux->offs) >> mux->shift;
>>>>> +    val &= mux->mask;
>>>>> +
>>>>> +    if (val >= num_parents)
>>>>> +        return -EINVAL;
>>>>> +
>>>>> +    return val;
>>>>> +}
>>>>> +
>>>>> +static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
>>>>> +{
>>>>> +    struct pmc_clk_mux *mux = to_pmc_clk_mux(hw);
>>>>> +    u32 val;
>>>>> +
>>>>> +    val = tegra_pmc_readl(pmc, mux->offs);
>>>>> +    val &= ~(mux->mask << mux->shift);
>>>>> +    val |= index << mux->shift;
>>>>> +    tegra_pmc_writel(pmc, val, mux->offs);
>>>>> +    pmc_clk_fence_udelay(mux->offs);
>>>>> +
>>>>> +    return 0;
>>>>> +}
>>>>> +
>>>>> +static const struct clk_ops pmc_clk_mux_ops = {
>>>>> +    .get_parent = pmc_clk_mux_get_parent,
>>>>> +    .set_parent = pmc_clk_mux_set_parent,
>>>>> +    .determine_rate = __clk_mux_determine_rate,
>>>>> +};
>>>>> +
>>>>> +static struct clk *
>>>>> +tegra_pmc_clk_mux_register(const char *name, const char * const
>>>>> *parent_names,
>>>>> +               int num_parents, unsigned long flags,
>>>>> +               unsigned long offset, u32 shift, u32 mask)
>>>>> +{
>>>>> +    struct clk_init_data init;
>>>>> +    struct pmc_clk_mux *mux;
>>>>> +
>>>>> +    mux = kzalloc(sizeof(*mux), GFP_KERNEL);
>>>>> +    if (!mux)
>>>>> +        return ERR_PTR(-ENOMEM);
>>>>> +
>>>>> +    init.name = name;
>>>>> +    init.ops = &pmc_clk_mux_ops;
>>>>> +    init.parent_names = parent_names;
>>>>> +    init.num_parents = num_parents;
>>>>> +    init.flags = flags;
>>>>> +
>>>>> +    mux->hw.init = &init;
>>>>> +    mux->offs = offset;
>>>>> +    mux->mask = mask;
>>>>> +    mux->shift = shift;
>>>>> +
>>>>> +    return clk_register(NULL, &mux->hw);
>>>>> +}
>>>>> +
>>>>> +static int pmc_clk_is_enabled(struct clk_hw *hw)
>>>>> +{
>>>>> +    struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
>>>>> +
>>>>> +    return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1
>>>>> : 0;
>>>>> +}
>>>>> +
>>>>> +static void pmc_clk_set_state(struct clk_hw *hw, int state)
>>>>> +{
>>>>> +    struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
>>>>> +    u32 val;
>>>>> +
>>>>> +    val = tegra_pmc_readl(pmc, gate->offs);
>>>>> +    val = state ? (val | BIT(gate->shift)) : (val &
>>>>> ~BIT(gate->shift));
>>>>> +    tegra_pmc_writel(pmc, val, gate->offs);
>>>>> +    pmc_clk_fence_udelay(gate->offs);
>>>>> +}
>>>>> +
>>>>> +static int pmc_clk_enable(struct clk_hw *hw)
>>>>> +{
>>>>> +    pmc_clk_set_state(hw, 1);
>>>>> +
>>>>> +    return 0;
>>>>> +}
>>>>> +
>>>>> +static void pmc_clk_disable(struct clk_hw *hw)
>>>>> +{
>>>>> +    pmc_clk_set_state(hw, 0);
>>>>> +}
>>>>> +
>>>>> +static const struct clk_ops pmc_clk_gate_ops = {
>>>>> +    .is_enabled = pmc_clk_is_enabled,
>>>>> +    .enable = pmc_clk_enable,
>>>>> +    .disable = pmc_clk_disable,
>>>>> +};
>>>>> +
>>>>> +static struct clk *
>>>>> +tegra_pmc_clk_gate_register(const char *name, const char
>>>>> *parent_name,
>>>>> +                unsigned long flags, unsigned long offset,
>>>>> +                u32 shift)
>>>>> +{
>>>>> +    struct clk_init_data init;
>>>>> +    struct pmc_clk_gate *gate;
>>>>> +
>>>>> +    gate = kzalloc(sizeof(*gate), GFP_KERNEL);
>>>>> +    if (!gate)
>>>>> +        return ERR_PTR(-ENOMEM);
>>>>> +
>>>>> +    init.name = name;
>>>>> +    init.ops = &pmc_clk_gate_ops;
>>>>> +    init.parent_names = &parent_name;
>>>>> +    init.num_parents = 1;
>>>>> +    init.flags = flags;
>>>>> +
>>>>> +    gate->hw.init = &init;
>>>>> +    gate->offs = offset;
>>>>> +    gate->shift = shift;
>>>>> +
>>>>> +    return clk_register(NULL, &gate->hw);
>>>>> +}
>>>>> +
>>>>> +static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
>>>>> +                     struct device_node *np)
>>>>> +{
>>>>> +    struct clk *clkmux, *clk, *parent;
>>>>> +    struct clk_onecell_data *clk_data;
>>>>> +    unsigned int num_clks;
>>>>> +    int i, ret;
>>>>> +
>>>>> +    /* each pmc clock output has a mux and a gate */
>>>>> +    num_clks = pmc->soc->num_pmc_clks * 2;
>>>>> +
>>>>> +    if (!num_clks)
>>>>> +        return;
>>>>> +
>>>>> +    clk_data = kmalloc(sizeof(*clk_data), GFP_KERNEL);
>>>>> +    if (!clk_data)
>>>>> +        return;
>>>>> +
>>>>> +    clk_data->clks = kcalloc(TEGRA_PMC_CLK_MAX,
>>>>> sizeof(*clk_data->clks),
>>>>> +                 GFP_KERNEL);
>>>>> +    if (!clk_data->clks)
>>>>> +        goto free_clkdata;
>>>>> +
>>>>> +    clk_data->clk_num = num_clks;
>>>>> +
>>>>> +    for (i = 0; i < pmc->soc->num_pmc_clks; i++) {
>>>>> +        struct pmc_clk_init_data *data;
>>>>> +
>>>>> +        data = pmc->soc->pmc_clks_data + i;
>>>>> +
>>>>> +        clkmux = tegra_pmc_clk_mux_register(data->mux_name,
>>>>> +                            data->parents,
>>>>> +                            data->num_parents,
>>>>> +                            CLK_SET_RATE_NO_REPARENT |
>>>>> +                            CLK_SET_RATE_PARENT,
>>>>> +                            PMC_CLK_OUT_CNTRL,
>>>>> +                            data->mux_shift, 3);
>>>>> +        if (IS_ERR(clkmux))
>>>>> +            goto free_clks;
>>>>> +
>>>>> +        clk_data->clks[data->mux_id] = clkmux;
>>>>> +
>>>>> +        clk = tegra_pmc_clk_gate_register(data->gate_name,
>>>>> +                          data->mux_name,
>>>>> +                          CLK_SET_RATE_PARENT,
>>>>> +                          PMC_CLK_OUT_CNTRL,
>>>>> +                          data->gate_shift);
>>>>> +        if (IS_ERR(clk))
>>>>> +            goto free_clks;
>>>>> +
>>>>> +        clk_data->clks[data->gate_id] = clk;
>>>>> +
>>>>> +        ret = clk_set_parent(clk, clkmux);
>>>>> +        if (ret < 0) {
>>>>> +            pr_err("failed to set parent of %s to %s\n",
>>>>> +                   __func__, __clk_get_name(clk),
>>>>> +                   __clk_get_name(clkmux));
>>>>> +        }
>>>>> +
>>>>> +        clk_register_clkdev(clk, data->dev_name, data->gate_name);
>>>>> +
>>>>> +        /* configure initial clock parent and state */
>>>>> +        parent = clk_get_sys(data->gate_name,
>>>>> +                     data->parents[data->init_parent_index]);

Couldn't the default parent be defined using "assigned clock" in a
device-tree? Please see "Assigned clock parents and rates" in the doc.

https://www.kernel.org/doc/Documentation/devicetree/bindings/clock/clock-bindings.txt

Then you could simply use of_clk_set_defaults(pmc->dev->of_node, true).

>>>>> +        if (!IS_ERR(parent)) {
>>>>> +            ret = clk_set_parent(clkmux, parent);
>>>>> +            if (ret < 0) {
>>>>> +                pr_err("failed to set parent of %s to %s\n",
>>>>> +                       __func__, __clk_get_name(clkmux),
>>>>> +                       __clk_get_name(parent));
>>>>> +                WARN_ON(1);
>>>>> +            }
>>>>> +        }
>>>>> +
>>>>> +        if (data->init_state) {
>>>>> +            if (clk_prepare_enable(clk)) {
>>>>> +                pr_err("failed to enable %s\n", __func__,
>>>>> +                       __clk_get_name(clk));
>>>>> +                WARN_ON(1);
>> Alternatively you could write it like this:
>>
>>     err = clk_prepare_enable(clk);
>>
>>     WARN_ON(err, "failed to enable %s: %d\n",
>>         __clk_get_name(clk), err);
>>
>>>> Should be a bit better to move the WARN_ON to the end of errors
>>>> handling
>>>> in order to catch all possible errors:
>>>>
>>>> @@ -2510,6 +2510,7 @@ static void tegra_pmc_clock_register(struct
>>>> tegra_pmc *pmc,
>>>>           return;
>>>>
>>>>    free_clks:
>>>> +       WARN_ON(1);
>>>>           kfree(clk_data->clks);
>>>>    free_clkdata:
>>>>           kfree(clk_data);
>>> Reason I had WARN_ON right during clk_set_parent failure is to have the
>>> loop continue for subsequence pmc clocks registration instead of
>>> terminating all pmc clocks registration.
>> Ah, okay. Nevertheless this WARN_ON in the end shouldn't be the least
>> (IMO).
> Hi Dmitry, Just want to be clear on the above comment. Are you
> suggesting to add additional WARN_ON at the end?

Yes, it was my suggestion.

> Thought WARN_ON right during corresponding clock failure with warn
> message showing clock names will be clear and also other clocks still
> should be registered.
> 
> To add additional WARN_ON at the end need to track status of each clock
> and use that to as warn condition.

You could add a warning/error message to every point of failure.

Primarily, it is important not to miss a error. Secondarily, it is
important to make diagnostic message meaningful.

Realistically, I doubt that this chunk of code will ever fail once it is
known to work well. So it will be nice to have a more detailed
diagnostics (just in a case), but it shouldn't be a must.

On 12/2/19 1:50 PM, Dmitry Osipenko wrote:
> 02.12.2019 23:09, Sowjanya Komatineni пишет:
>> On 11/28/19 5:25 AM, Dmitry Osipenko wrote:
>>> 28.11.2019 01:57, Sowjanya Komatineni пишет:
>>>> On 11/27/19 7:14 AM, Dmitry Osipenko wrote:
>>>>> 27.11.2019 07:59, Sowjanya Komatineni пишет:
>>>>>> Tegra210 and prior Tegra PMC has clk_out_1, clk_out_2, clk_out_3 with
>>>>>> mux and gate for each of these clocks.
>>>>>>
>>>>>> Currently these PMC clocks are registered by Tegra clock driver using
>>>>>> clk_register_mux and clk_register_gate by passing PMC base address
>>>>>> and register offsets and PMC programming for these clocks happens
>>>>>> through direct PMC access by the clock driver.
>>>>>>
>>>>>> With this, when PMC is in secure mode any direct PMC access from the
>>>>>> non-secure world does not go through and these clocks will not be
>>>>>> functional.
>>>>>>
>>>>>> This patch adds these clocks registration with PMC as a clock provider
>>>>>> for these clocks. clk_ops callback implementations for these clocks
>>>>>> uses tegra_pmc_readl and tegra_pmc_writel which supports PMC
>>>>>> programming
>>>>>> in secure mode and non-secure mode.
>>>>>>
>>>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>>>> ---
>>>>>>     drivers/soc/tegra/pmc.c | 330
>>>>>> ++++++++++++++++++++++++++++++++++++++++++++++++
>>>>>>     1 file changed, 330 insertions(+)
>>>>>>
>>>>>> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
>>>>>> index ea0e11a09c12..a353f6d0a832 100644
>>>>>> --- a/drivers/soc/tegra/pmc.c
>>>>>> +++ b/drivers/soc/tegra/pmc.c
>>>>>> @@ -13,6 +13,9 @@
>>>>>>       #include <linux/arm-smccc.h>
>>>>>>     #include <linux/clk.h>
>>>>>> +#include <linux/clk-provider.h>
>>>>>> +#include <linux/clkdev.h>
>>>>>> +#include <linux/clk/clk-conf.h>
>>>>>>     #include <linux/clk/tegra.h>
>>>>>>     #include <linux/debugfs.h>
>>>>>>     #include <linux/delay.h>
>>>>>> @@ -48,6 +51,7 @@
>>>>>>     #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
>>>>>>     #include <dt-bindings/gpio/tegra186-gpio.h>
>>>>>>     #include <dt-bindings/gpio/tegra194-gpio.h>
>>>>>> +#include <dt-bindings/soc/tegra-pmc.h>
>>>>>>       #define PMC_CNTRL            0x0
>>>>>>     #define  PMC_CNTRL_INTR_POLARITY    BIT(17) /* inverts INTR
>>>>>> polarity */
>>>>>> @@ -100,6 +104,7 @@
>>>>>>     #define PMC_WAKE2_STATUS        0x168
>>>>>>     #define PMC_SW_WAKE2_STATUS        0x16c
>>>>>>     +#define PMC_CLK_OUT_CNTRL        0x1a8
>>>>>>     #define PMC_SENSOR_CTRL            0x1b0
>>>>>>     #define  PMC_SENSOR_CTRL_SCRATCH_WRITE    BIT(2)
>>>>>>     #define  PMC_SENSOR_CTRL_ENABLE_RST    BIT(1)
>>>>>> @@ -155,6 +160,91 @@
>>>>>>     #define  TEGRA_SMC_PMC_READ    0xaa
>>>>>>     #define  TEGRA_SMC_PMC_WRITE    0xbb
>>>>>>     +struct pmc_clk_mux {
>>>>>> +    struct clk_hw    hw;
>>>>>> +    unsigned long    offs;
>>>>>> +    u32        mask;
>>>>>> +    u32        shift;
>>>>>> +};
>>>>>> +
>>>>>> +#define to_pmc_clk_mux(_hw) container_of(_hw, struct pmc_clk_mux, hw)
>>>>>> +
>>>>>> +struct pmc_clk_gate {
>>>>>> +    struct clk_hw    hw;
>>>>>> +    unsigned long    offs;
>>>>>> +    u32        shift;
>>>>>> +};
>>>>>> +
>>>>>> +#define to_pmc_clk_gate(_hw) container_of(_hw, struct
>>>>>> pmc_clk_gate, hw)
>>>>>> +
>>>>>> +struct pmc_clk_init_data {
>>>>>> +    char *mux_name;
>>>>>> +    char *gate_name;
>>>>>> +    const char **parents;
>>>>>> +    int num_parents;
>>>>>> +    int mux_id;
>>>>>> +    int gate_id;
>>>>>> +    char *dev_name;
>>>>>> +    u8 mux_shift;
>>>>>> +    u8 gate_shift;
>>>>>> +    u8 init_parent_index;
>>>>>> +    int init_state;
>>>>>> +};
>>>>>> +
>>>>>> +static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2",
>>>>>> +    "clk_m_div4", "extern1",
>>>>>> +};
>>>>>> +
>>>>>> +static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2",
>>>>>> +    "clk_m_div4", "extern2",
>>>>>> +};
>>>>>> +
>>>>>> +static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2",
>>>>>> +    "clk_m_div4", "extern3",
>>>>>> +};
>>>>>> +
>>>>>> +static struct pmc_clk_init_data tegra_pmc_clks_data[] = {
>>>>>> +    {
>>>>>> +        .mux_name = "clk_out_1_mux",
>>>>>> +        .gate_name = "clk_out_1",
>>>>>> +        .parents = clk_out1_parents,
>>>>>> +        .num_parents = ARRAY_SIZE(clk_out1_parents),
>>>>>> +        .mux_id = TEGRA_PMC_CLK_OUT_1_MUX,
>>>>>> +        .gate_id = TEGRA_PMC_CLK_OUT_1,
>>>>>> +        .dev_name = "extern1",
>>>>>> +        .mux_shift = 6,
>>>>>> +        .gate_shift = 2,
>>>>>> +        .init_parent_index = 3,
>>>>>> +        .init_state = 1,
>>>>>> +    },
>>>>>> +    {
>>>>>> +        .mux_name = "clk_out_2_mux",
>>>>>> +        .gate_name = "clk_out_2",
>>>>>> +        .parents = clk_out2_parents,
>>>>>> +        .num_parents = ARRAY_SIZE(clk_out2_parents),
>>>>>> +        .mux_id = TEGRA_PMC_CLK_OUT_2_MUX,
>>>>>> +        .gate_id = TEGRA_PMC_CLK_OUT_2,
>>>>>> +        .dev_name = "extern2",
>>>>>> +        .mux_shift = 14,
>>>>>> +        .gate_shift = 10,
>>>>>> +        .init_parent_index = 0,
>>>>>> +        .init_state = 0,
>>>>>> +    },
>>>>>> +    {
>>>>>> +        .mux_name = "clk_out_3_mux",
>>>>>> +        .gate_name = "clk_out_3",
>>>>>> +        .parents = clk_out3_parents,
>>>>>> +        .num_parents = ARRAY_SIZE(clk_out3_parents),
>>>>>> +        .mux_id = TEGRA_PMC_CLK_OUT_3_MUX,
>>>>>> +        .gate_id = TEGRA_PMC_CLK_OUT_3,
>>>>>> +        .dev_name = "extern3",
>>>>>> +        .mux_shift = 22,
>>>>>> +        .gate_shift = 18,
>>>>>> +        .init_parent_index = 0,
>>>>>> +        .init_state = 0,
>>>>>> +    },
>>>>>> +};
>>>>>> +
>>>>>>     struct tegra_powergate {
>>>>>>         struct generic_pm_domain genpd;
>>>>>>         struct tegra_pmc *pmc;
>>>>>> @@ -254,6 +344,9 @@ struct tegra_pmc_soc {
>>>>>>          */
>>>>>>         const struct tegra_wake_event *wake_events;
>>>>>>         unsigned int num_wake_events;
>>>>>> +
>>>>>> +    struct pmc_clk_init_data *pmc_clks_data;
>>>>>> +    unsigned int num_pmc_clks;
>>>>>>     };
>>>>>>       static const char * const tegra186_reset_sources[] = {
>>>>>> @@ -2163,6 +2256,228 @@ static int tegra_pmc_clk_notify_cb(struct
>>>>>> notifier_block *nb,
>>>>>>         return NOTIFY_OK;
>>>>>>     }
>>>>>>     +static void pmc_clk_fence_udelay(u32 offset)
>>>>>> +{
>>>>>> +    tegra_pmc_readl(pmc, offset);
>>>>>> +    /* pmc clk propagation delay 2 us */
>>>>>> +    udelay(2);
>>>>>> +}
>>>>>> +
>>>>>> +static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
>>>>>> +{
>>>>>> +    struct pmc_clk_mux *mux = to_pmc_clk_mux(hw);
>>>>>> +    int num_parents = clk_hw_get_num_parents(hw);
>>>>>> +    u32 val;
>>>>>> +
>>>>>> +    val = tegra_pmc_readl(pmc, mux->offs) >> mux->shift;
>>>>>> +    val &= mux->mask;
>>>>>> +
>>>>>> +    if (val >= num_parents)
>>>>>> +        return -EINVAL;
>>>>>> +
>>>>>> +    return val;
>>>>>> +}
>>>>>> +
>>>>>> +static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
>>>>>> +{
>>>>>> +    struct pmc_clk_mux *mux = to_pmc_clk_mux(hw);
>>>>>> +    u32 val;
>>>>>> +
>>>>>> +    val = tegra_pmc_readl(pmc, mux->offs);
>>>>>> +    val &= ~(mux->mask << mux->shift);
>>>>>> +    val |= index << mux->shift;
>>>>>> +    tegra_pmc_writel(pmc, val, mux->offs);
>>>>>> +    pmc_clk_fence_udelay(mux->offs);
>>>>>> +
>>>>>> +    return 0;
>>>>>> +}
>>>>>> +
>>>>>> +static const struct clk_ops pmc_clk_mux_ops = {
>>>>>> +    .get_parent = pmc_clk_mux_get_parent,
>>>>>> +    .set_parent = pmc_clk_mux_set_parent,
>>>>>> +    .determine_rate = __clk_mux_determine_rate,
>>>>>> +};
>>>>>> +
>>>>>> +static struct clk *
>>>>>> +tegra_pmc_clk_mux_register(const char *name, const char * const
>>>>>> *parent_names,
>>>>>> +               int num_parents, unsigned long flags,
>>>>>> +               unsigned long offset, u32 shift, u32 mask)
>>>>>> +{
>>>>>> +    struct clk_init_data init;
>>>>>> +    struct pmc_clk_mux *mux;
>>>>>> +
>>>>>> +    mux = kzalloc(sizeof(*mux), GFP_KERNEL);
>>>>>> +    if (!mux)
>>>>>> +        return ERR_PTR(-ENOMEM);
>>>>>> +
>>>>>> +    init.name = name;
>>>>>> +    init.ops = &pmc_clk_mux_ops;
>>>>>> +    init.parent_names = parent_names;
>>>>>> +    init.num_parents = num_parents;
>>>>>> +    init.flags = flags;
>>>>>> +
>>>>>> +    mux->hw.init = &init;
>>>>>> +    mux->offs = offset;
>>>>>> +    mux->mask = mask;
>>>>>> +    mux->shift = shift;
>>>>>> +
>>>>>> +    return clk_register(NULL, &mux->hw);
>>>>>> +}
>>>>>> +
>>>>>> +static int pmc_clk_is_enabled(struct clk_hw *hw)
>>>>>> +{
>>>>>> +    struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
>>>>>> +
>>>>>> +    return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1
>>>>>> : 0;
>>>>>> +}
>>>>>> +
>>>>>> +static void pmc_clk_set_state(struct clk_hw *hw, int state)
>>>>>> +{
>>>>>> +    struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
>>>>>> +    u32 val;
>>>>>> +
>>>>>> +    val = tegra_pmc_readl(pmc, gate->offs);
>>>>>> +    val = state ? (val | BIT(gate->shift)) : (val &
>>>>>> ~BIT(gate->shift));
>>>>>> +    tegra_pmc_writel(pmc, val, gate->offs);
>>>>>> +    pmc_clk_fence_udelay(gate->offs);
>>>>>> +}
>>>>>> +
>>>>>> +static int pmc_clk_enable(struct clk_hw *hw)
>>>>>> +{
>>>>>> +    pmc_clk_set_state(hw, 1);
>>>>>> +
>>>>>> +    return 0;
>>>>>> +}
>>>>>> +
>>>>>> +static void pmc_clk_disable(struct clk_hw *hw)
>>>>>> +{
>>>>>> +    pmc_clk_set_state(hw, 0);
>>>>>> +}
>>>>>> +
>>>>>> +static const struct clk_ops pmc_clk_gate_ops = {
>>>>>> +    .is_enabled = pmc_clk_is_enabled,
>>>>>> +    .enable = pmc_clk_enable,
>>>>>> +    .disable = pmc_clk_disable,
>>>>>> +};
>>>>>> +
>>>>>> +static struct clk *
>>>>>> +tegra_pmc_clk_gate_register(const char *name, const char
>>>>>> *parent_name,
>>>>>> +                unsigned long flags, unsigned long offset,
>>>>>> +                u32 shift)
>>>>>> +{
>>>>>> +    struct clk_init_data init;
>>>>>> +    struct pmc_clk_gate *gate;
>>>>>> +
>>>>>> +    gate = kzalloc(sizeof(*gate), GFP_KERNEL);
>>>>>> +    if (!gate)
>>>>>> +        return ERR_PTR(-ENOMEM);
>>>>>> +
>>>>>> +    init.name = name;
>>>>>> +    init.ops = &pmc_clk_gate_ops;
>>>>>> +    init.parent_names = &parent_name;
>>>>>> +    init.num_parents = 1;
>>>>>> +    init.flags = flags;
>>>>>> +
>>>>>> +    gate->hw.init = &init;
>>>>>> +    gate->offs = offset;
>>>>>> +    gate->shift = shift;
>>>>>> +
>>>>>> +    return clk_register(NULL, &gate->hw);
>>>>>> +}
>>>>>> +
>>>>>> +static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
>>>>>> +                     struct device_node *np)
>>>>>> +{
>>>>>> +    struct clk *clkmux, *clk, *parent;
>>>>>> +    struct clk_onecell_data *clk_data;
>>>>>> +    unsigned int num_clks;
>>>>>> +    int i, ret;
>>>>>> +
>>>>>> +    /* each pmc clock output has a mux and a gate */
>>>>>> +    num_clks = pmc->soc->num_pmc_clks * 2;
>>>>>> +
>>>>>> +    if (!num_clks)
>>>>>> +        return;
>>>>>> +
>>>>>> +    clk_data = kmalloc(sizeof(*clk_data), GFP_KERNEL);
>>>>>> +    if (!clk_data)
>>>>>> +        return;
>>>>>> +
>>>>>> +    clk_data->clks = kcalloc(TEGRA_PMC_CLK_MAX,
>>>>>> sizeof(*clk_data->clks),
>>>>>> +                 GFP_KERNEL);
>>>>>> +    if (!clk_data->clks)
>>>>>> +        goto free_clkdata;
>>>>>> +
>>>>>> +    clk_data->clk_num = num_clks;
>>>>>> +
>>>>>> +    for (i = 0; i < pmc->soc->num_pmc_clks; i++) {
>>>>>> +        struct pmc_clk_init_data *data;
>>>>>> +
>>>>>> +        data = pmc->soc->pmc_clks_data + i;
>>>>>> +
>>>>>> +        clkmux = tegra_pmc_clk_mux_register(data->mux_name,
>>>>>> +                            data->parents,
>>>>>> +                            data->num_parents,
>>>>>> +                            CLK_SET_RATE_NO_REPARENT |
>>>>>> +                            CLK_SET_RATE_PARENT,
>>>>>> +                            PMC_CLK_OUT_CNTRL,
>>>>>> +                            data->mux_shift, 3);
>>>>>> +        if (IS_ERR(clkmux))
>>>>>> +            goto free_clks;
>>>>>> +
>>>>>> +        clk_data->clks[data->mux_id] = clkmux;
>>>>>> +
>>>>>> +        clk = tegra_pmc_clk_gate_register(data->gate_name,
>>>>>> +                          data->mux_name,
>>>>>> +                          CLK_SET_RATE_PARENT,
>>>>>> +                          PMC_CLK_OUT_CNTRL,
>>>>>> +                          data->gate_shift);
>>>>>> +        if (IS_ERR(clk))
>>>>>> +            goto free_clks;
>>>>>> +
>>>>>> +        clk_data->clks[data->gate_id] = clk;
>>>>>> +
>>>>>> +        ret = clk_set_parent(clk, clkmux);
>>>>>> +        if (ret < 0) {
>>>>>> +            pr_err("failed to set parent of %s to %s\n",
>>>>>> +                   __func__, __clk_get_name(clk),
>>>>>> +                   __clk_get_name(clkmux));
>>>>>> +        }
>>>>>> +
>>>>>> +        clk_register_clkdev(clk, data->dev_name, data->gate_name);
>>>>>> +
>>>>>> +        /* configure initial clock parent and state */
>>>>>> +        parent = clk_get_sys(data->gate_name,
>>>>>> +                     data->parents[data->init_parent_index]);
> Couldn't the default parent be defined using "assigned clock" in a
> device-tree? Please see "Assigned clock parents and rates" in the doc.
>
> https://www.kernel.org/doc/Documentation/devicetree/bindings/clock/clock-bindings.txt
>
> Then you could simply use of_clk_set_defaults(pmc->dev->of_node, true).

Yes, of_clk_add_provider() does of_clk_set_defaults which sets based on 
assigned parents and clock rates.

This need device tree to specify assigned clock parent properties. Will 
update device tree and remove init parent from the driver.

>
>>>>>> +        if (!IS_ERR(parent)) {
>>>>>> +            ret = clk_set_parent(clkmux, parent);
>>>>>> +            if (ret < 0) {
>>>>>> +                pr_err("failed to set parent of %s to %s\n",
>>>>>> +                       __func__, __clk_get_name(clkmux),
>>>>>> +                       __clk_get_name(parent));
>>>>>> +                WARN_ON(1);
>>>>>> +            }
>>>>>> +        }
>>>>>> +
>>>>>> +        if (data->init_state) {
>>>>>> +            if (clk_prepare_enable(clk)) {
>>>>>> +                pr_err("failed to enable %s\n", __func__,
>>>>>> +                       __clk_get_name(clk));
>>>>>> +                WARN_ON(1);
>>> Alternatively you could write it like this:
>>>
>>>      err = clk_prepare_enable(clk);
>>>
>>>      WARN_ON(err, "failed to enable %s: %d\n",
>>>          __clk_get_name(clk), err);
>>>
>>>>> Should be a bit better to move the WARN_ON to the end of errors
>>>>> handling
>>>>> in order to catch all possible errors:
>>>>>
>>>>> @@ -2510,6 +2510,7 @@ static void tegra_pmc_clock_register(struct
>>>>> tegra_pmc *pmc,
>>>>>            return;
>>>>>
>>>>>     free_clks:
>>>>> +       WARN_ON(1);
>>>>>            kfree(clk_data->clks);
>>>>>     free_clkdata:
>>>>>            kfree(clk_data);
>>>> Reason I had WARN_ON right during clk_set_parent failure is to have the
>>>> loop continue for subsequence pmc clocks registration instead of
>>>> terminating all pmc clocks registration.
>>> Ah, okay. Nevertheless this WARN_ON in the end shouldn't be the least
>>> (IMO).
>> Hi Dmitry, Just want to be clear on the above comment. Are you
>> suggesting to add additional WARN_ON at the end?
> Yes, it was my suggestion.
>
>> Thought WARN_ON right during corresponding clock failure with warn
>> message showing clock names will be clear and also other clocks still
>> should be registered.
>>
>> To add additional WARN_ON at the end need to track status of each clock
>> and use that to as warn condition.
> You could add a warning/error message to every point of failure.
>
> Primarily, it is important not to miss a error. Secondarily, it is
> important to make diagnostic message meaningful.
>
> Realistically, I doubt that this chunk of code will ever fail once it is
> known to work well. So it will be nice to have a more detailed
> diagnostics (just in a case), but it shouldn't be a must.

OK, Will add additional WARN message "failed registering PMC clocks" at 
the end.

On 12/2/19 2:58 PM, Sowjanya Komatineni wrote:
>
> On 12/2/19 1:50 PM, Dmitry Osipenko wrote:
>> 02.12.2019 23:09, Sowjanya Komatineni пишет:
>>> On 11/28/19 5:25 AM, Dmitry Osipenko wrote:
>>>> 28.11.2019 01:57, Sowjanya Komatineni пишет:
>>>>> On 11/27/19 7:14 AM, Dmitry Osipenko wrote:
>>>>>> 27.11.2019 07:59, Sowjanya Komatineni пишет:
>>>>>>> Tegra210 and prior Tegra PMC has clk_out_1, clk_out_2, clk_out_3 
>>>>>>> with
>>>>>>> mux and gate for each of these clocks.
>>>>>>>
>>>>>>> Currently these PMC clocks are registered by Tegra clock driver 
>>>>>>> using
>>>>>>> clk_register_mux and clk_register_gate by passing PMC base address
>>>>>>> and register offsets and PMC programming for these clocks happens
>>>>>>> through direct PMC access by the clock driver.
>>>>>>>
>>>>>>> With this, when PMC is in secure mode any direct PMC access from 
>>>>>>> the
>>>>>>> non-secure world does not go through and these clocks will not be
>>>>>>> functional.
>>>>>>>
>>>>>>> This patch adds these clocks registration with PMC as a clock 
>>>>>>> provider
>>>>>>> for these clocks. clk_ops callback implementations for these clocks
>>>>>>> uses tegra_pmc_readl and tegra_pmc_writel which supports PMC
>>>>>>> programming
>>>>>>> in secure mode and non-secure mode.
>>>>>>>
>>>>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>>>>> ---
>>>>>>>     drivers/soc/tegra/pmc.c | 330
>>>>>>> ++++++++++++++++++++++++++++++++++++++++++++++++
>>>>>>>     1 file changed, 330 insertions(+)
>>>>>>>
>>>>>>> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
>>>>>>> index ea0e11a09c12..a353f6d0a832 100644
>>>>>>> --- a/drivers/soc/tegra/pmc.c
>>>>>>> +++ b/drivers/soc/tegra/pmc.c
>>>>>>> @@ -13,6 +13,9 @@
>>>>>>>       #include <linux/arm-smccc.h>
>>>>>>>     #include <linux/clk.h>
>>>>>>> +#include <linux/clk-provider.h>
>>>>>>> +#include <linux/clkdev.h>
>>>>>>> +#include <linux/clk/clk-conf.h>
>>>>>>>     #include <linux/clk/tegra.h>
>>>>>>>     #include <linux/debugfs.h>
>>>>>>>     #include <linux/delay.h>
>>>>>>> @@ -48,6 +51,7 @@
>>>>>>>     #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
>>>>>>>     #include <dt-bindings/gpio/tegra186-gpio.h>
>>>>>>>     #include <dt-bindings/gpio/tegra194-gpio.h>
>>>>>>> +#include <dt-bindings/soc/tegra-pmc.h>
>>>>>>>       #define PMC_CNTRL            0x0
>>>>>>>     #define  PMC_CNTRL_INTR_POLARITY    BIT(17) /* inverts INTR
>>>>>>> polarity */
>>>>>>> @@ -100,6 +104,7 @@
>>>>>>>     #define PMC_WAKE2_STATUS        0x168
>>>>>>>     #define PMC_SW_WAKE2_STATUS        0x16c
>>>>>>>     +#define PMC_CLK_OUT_CNTRL        0x1a8
>>>>>>>     #define PMC_SENSOR_CTRL            0x1b0
>>>>>>>     #define  PMC_SENSOR_CTRL_SCRATCH_WRITE    BIT(2)
>>>>>>>     #define  PMC_SENSOR_CTRL_ENABLE_RST    BIT(1)
>>>>>>> @@ -155,6 +160,91 @@
>>>>>>>     #define  TEGRA_SMC_PMC_READ    0xaa
>>>>>>>     #define  TEGRA_SMC_PMC_WRITE    0xbb
>>>>>>>     +struct pmc_clk_mux {
>>>>>>> +    struct clk_hw    hw;
>>>>>>> +    unsigned long    offs;
>>>>>>> +    u32        mask;
>>>>>>> +    u32        shift;
>>>>>>> +};
>>>>>>> +
>>>>>>> +#define to_pmc_clk_mux(_hw) container_of(_hw, struct 
>>>>>>> pmc_clk_mux, hw)
>>>>>>> +
>>>>>>> +struct pmc_clk_gate {
>>>>>>> +    struct clk_hw    hw;
>>>>>>> +    unsigned long    offs;
>>>>>>> +    u32        shift;
>>>>>>> +};
>>>>>>> +
>>>>>>> +#define to_pmc_clk_gate(_hw) container_of(_hw, struct
>>>>>>> pmc_clk_gate, hw)
>>>>>>> +
>>>>>>> +struct pmc_clk_init_data {
>>>>>>> +    char *mux_name;
>>>>>>> +    char *gate_name;
>>>>>>> +    const char **parents;
>>>>>>> +    int num_parents;
>>>>>>> +    int mux_id;
>>>>>>> +    int gate_id;
>>>>>>> +    char *dev_name;
>>>>>>> +    u8 mux_shift;
>>>>>>> +    u8 gate_shift;
>>>>>>> +    u8 init_parent_index;
>>>>>>> +    int init_state;
>>>>>>> +};
>>>>>>> +
>>>>>>> +static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2",
>>>>>>> +    "clk_m_div4", "extern1",
>>>>>>> +};
>>>>>>> +
>>>>>>> +static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2",
>>>>>>> +    "clk_m_div4", "extern2",
>>>>>>> +};
>>>>>>> +
>>>>>>> +static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2",
>>>>>>> +    "clk_m_div4", "extern3",
>>>>>>> +};
>>>>>>> +
>>>>>>> +static struct pmc_clk_init_data tegra_pmc_clks_data[] = {
>>>>>>> +    {
>>>>>>> +        .mux_name = "clk_out_1_mux",
>>>>>>> +        .gate_name = "clk_out_1",
>>>>>>> +        .parents = clk_out1_parents,
>>>>>>> +        .num_parents = ARRAY_SIZE(clk_out1_parents),
>>>>>>> +        .mux_id = TEGRA_PMC_CLK_OUT_1_MUX,
>>>>>>> +        .gate_id = TEGRA_PMC_CLK_OUT_1,
>>>>>>> +        .dev_name = "extern1",
>>>>>>> +        .mux_shift = 6,
>>>>>>> +        .gate_shift = 2,
>>>>>>> +        .init_parent_index = 3,
>>>>>>> +        .init_state = 1,
>>>>>>> +    },
>>>>>>> +    {
>>>>>>> +        .mux_name = "clk_out_2_mux",
>>>>>>> +        .gate_name = "clk_out_2",
>>>>>>> +        .parents = clk_out2_parents,
>>>>>>> +        .num_parents = ARRAY_SIZE(clk_out2_parents),
>>>>>>> +        .mux_id = TEGRA_PMC_CLK_OUT_2_MUX,
>>>>>>> +        .gate_id = TEGRA_PMC_CLK_OUT_2,
>>>>>>> +        .dev_name = "extern2",
>>>>>>> +        .mux_shift = 14,
>>>>>>> +        .gate_shift = 10,
>>>>>>> +        .init_parent_index = 0,
>>>>>>> +        .init_state = 0,
>>>>>>> +    },
>>>>>>> +    {
>>>>>>> +        .mux_name = "clk_out_3_mux",
>>>>>>> +        .gate_name = "clk_out_3",
>>>>>>> +        .parents = clk_out3_parents,
>>>>>>> +        .num_parents = ARRAY_SIZE(clk_out3_parents),
>>>>>>> +        .mux_id = TEGRA_PMC_CLK_OUT_3_MUX,
>>>>>>> +        .gate_id = TEGRA_PMC_CLK_OUT_3,
>>>>>>> +        .dev_name = "extern3",
>>>>>>> +        .mux_shift = 22,
>>>>>>> +        .gate_shift = 18,
>>>>>>> +        .init_parent_index = 0,
>>>>>>> +        .init_state = 0,
>>>>>>> +    },
>>>>>>> +};
>>>>>>> +
>>>>>>>     struct tegra_powergate {
>>>>>>>         struct generic_pm_domain genpd;
>>>>>>>         struct tegra_pmc *pmc;
>>>>>>> @@ -254,6 +344,9 @@ struct tegra_pmc_soc {
>>>>>>>          */
>>>>>>>         const struct tegra_wake_event *wake_events;
>>>>>>>         unsigned int num_wake_events;
>>>>>>> +
>>>>>>> +    struct pmc_clk_init_data *pmc_clks_data;
>>>>>>> +    unsigned int num_pmc_clks;
>>>>>>>     };
>>>>>>>       static const char * const tegra186_reset_sources[] = {
>>>>>>> @@ -2163,6 +2256,228 @@ static int tegra_pmc_clk_notify_cb(struct
>>>>>>> notifier_block *nb,
>>>>>>>         return NOTIFY_OK;
>>>>>>>     }
>>>>>>>     +static void pmc_clk_fence_udelay(u32 offset)
>>>>>>> +{
>>>>>>> +    tegra_pmc_readl(pmc, offset);
>>>>>>> +    /* pmc clk propagation delay 2 us */
>>>>>>> +    udelay(2);
>>>>>>> +}
>>>>>>> +
>>>>>>> +static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
>>>>>>> +{
>>>>>>> +    struct pmc_clk_mux *mux = to_pmc_clk_mux(hw);
>>>>>>> +    int num_parents = clk_hw_get_num_parents(hw);
>>>>>>> +    u32 val;
>>>>>>> +
>>>>>>> +    val = tegra_pmc_readl(pmc, mux->offs) >> mux->shift;
>>>>>>> +    val &= mux->mask;
>>>>>>> +
>>>>>>> +    if (val >= num_parents)
>>>>>>> +        return -EINVAL;
>>>>>>> +
>>>>>>> +    return val;
>>>>>>> +}
>>>>>>> +
>>>>>>> +static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
>>>>>>> +{
>>>>>>> +    struct pmc_clk_mux *mux = to_pmc_clk_mux(hw);
>>>>>>> +    u32 val;
>>>>>>> +
>>>>>>> +    val = tegra_pmc_readl(pmc, mux->offs);
>>>>>>> +    val &= ~(mux->mask << mux->shift);
>>>>>>> +    val |= index << mux->shift;
>>>>>>> +    tegra_pmc_writel(pmc, val, mux->offs);
>>>>>>> +    pmc_clk_fence_udelay(mux->offs);
>>>>>>> +
>>>>>>> +    return 0;
>>>>>>> +}
>>>>>>> +
>>>>>>> +static const struct clk_ops pmc_clk_mux_ops = {
>>>>>>> +    .get_parent = pmc_clk_mux_get_parent,
>>>>>>> +    .set_parent = pmc_clk_mux_set_parent,
>>>>>>> +    .determine_rate = __clk_mux_determine_rate,
>>>>>>> +};
>>>>>>> +
>>>>>>> +static struct clk *
>>>>>>> +tegra_pmc_clk_mux_register(const char *name, const char * const
>>>>>>> *parent_names,
>>>>>>> +               int num_parents, unsigned long flags,
>>>>>>> +               unsigned long offset, u32 shift, u32 mask)
>>>>>>> +{
>>>>>>> +    struct clk_init_data init;
>>>>>>> +    struct pmc_clk_mux *mux;
>>>>>>> +
>>>>>>> +    mux = kzalloc(sizeof(*mux), GFP_KERNEL);
>>>>>>> +    if (!mux)
>>>>>>> +        return ERR_PTR(-ENOMEM);
>>>>>>> +
>>>>>>> +    init.name = name;
>>>>>>> +    init.ops = &pmc_clk_mux_ops;
>>>>>>> +    init.parent_names = parent_names;
>>>>>>> +    init.num_parents = num_parents;
>>>>>>> +    init.flags = flags;
>>>>>>> +
>>>>>>> +    mux->hw.init = &init;
>>>>>>> +    mux->offs = offset;
>>>>>>> +    mux->mask = mask;
>>>>>>> +    mux->shift = shift;
>>>>>>> +
>>>>>>> +    return clk_register(NULL, &mux->hw);
>>>>>>> +}
>>>>>>> +
>>>>>>> +static int pmc_clk_is_enabled(struct clk_hw *hw)
>>>>>>> +{
>>>>>>> +    struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
>>>>>>> +
>>>>>>> +    return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1
>>>>>>> : 0;
>>>>>>> +}
>>>>>>> +
>>>>>>> +static void pmc_clk_set_state(struct clk_hw *hw, int state)
>>>>>>> +{
>>>>>>> +    struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
>>>>>>> +    u32 val;
>>>>>>> +
>>>>>>> +    val = tegra_pmc_readl(pmc, gate->offs);
>>>>>>> +    val = state ? (val | BIT(gate->shift)) : (val &
>>>>>>> ~BIT(gate->shift));
>>>>>>> +    tegra_pmc_writel(pmc, val, gate->offs);
>>>>>>> +    pmc_clk_fence_udelay(gate->offs);
>>>>>>> +}
>>>>>>> +
>>>>>>> +static int pmc_clk_enable(struct clk_hw *hw)
>>>>>>> +{
>>>>>>> +    pmc_clk_set_state(hw, 1);
>>>>>>> +
>>>>>>> +    return 0;
>>>>>>> +}
>>>>>>> +
>>>>>>> +static void pmc_clk_disable(struct clk_hw *hw)
>>>>>>> +{
>>>>>>> +    pmc_clk_set_state(hw, 0);
>>>>>>> +}
>>>>>>> +
>>>>>>> +static const struct clk_ops pmc_clk_gate_ops = {
>>>>>>> +    .is_enabled = pmc_clk_is_enabled,
>>>>>>> +    .enable = pmc_clk_enable,
>>>>>>> +    .disable = pmc_clk_disable,
>>>>>>> +};
>>>>>>> +
>>>>>>> +static struct clk *
>>>>>>> +tegra_pmc_clk_gate_register(const char *name, const char
>>>>>>> *parent_name,
>>>>>>> +                unsigned long flags, unsigned long offset,
>>>>>>> +                u32 shift)
>>>>>>> +{
>>>>>>> +    struct clk_init_data init;
>>>>>>> +    struct pmc_clk_gate *gate;
>>>>>>> +
>>>>>>> +    gate = kzalloc(sizeof(*gate), GFP_KERNEL);
>>>>>>> +    if (!gate)
>>>>>>> +        return ERR_PTR(-ENOMEM);
>>>>>>> +
>>>>>>> +    init.name = name;
>>>>>>> +    init.ops = &pmc_clk_gate_ops;
>>>>>>> +    init.parent_names = &parent_name;
>>>>>>> +    init.num_parents = 1;
>>>>>>> +    init.flags = flags;
>>>>>>> +
>>>>>>> +    gate->hw.init = &init;
>>>>>>> +    gate->offs = offset;
>>>>>>> +    gate->shift = shift;
>>>>>>> +
>>>>>>> +    return clk_register(NULL, &gate->hw);
>>>>>>> +}
>>>>>>> +
>>>>>>> +static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
>>>>>>> +                     struct device_node *np)
>>>>>>> +{
>>>>>>> +    struct clk *clkmux, *clk, *parent;
>>>>>>> +    struct clk_onecell_data *clk_data;
>>>>>>> +    unsigned int num_clks;
>>>>>>> +    int i, ret;
>>>>>>> +
>>>>>>> +    /* each pmc clock output has a mux and a gate */
>>>>>>> +    num_clks = pmc->soc->num_pmc_clks * 2;
>>>>>>> +
>>>>>>> +    if (!num_clks)
>>>>>>> +        return;
>>>>>>> +
>>>>>>> +    clk_data = kmalloc(sizeof(*clk_data), GFP_KERNEL);
>>>>>>> +    if (!clk_data)
>>>>>>> +        return;
>>>>>>> +
>>>>>>> +    clk_data->clks = kcalloc(TEGRA_PMC_CLK_MAX,
>>>>>>> sizeof(*clk_data->clks),
>>>>>>> +                 GFP_KERNEL);
>>>>>>> +    if (!clk_data->clks)
>>>>>>> +        goto free_clkdata;
>>>>>>> +
>>>>>>> +    clk_data->clk_num = num_clks;
>>>>>>> +
>>>>>>> +    for (i = 0; i < pmc->soc->num_pmc_clks; i++) {
>>>>>>> +        struct pmc_clk_init_data *data;
>>>>>>> +
>>>>>>> +        data = pmc->soc->pmc_clks_data + i;
>>>>>>> +
>>>>>>> +        clkmux = tegra_pmc_clk_mux_register(data->mux_name,
>>>>>>> +                            data->parents,
>>>>>>> +                            data->num_parents,
>>>>>>> +                            CLK_SET_RATE_NO_REPARENT |
>>>>>>> +                            CLK_SET_RATE_PARENT,
>>>>>>> +                            PMC_CLK_OUT_CNTRL,
>>>>>>> +                            data->mux_shift, 3);
>>>>>>> +        if (IS_ERR(clkmux))
>>>>>>> +            goto free_clks;
>>>>>>> +
>>>>>>> +        clk_data->clks[data->mux_id] = clkmux;
>>>>>>> +
>>>>>>> +        clk = tegra_pmc_clk_gate_register(data->gate_name,
>>>>>>> +                          data->mux_name,
>>>>>>> +                          CLK_SET_RATE_PARENT,
>>>>>>> +                          PMC_CLK_OUT_CNTRL,
>>>>>>> +                          data->gate_shift);
>>>>>>> +        if (IS_ERR(clk))
>>>>>>> +            goto free_clks;
>>>>>>> +
>>>>>>> +        clk_data->clks[data->gate_id] = clk;
>>>>>>> +
>>>>>>> +        ret = clk_set_parent(clk, clkmux);
>>>>>>> +        if (ret < 0) {
>>>>>>> +            pr_err("failed to set parent of %s to %s\n",
>>>>>>> +                   __func__, __clk_get_name(clk),
>>>>>>> +                   __clk_get_name(clkmux));
>>>>>>> +        }
>>>>>>> +
>>>>>>> +        clk_register_clkdev(clk, data->dev_name, data->gate_name);
>>>>>>> +
>>>>>>> +        /* configure initial clock parent and state */
>>>>>>> +        parent = clk_get_sys(data->gate_name,
>>>>>>> + data->parents[data->init_parent_index]);
>> Couldn't the default parent be defined using "assigned clock" in a
>> device-tree? Please see "Assigned clock parents and rates" in the doc.
>>
>> https://www.kernel.org/doc/Documentation/devicetree/bindings/clock/clock-bindings.txt 
>>
>>
>> Then you could simply use of_clk_set_defaults(pmc->dev->of_node, true).
>
> Yes, of_clk_add_provider() does of_clk_set_defaults which sets based 
> on assigned parents and clock rates.
>
> This need device tree to specify assigned clock parent properties. 
> Will update device tree and remove init parent from the driver.
>
assigned-clock properties should be set in consumer node of these clocks 
and currently these clocks are not used yet.

So will just remove init parent from driver and when these clocks are 
used device tree can be updated in corresponding consumer node with 
these properties.

>>
>>>>>>> +        if (!IS_ERR(parent)) {
>>>>>>> +            ret = clk_set_parent(clkmux, parent);
>>>>>>> +            if (ret < 0) {
>>>>>>> +                pr_err("failed to set parent of %s to %s\n",
>>>>>>> +                       __func__, __clk_get_name(clkmux),
>>>>>>> +                       __clk_get_name(parent));
>>>>>>> +                WARN_ON(1);
>>>>>>> +            }
>>>>>>> +        }
>>>>>>> +
>>>>>>> +        if (data->init_state) {
>>>>>>> +            if (clk_prepare_enable(clk)) {
>>>>>>> +                pr_err("failed to enable %s\n", __func__,
>>>>>>> +                       __clk_get_name(clk));
>>>>>>> +                WARN_ON(1);
>>>> Alternatively you could write it like this:
>>>>
>>>>      err = clk_prepare_enable(clk);
>>>>
>>>>      WARN_ON(err, "failed to enable %s: %d\n",
>>>>          __clk_get_name(clk), err);
>>>>
>>>>>> Should be a bit better to move the WARN_ON to the end of errors
>>>>>> handling
>>>>>> in order to catch all possible errors:
>>>>>>
>>>>>> @@ -2510,6 +2510,7 @@ static void tegra_pmc_clock_register(struct
>>>>>> tegra_pmc *pmc,
>>>>>>            return;
>>>>>>
>>>>>>     free_clks:
>>>>>> +       WARN_ON(1);
>>>>>>            kfree(clk_data->clks);
>>>>>>     free_clkdata:
>>>>>>            kfree(clk_data);
>>>>> Reason I had WARN_ON right during clk_set_parent failure is to 
>>>>> have the
>>>>> loop continue for subsequence pmc clocks registration instead of
>>>>> terminating all pmc clocks registration.
>>>> Ah, okay. Nevertheless this WARN_ON in the end shouldn't be the least
>>>> (IMO).
>>> Hi Dmitry, Just want to be clear on the above comment. Are you
>>> suggesting to add additional WARN_ON at the end?
>> Yes, it was my suggestion.
>>
>>> Thought WARN_ON right during corresponding clock failure with warn
>>> message showing clock names will be clear and also other clocks still
>>> should be registered.
>>>
>>> To add additional WARN_ON at the end need to track status of each clock
>>> and use that to as warn condition.
>> You could add a warning/error message to every point of failure.
>>
>> Primarily, it is important not to miss a error. Secondarily, it is
>> important to make diagnostic message meaningful.
>>
>> Realistically, I doubt that this chunk of code will ever fail once it is
>> known to work well. So it will be nice to have a more detailed
>> diagnostics (just in a case), but it shouldn't be a must.
>
> OK, Will add additional WARN message "failed registering PMC clocks" 
> at the end.
>

On 12/2/19 3:10 PM, Sowjanya Komatineni wrote:
>
> On 12/2/19 2:58 PM, Sowjanya Komatineni wrote:
>>
>> On 12/2/19 1:50 PM, Dmitry Osipenko wrote:
>>> 02.12.2019 23:09, Sowjanya Komatineni пишет:
>>>> On 11/28/19 5:25 AM, Dmitry Osipenko wrote:
>>>>> 28.11.2019 01:57, Sowjanya Komatineni пишет:
>>>>>> On 11/27/19 7:14 AM, Dmitry Osipenko wrote:
>>>>>>> 27.11.2019 07:59, Sowjanya Komatineni пишет:
>>>>>>>> Tegra210 and prior Tegra PMC has clk_out_1, clk_out_2, 
>>>>>>>> clk_out_3 with
>>>>>>>> mux and gate for each of these clocks.
>>>>>>>>
>>>>>>>> Currently these PMC clocks are registered by Tegra clock driver 
>>>>>>>> using
>>>>>>>> clk_register_mux and clk_register_gate by passing PMC base address
>>>>>>>> and register offsets and PMC programming for these clocks happens
>>>>>>>> through direct PMC access by the clock driver.
>>>>>>>>
>>>>>>>> With this, when PMC is in secure mode any direct PMC access 
>>>>>>>> from the
>>>>>>>> non-secure world does not go through and these clocks will not be
>>>>>>>> functional.
>>>>>>>>
>>>>>>>> This patch adds these clocks registration with PMC as a clock 
>>>>>>>> provider
>>>>>>>> for these clocks. clk_ops callback implementations for these 
>>>>>>>> clocks
>>>>>>>> uses tegra_pmc_readl and tegra_pmc_writel which supports PMC
>>>>>>>> programming
>>>>>>>> in secure mode and non-secure mode.
>>>>>>>>
>>>>>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>>>>>> ---
>>>>>>>>     drivers/soc/tegra/pmc.c | 330
>>>>>>>> ++++++++++++++++++++++++++++++++++++++++++++++++
>>>>>>>>     1 file changed, 330 insertions(+)
>>>>>>>>
>>>>>>>> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
>>>>>>>> index ea0e11a09c12..a353f6d0a832 100644
>>>>>>>> --- a/drivers/soc/tegra/pmc.c
>>>>>>>> +++ b/drivers/soc/tegra/pmc.c
>>>>>>>> @@ -13,6 +13,9 @@
>>>>>>>>       #include <linux/arm-smccc.h>
>>>>>>>>     #include <linux/clk.h>
>>>>>>>> +#include <linux/clk-provider.h>
>>>>>>>> +#include <linux/clkdev.h>
>>>>>>>> +#include <linux/clk/clk-conf.h>
>>>>>>>>     #include <linux/clk/tegra.h>
>>>>>>>>     #include <linux/debugfs.h>
>>>>>>>>     #include <linux/delay.h>
>>>>>>>> @@ -48,6 +51,7 @@
>>>>>>>>     #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
>>>>>>>>     #include <dt-bindings/gpio/tegra186-gpio.h>
>>>>>>>>     #include <dt-bindings/gpio/tegra194-gpio.h>
>>>>>>>> +#include <dt-bindings/soc/tegra-pmc.h>
>>>>>>>>       #define PMC_CNTRL            0x0
>>>>>>>>     #define  PMC_CNTRL_INTR_POLARITY    BIT(17) /* inverts INTR
>>>>>>>> polarity */
>>>>>>>> @@ -100,6 +104,7 @@
>>>>>>>>     #define PMC_WAKE2_STATUS        0x168
>>>>>>>>     #define PMC_SW_WAKE2_STATUS        0x16c
>>>>>>>>     +#define PMC_CLK_OUT_CNTRL        0x1a8
>>>>>>>>     #define PMC_SENSOR_CTRL            0x1b0
>>>>>>>>     #define  PMC_SENSOR_CTRL_SCRATCH_WRITE    BIT(2)
>>>>>>>>     #define  PMC_SENSOR_CTRL_ENABLE_RST    BIT(1)
>>>>>>>> @@ -155,6 +160,91 @@
>>>>>>>>     #define  TEGRA_SMC_PMC_READ    0xaa
>>>>>>>>     #define  TEGRA_SMC_PMC_WRITE    0xbb
>>>>>>>>     +struct pmc_clk_mux {
>>>>>>>> +    struct clk_hw    hw;
>>>>>>>> +    unsigned long    offs;
>>>>>>>> +    u32        mask;
>>>>>>>> +    u32        shift;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +#define to_pmc_clk_mux(_hw) container_of(_hw, struct 
>>>>>>>> pmc_clk_mux, hw)
>>>>>>>> +
>>>>>>>> +struct pmc_clk_gate {
>>>>>>>> +    struct clk_hw    hw;
>>>>>>>> +    unsigned long    offs;
>>>>>>>> +    u32        shift;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +#define to_pmc_clk_gate(_hw) container_of(_hw, struct
>>>>>>>> pmc_clk_gate, hw)
>>>>>>>> +
>>>>>>>> +struct pmc_clk_init_data {
>>>>>>>> +    char *mux_name;
>>>>>>>> +    char *gate_name;
>>>>>>>> +    const char **parents;
>>>>>>>> +    int num_parents;
>>>>>>>> +    int mux_id;
>>>>>>>> +    int gate_id;
>>>>>>>> +    char *dev_name;
>>>>>>>> +    u8 mux_shift;
>>>>>>>> +    u8 gate_shift;
>>>>>>>> +    u8 init_parent_index;
>>>>>>>> +    int init_state;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2",
>>>>>>>> +    "clk_m_div4", "extern1",
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2",
>>>>>>>> +    "clk_m_div4", "extern2",
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2",
>>>>>>>> +    "clk_m_div4", "extern3",
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +static struct pmc_clk_init_data tegra_pmc_clks_data[] = {
>>>>>>>> +    {
>>>>>>>> +        .mux_name = "clk_out_1_mux",
>>>>>>>> +        .gate_name = "clk_out_1",
>>>>>>>> +        .parents = clk_out1_parents,
>>>>>>>> +        .num_parents = ARRAY_SIZE(clk_out1_parents),
>>>>>>>> +        .mux_id = TEGRA_PMC_CLK_OUT_1_MUX,
>>>>>>>> +        .gate_id = TEGRA_PMC_CLK_OUT_1,
>>>>>>>> +        .dev_name = "extern1",
>>>>>>>> +        .mux_shift = 6,
>>>>>>>> +        .gate_shift = 2,
>>>>>>>> +        .init_parent_index = 3,
>>>>>>>> +        .init_state = 1,
>>>>>>>> +    },
>>>>>>>> +    {
>>>>>>>> +        .mux_name = "clk_out_2_mux",
>>>>>>>> +        .gate_name = "clk_out_2",
>>>>>>>> +        .parents = clk_out2_parents,
>>>>>>>> +        .num_parents = ARRAY_SIZE(clk_out2_parents),
>>>>>>>> +        .mux_id = TEGRA_PMC_CLK_OUT_2_MUX,
>>>>>>>> +        .gate_id = TEGRA_PMC_CLK_OUT_2,
>>>>>>>> +        .dev_name = "extern2",
>>>>>>>> +        .mux_shift = 14,
>>>>>>>> +        .gate_shift = 10,
>>>>>>>> +        .init_parent_index = 0,
>>>>>>>> +        .init_state = 0,
>>>>>>>> +    },
>>>>>>>> +    {
>>>>>>>> +        .mux_name = "clk_out_3_mux",
>>>>>>>> +        .gate_name = "clk_out_3",
>>>>>>>> +        .parents = clk_out3_parents,
>>>>>>>> +        .num_parents = ARRAY_SIZE(clk_out3_parents),
>>>>>>>> +        .mux_id = TEGRA_PMC_CLK_OUT_3_MUX,
>>>>>>>> +        .gate_id = TEGRA_PMC_CLK_OUT_3,
>>>>>>>> +        .dev_name = "extern3",
>>>>>>>> +        .mux_shift = 22,
>>>>>>>> +        .gate_shift = 18,
>>>>>>>> +        .init_parent_index = 0,
>>>>>>>> +        .init_state = 0,
>>>>>>>> +    },
>>>>>>>> +};
>>>>>>>> +
>>>>>>>>     struct tegra_powergate {
>>>>>>>>         struct generic_pm_domain genpd;
>>>>>>>>         struct tegra_pmc *pmc;
>>>>>>>> @@ -254,6 +344,9 @@ struct tegra_pmc_soc {
>>>>>>>>          */
>>>>>>>>         const struct tegra_wake_event *wake_events;
>>>>>>>>         unsigned int num_wake_events;
>>>>>>>> +
>>>>>>>> +    struct pmc_clk_init_data *pmc_clks_data;
>>>>>>>> +    unsigned int num_pmc_clks;
>>>>>>>>     };
>>>>>>>>       static const char * const tegra186_reset_sources[] = {
>>>>>>>> @@ -2163,6 +2256,228 @@ static int tegra_pmc_clk_notify_cb(struct
>>>>>>>> notifier_block *nb,
>>>>>>>>         return NOTIFY_OK;
>>>>>>>>     }
>>>>>>>>     +static void pmc_clk_fence_udelay(u32 offset)
>>>>>>>> +{
>>>>>>>> +    tegra_pmc_readl(pmc, offset);
>>>>>>>> +    /* pmc clk propagation delay 2 us */
>>>>>>>> +    udelay(2);
>>>>>>>> +}
>>>>>>>> +
>>>>>>>> +static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
>>>>>>>> +{
>>>>>>>> +    struct pmc_clk_mux *mux = to_pmc_clk_mux(hw);
>>>>>>>> +    int num_parents = clk_hw_get_num_parents(hw);
>>>>>>>> +    u32 val;
>>>>>>>> +
>>>>>>>> +    val = tegra_pmc_readl(pmc, mux->offs) >> mux->shift;
>>>>>>>> +    val &= mux->mask;
>>>>>>>> +
>>>>>>>> +    if (val >= num_parents)
>>>>>>>> +        return -EINVAL;
>>>>>>>> +
>>>>>>>> +    return val;
>>>>>>>> +}
>>>>>>>> +
>>>>>>>> +static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
>>>>>>>> +{
>>>>>>>> +    struct pmc_clk_mux *mux = to_pmc_clk_mux(hw);
>>>>>>>> +    u32 val;
>>>>>>>> +
>>>>>>>> +    val = tegra_pmc_readl(pmc, mux->offs);
>>>>>>>> +    val &= ~(mux->mask << mux->shift);
>>>>>>>> +    val |= index << mux->shift;
>>>>>>>> +    tegra_pmc_writel(pmc, val, mux->offs);
>>>>>>>> +    pmc_clk_fence_udelay(mux->offs);
>>>>>>>> +
>>>>>>>> +    return 0;
>>>>>>>> +}
>>>>>>>> +
>>>>>>>> +static const struct clk_ops pmc_clk_mux_ops = {
>>>>>>>> +    .get_parent = pmc_clk_mux_get_parent,
>>>>>>>> +    .set_parent = pmc_clk_mux_set_parent,
>>>>>>>> +    .determine_rate = __clk_mux_determine_rate,
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +static struct clk *
>>>>>>>> +tegra_pmc_clk_mux_register(const char *name, const char * const
>>>>>>>> *parent_names,
>>>>>>>> +               int num_parents, unsigned long flags,
>>>>>>>> +               unsigned long offset, u32 shift, u32 mask)
>>>>>>>> +{
>>>>>>>> +    struct clk_init_data init;
>>>>>>>> +    struct pmc_clk_mux *mux;
>>>>>>>> +
>>>>>>>> +    mux = kzalloc(sizeof(*mux), GFP_KERNEL);
>>>>>>>> +    if (!mux)
>>>>>>>> +        return ERR_PTR(-ENOMEM);
>>>>>>>> +
>>>>>>>> +    init.name = name;
>>>>>>>> +    init.ops = &pmc_clk_mux_ops;
>>>>>>>> +    init.parent_names = parent_names;
>>>>>>>> +    init.num_parents = num_parents;
>>>>>>>> +    init.flags = flags;
>>>>>>>> +
>>>>>>>> +    mux->hw.init = &init;
>>>>>>>> +    mux->offs = offset;
>>>>>>>> +    mux->mask = mask;
>>>>>>>> +    mux->shift = shift;
>>>>>>>> +
>>>>>>>> +    return clk_register(NULL, &mux->hw);
>>>>>>>> +}
>>>>>>>> +
>>>>>>>> +static int pmc_clk_is_enabled(struct clk_hw *hw)
>>>>>>>> +{
>>>>>>>> +    struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
>>>>>>>> +
>>>>>>>> +    return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) 
>>>>>>>> ? 1
>>>>>>>> : 0;
>>>>>>>> +}
>>>>>>>> +
>>>>>>>> +static void pmc_clk_set_state(struct clk_hw *hw, int state)
>>>>>>>> +{
>>>>>>>> +    struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
>>>>>>>> +    u32 val;
>>>>>>>> +
>>>>>>>> +    val = tegra_pmc_readl(pmc, gate->offs);
>>>>>>>> +    val = state ? (val | BIT(gate->shift)) : (val &
>>>>>>>> ~BIT(gate->shift));
>>>>>>>> +    tegra_pmc_writel(pmc, val, gate->offs);
>>>>>>>> +    pmc_clk_fence_udelay(gate->offs);
>>>>>>>> +}
>>>>>>>> +
>>>>>>>> +static int pmc_clk_enable(struct clk_hw *hw)
>>>>>>>> +{
>>>>>>>> +    pmc_clk_set_state(hw, 1);
>>>>>>>> +
>>>>>>>> +    return 0;
>>>>>>>> +}
>>>>>>>> +
>>>>>>>> +static void pmc_clk_disable(struct clk_hw *hw)
>>>>>>>> +{
>>>>>>>> +    pmc_clk_set_state(hw, 0);
>>>>>>>> +}
>>>>>>>> +
>>>>>>>> +static const struct clk_ops pmc_clk_gate_ops = {
>>>>>>>> +    .is_enabled = pmc_clk_is_enabled,
>>>>>>>> +    .enable = pmc_clk_enable,
>>>>>>>> +    .disable = pmc_clk_disable,
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +static struct clk *
>>>>>>>> +tegra_pmc_clk_gate_register(const char *name, const char
>>>>>>>> *parent_name,
>>>>>>>> +                unsigned long flags, unsigned long offset,
>>>>>>>> +                u32 shift)
>>>>>>>> +{
>>>>>>>> +    struct clk_init_data init;
>>>>>>>> +    struct pmc_clk_gate *gate;
>>>>>>>> +
>>>>>>>> +    gate = kzalloc(sizeof(*gate), GFP_KERNEL);
>>>>>>>> +    if (!gate)
>>>>>>>> +        return ERR_PTR(-ENOMEM);
>>>>>>>> +
>>>>>>>> +    init.name = name;
>>>>>>>> +    init.ops = &pmc_clk_gate_ops;
>>>>>>>> +    init.parent_names = &parent_name;
>>>>>>>> +    init.num_parents = 1;
>>>>>>>> +    init.flags = flags;
>>>>>>>> +
>>>>>>>> +    gate->hw.init = &init;
>>>>>>>> +    gate->offs = offset;
>>>>>>>> +    gate->shift = shift;
>>>>>>>> +
>>>>>>>> +    return clk_register(NULL, &gate->hw);
>>>>>>>> +}
>>>>>>>> +
>>>>>>>> +static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
>>>>>>>> +                     struct device_node *np)
>>>>>>>> +{
>>>>>>>> +    struct clk *clkmux, *clk, *parent;
>>>>>>>> +    struct clk_onecell_data *clk_data;
>>>>>>>> +    unsigned int num_clks;
>>>>>>>> +    int i, ret;
>>>>>>>> +
>>>>>>>> +    /* each pmc clock output has a mux and a gate */
>>>>>>>> +    num_clks = pmc->soc->num_pmc_clks * 2;
>>>>>>>> +
>>>>>>>> +    if (!num_clks)
>>>>>>>> +        return;
>>>>>>>> +
>>>>>>>> +    clk_data = kmalloc(sizeof(*clk_data), GFP_KERNEL);
>>>>>>>> +    if (!clk_data)
>>>>>>>> +        return;
>>>>>>>> +
>>>>>>>> +    clk_data->clks = kcalloc(TEGRA_PMC_CLK_MAX,
>>>>>>>> sizeof(*clk_data->clks),
>>>>>>>> +                 GFP_KERNEL);
>>>>>>>> +    if (!clk_data->clks)
>>>>>>>> +        goto free_clkdata;
>>>>>>>> +
>>>>>>>> +    clk_data->clk_num = num_clks;
>>>>>>>> +
>>>>>>>> +    for (i = 0; i < pmc->soc->num_pmc_clks; i++) {
>>>>>>>> +        struct pmc_clk_init_data *data;
>>>>>>>> +
>>>>>>>> +        data = pmc->soc->pmc_clks_data + i;
>>>>>>>> +
>>>>>>>> +        clkmux = tegra_pmc_clk_mux_register(data->mux_name,
>>>>>>>> +                            data->parents,
>>>>>>>> +                            data->num_parents,
>>>>>>>> + CLK_SET_RATE_NO_REPARENT |
>>>>>>>> +                            CLK_SET_RATE_PARENT,
>>>>>>>> +                            PMC_CLK_OUT_CNTRL,
>>>>>>>> +                            data->mux_shift, 3);
>>>>>>>> +        if (IS_ERR(clkmux))
>>>>>>>> +            goto free_clks;
>>>>>>>> +
>>>>>>>> +        clk_data->clks[data->mux_id] = clkmux;
>>>>>>>> +
>>>>>>>> +        clk = tegra_pmc_clk_gate_register(data->gate_name,
>>>>>>>> +                          data->mux_name,
>>>>>>>> +                          CLK_SET_RATE_PARENT,
>>>>>>>> +                          PMC_CLK_OUT_CNTRL,
>>>>>>>> +                          data->gate_shift);
>>>>>>>> +        if (IS_ERR(clk))
>>>>>>>> +            goto free_clks;
>>>>>>>> +
>>>>>>>> +        clk_data->clks[data->gate_id] = clk;
>>>>>>>> +
>>>>>>>> +        ret = clk_set_parent(clk, clkmux);
>>>>>>>> +        if (ret < 0) {
>>>>>>>> +            pr_err("failed to set parent of %s to %s\n",
>>>>>>>> +                   __func__, __clk_get_name(clk),
>>>>>>>> +                   __clk_get_name(clkmux));
>>>>>>>> +        }
>>>>>>>> +
>>>>>>>> +        clk_register_clkdev(clk, data->dev_name, 
>>>>>>>> data->gate_name);
>>>>>>>> +
>>>>>>>> +        /* configure initial clock parent and state */
>>>>>>>> +        parent = clk_get_sys(data->gate_name,
>>>>>>>> + data->parents[data->init_parent_index]);
>>> Couldn't the default parent be defined using "assigned clock" in a
>>> device-tree? Please see "Assigned clock parents and rates" in the doc.
>>>
>>> https://www.kernel.org/doc/Documentation/devicetree/bindings/clock/clock-bindings.txt 
>>>
>>>
>>> Then you could simply use of_clk_set_defaults(pmc->dev->of_node, true).
>>
>> Yes, of_clk_add_provider() does of_clk_set_defaults which sets based 
>> on assigned parents and clock rates.
>>
>> This need device tree to specify assigned clock parent properties. 
>> Will update device tree and remove init parent from the driver.
>>
> assigned-clock properties should be set in consumer node of these 
> clocks and currently these clocks are not used yet.
>
> So will just remove init parent from driver and when these clocks are 
> used device tree can be updated in corresponding consumer node with 
> these properties.
>
How about default ON/OFF init state for the clocks? I see assigned-clock 
properties for parent and rate only.

But based on existing clock-tegra-pmc driver, I see clk_out_1 is default 
enabled with extern1 parent for T30 thru T210 platforms.

Peter/Thierry, What was the reason we enable clk_out_1 right from the 
clock registration?

>>>
>>>>>>>> +        if (!IS_ERR(parent)) {
>>>>>>>> +            ret = clk_set_parent(clkmux, parent);
>>>>>>>> +            if (ret < 0) {
>>>>>>>> +                pr_err("failed to set parent of %s to %s\n",
>>>>>>>> +                       __func__, __clk_get_name(clkmux),
>>>>>>>> +                       __clk_get_name(parent));
>>>>>>>> +                WARN_ON(1);
>>>>>>>> +            }
>>>>>>>> +        }
>>>>>>>> +
>>>>>>>> +        if (data->init_state) {
>>>>>>>> +            if (clk_prepare_enable(clk)) {
>>>>>>>> +                pr_err("failed to enable %s\n", __func__,
>>>>>>>> +                       __clk_get_name(clk));
>>>>>>>> +                WARN_ON(1);
>>>>> Alternatively you could write it like this:
>>>>>
>>>>>      err = clk_prepare_enable(clk);
>>>>>
>>>>>      WARN_ON(err, "failed to enable %s: %d\n",
>>>>>          __clk_get_name(clk), err);
>>>>>
>>>>>>> Should be a bit better to move the WARN_ON to the end of errors
>>>>>>> handling
>>>>>>> in order to catch all possible errors:
>>>>>>>
>>>>>>> @@ -2510,6 +2510,7 @@ static void tegra_pmc_clock_register(struct
>>>>>>> tegra_pmc *pmc,
>>>>>>>            return;
>>>>>>>
>>>>>>>     free_clks:
>>>>>>> +       WARN_ON(1);
>>>>>>>            kfree(clk_data->clks);
>>>>>>>     free_clkdata:
>>>>>>>            kfree(clk_data);
>>>>>> Reason I had WARN_ON right during clk_set_parent failure is to 
>>>>>> have the
>>>>>> loop continue for subsequence pmc clocks registration instead of
>>>>>> terminating all pmc clocks registration.
>>>>> Ah, okay. Nevertheless this WARN_ON in the end shouldn't be the least
>>>>> (IMO).
>>>> Hi Dmitry, Just want to be clear on the above comment. Are you
>>>> suggesting to add additional WARN_ON at the end?
>>> Yes, it was my suggestion.
>>>
>>>> Thought WARN_ON right during corresponding clock failure with warn
>>>> message showing clock names will be clear and also other clocks still
>>>> should be registered.
>>>>
>>>> To add additional WARN_ON at the end need to track status of each 
>>>> clock
>>>> and use that to as warn condition.
>>> You could add a warning/error message to every point of failure.
>>>
>>> Primarily, it is important not to miss a error. Secondarily, it is
>>> important to make diagnostic message meaningful.
>>>
>>> Realistically, I doubt that this chunk of code will ever fail once 
>>> it is
>>> known to work well. So it will be nice to have a more detailed
>>> diagnostics (just in a case), but it shouldn't be a must.
>>
>> OK, Will add additional WARN message "failed registering PMC clocks" 
>> at the end.
>>

On 12/2/19 3:14 PM, Sowjanya Komatineni wrote:
>
> On 12/2/19 3:10 PM, Sowjanya Komatineni wrote:
>>
>> On 12/2/19 2:58 PM, Sowjanya Komatineni wrote:
>>>
>>> On 12/2/19 1:50 PM, Dmitry Osipenko wrote:
>>>> 02.12.2019 23:09, Sowjanya Komatineni пишет:
>>>>> On 11/28/19 5:25 AM, Dmitry Osipenko wrote:
>>>>>> 28.11.2019 01:57, Sowjanya Komatineni пишет:
>>>>>>> On 11/27/19 7:14 AM, Dmitry Osipenko wrote:
>>>>>>>> 27.11.2019 07:59, Sowjanya Komatineni пишет:
>>>>>>>>> Tegra210 and prior Tegra PMC has clk_out_1, clk_out_2, 
>>>>>>>>> clk_out_3 with
>>>>>>>>> mux and gate for each of these clocks.
>>>>>>>>>
>>>>>>>>> Currently these PMC clocks are registered by Tegra clock 
>>>>>>>>> driver using
>>>>>>>>> clk_register_mux and clk_register_gate by passing PMC base 
>>>>>>>>> address
>>>>>>>>> and register offsets and PMC programming for these clocks happens
>>>>>>>>> through direct PMC access by the clock driver.
>>>>>>>>>
>>>>>>>>> With this, when PMC is in secure mode any direct PMC access 
>>>>>>>>> from the
>>>>>>>>> non-secure world does not go through and these clocks will not be
>>>>>>>>> functional.
>>>>>>>>>
>>>>>>>>> This patch adds these clocks registration with PMC as a clock 
>>>>>>>>> provider
>>>>>>>>> for these clocks. clk_ops callback implementations for these 
>>>>>>>>> clocks
>>>>>>>>> uses tegra_pmc_readl and tegra_pmc_writel which supports PMC
>>>>>>>>> programming
>>>>>>>>> in secure mode and non-secure mode.
>>>>>>>>>
>>>>>>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>>>>>>> ---
>>>>>>>>>     drivers/soc/tegra/pmc.c | 330
>>>>>>>>> ++++++++++++++++++++++++++++++++++++++++++++++++
>>>>>>>>>     1 file changed, 330 insertions(+)
>>>>>>>>>
>>>>>>>>> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
>>>>>>>>> index ea0e11a09c12..a353f6d0a832 100644
>>>>>>>>> --- a/drivers/soc/tegra/pmc.c
>>>>>>>>> +++ b/drivers/soc/tegra/pmc.c
>>>>>>>>> @@ -13,6 +13,9 @@
>>>>>>>>>       #include <linux/arm-smccc.h>
>>>>>>>>>     #include <linux/clk.h>
>>>>>>>>> +#include <linux/clk-provider.h>
>>>>>>>>> +#include <linux/clkdev.h>
>>>>>>>>> +#include <linux/clk/clk-conf.h>
>>>>>>>>>     #include <linux/clk/tegra.h>
>>>>>>>>>     #include <linux/debugfs.h>
>>>>>>>>>     #include <linux/delay.h>
>>>>>>>>> @@ -48,6 +51,7 @@
>>>>>>>>>     #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
>>>>>>>>>     #include <dt-bindings/gpio/tegra186-gpio.h>
>>>>>>>>>     #include <dt-bindings/gpio/tegra194-gpio.h>
>>>>>>>>> +#include <dt-bindings/soc/tegra-pmc.h>
>>>>>>>>>       #define PMC_CNTRL            0x0
>>>>>>>>>     #define  PMC_CNTRL_INTR_POLARITY    BIT(17) /* inverts INTR
>>>>>>>>> polarity */
>>>>>>>>> @@ -100,6 +104,7 @@
>>>>>>>>>     #define PMC_WAKE2_STATUS        0x168
>>>>>>>>>     #define PMC_SW_WAKE2_STATUS        0x16c
>>>>>>>>>     +#define PMC_CLK_OUT_CNTRL        0x1a8
>>>>>>>>>     #define PMC_SENSOR_CTRL            0x1b0
>>>>>>>>>     #define  PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2)
>>>>>>>>>     #define  PMC_SENSOR_CTRL_ENABLE_RST    BIT(1)
>>>>>>>>> @@ -155,6 +160,91 @@
>>>>>>>>>     #define  TEGRA_SMC_PMC_READ    0xaa
>>>>>>>>>     #define  TEGRA_SMC_PMC_WRITE    0xbb
>>>>>>>>>     +struct pmc_clk_mux {
>>>>>>>>> +    struct clk_hw    hw;
>>>>>>>>> +    unsigned long    offs;
>>>>>>>>> +    u32        mask;
>>>>>>>>> +    u32        shift;
>>>>>>>>> +};
>>>>>>>>> +
>>>>>>>>> +#define to_pmc_clk_mux(_hw) container_of(_hw, struct 
>>>>>>>>> pmc_clk_mux, hw)
>>>>>>>>> +
>>>>>>>>> +struct pmc_clk_gate {
>>>>>>>>> +    struct clk_hw    hw;
>>>>>>>>> +    unsigned long    offs;
>>>>>>>>> +    u32        shift;
>>>>>>>>> +};
>>>>>>>>> +
>>>>>>>>> +#define to_pmc_clk_gate(_hw) container_of(_hw, struct
>>>>>>>>> pmc_clk_gate, hw)
>>>>>>>>> +
>>>>>>>>> +struct pmc_clk_init_data {
>>>>>>>>> +    char *mux_name;
>>>>>>>>> +    char *gate_name;
>>>>>>>>> +    const char **parents;
>>>>>>>>> +    int num_parents;
>>>>>>>>> +    int mux_id;
>>>>>>>>> +    int gate_id;
>>>>>>>>> +    char *dev_name;
>>>>>>>>> +    u8 mux_shift;
>>>>>>>>> +    u8 gate_shift;
>>>>>>>>> +    u8 init_parent_index;
>>>>>>>>> +    int init_state;
>>>>>>>>> +};
>>>>>>>>> +
>>>>>>>>> +static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2",
>>>>>>>>> +    "clk_m_div4", "extern1",
>>>>>>>>> +};
>>>>>>>>> +
>>>>>>>>> +static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2",
>>>>>>>>> +    "clk_m_div4", "extern2",
>>>>>>>>> +};
>>>>>>>>> +
>>>>>>>>> +static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2",
>>>>>>>>> +    "clk_m_div4", "extern3",
>>>>>>>>> +};
>>>>>>>>> +
>>>>>>>>> +static struct pmc_clk_init_data tegra_pmc_clks_data[] = {
>>>>>>>>> +    {
>>>>>>>>> +        .mux_name = "clk_out_1_mux",
>>>>>>>>> +        .gate_name = "clk_out_1",
>>>>>>>>> +        .parents = clk_out1_parents,
>>>>>>>>> +        .num_parents = ARRAY_SIZE(clk_out1_parents),
>>>>>>>>> +        .mux_id = TEGRA_PMC_CLK_OUT_1_MUX,
>>>>>>>>> +        .gate_id = TEGRA_PMC_CLK_OUT_1,
>>>>>>>>> +        .dev_name = "extern1",
>>>>>>>>> +        .mux_shift = 6,
>>>>>>>>> +        .gate_shift = 2,
>>>>>>>>> +        .init_parent_index = 3,
>>>>>>>>> +        .init_state = 1,
>>>>>>>>> +    },
>>>>>>>>> +    {
>>>>>>>>> +        .mux_name = "clk_out_2_mux",
>>>>>>>>> +        .gate_name = "clk_out_2",
>>>>>>>>> +        .parents = clk_out2_parents,
>>>>>>>>> +        .num_parents = ARRAY_SIZE(clk_out2_parents),
>>>>>>>>> +        .mux_id = TEGRA_PMC_CLK_OUT_2_MUX,
>>>>>>>>> +        .gate_id = TEGRA_PMC_CLK_OUT_2,
>>>>>>>>> +        .dev_name = "extern2",
>>>>>>>>> +        .mux_shift = 14,
>>>>>>>>> +        .gate_shift = 10,
>>>>>>>>> +        .init_parent_index = 0,
>>>>>>>>> +        .init_state = 0,
>>>>>>>>> +    },
>>>>>>>>> +    {
>>>>>>>>> +        .mux_name = "clk_out_3_mux",
>>>>>>>>> +        .gate_name = "clk_out_3",
>>>>>>>>> +        .parents = clk_out3_parents,
>>>>>>>>> +        .num_parents = ARRAY_SIZE(clk_out3_parents),
>>>>>>>>> +        .mux_id = TEGRA_PMC_CLK_OUT_3_MUX,
>>>>>>>>> +        .gate_id = TEGRA_PMC_CLK_OUT_3,
>>>>>>>>> +        .dev_name = "extern3",
>>>>>>>>> +        .mux_shift = 22,
>>>>>>>>> +        .gate_shift = 18,
>>>>>>>>> +        .init_parent_index = 0,
>>>>>>>>> +        .init_state = 0,
>>>>>>>>> +    },
>>>>>>>>> +};
>>>>>>>>> +
>>>>>>>>>     struct tegra_powergate {
>>>>>>>>>         struct generic_pm_domain genpd;
>>>>>>>>>         struct tegra_pmc *pmc;
>>>>>>>>> @@ -254,6 +344,9 @@ struct tegra_pmc_soc {
>>>>>>>>>          */
>>>>>>>>>         const struct tegra_wake_event *wake_events;
>>>>>>>>>         unsigned int num_wake_events;
>>>>>>>>> +
>>>>>>>>> +    struct pmc_clk_init_data *pmc_clks_data;
>>>>>>>>> +    unsigned int num_pmc_clks;
>>>>>>>>>     };
>>>>>>>>>       static const char * const tegra186_reset_sources[] = {
>>>>>>>>> @@ -2163,6 +2256,228 @@ static int tegra_pmc_clk_notify_cb(struct
>>>>>>>>> notifier_block *nb,
>>>>>>>>>         return NOTIFY_OK;
>>>>>>>>>     }
>>>>>>>>>     +static void pmc_clk_fence_udelay(u32 offset)
>>>>>>>>> +{
>>>>>>>>> +    tegra_pmc_readl(pmc, offset);
>>>>>>>>> +    /* pmc clk propagation delay 2 us */
>>>>>>>>> +    udelay(2);
>>>>>>>>> +}
>>>>>>>>> +
>>>>>>>>> +static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
>>>>>>>>> +{
>>>>>>>>> +    struct pmc_clk_mux *mux = to_pmc_clk_mux(hw);
>>>>>>>>> +    int num_parents = clk_hw_get_num_parents(hw);
>>>>>>>>> +    u32 val;
>>>>>>>>> +
>>>>>>>>> +    val = tegra_pmc_readl(pmc, mux->offs) >> mux->shift;
>>>>>>>>> +    val &= mux->mask;
>>>>>>>>> +
>>>>>>>>> +    if (val >= num_parents)
>>>>>>>>> +        return -EINVAL;
>>>>>>>>> +
>>>>>>>>> +    return val;
>>>>>>>>> +}
>>>>>>>>> +
>>>>>>>>> +static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
>>>>>>>>> +{
>>>>>>>>> +    struct pmc_clk_mux *mux = to_pmc_clk_mux(hw);
>>>>>>>>> +    u32 val;
>>>>>>>>> +
>>>>>>>>> +    val = tegra_pmc_readl(pmc, mux->offs);
>>>>>>>>> +    val &= ~(mux->mask << mux->shift);
>>>>>>>>> +    val |= index << mux->shift;
>>>>>>>>> +    tegra_pmc_writel(pmc, val, mux->offs);
>>>>>>>>> +    pmc_clk_fence_udelay(mux->offs);
>>>>>>>>> +
>>>>>>>>> +    return 0;
>>>>>>>>> +}
>>>>>>>>> +
>>>>>>>>> +static const struct clk_ops pmc_clk_mux_ops = {
>>>>>>>>> +    .get_parent = pmc_clk_mux_get_parent,
>>>>>>>>> +    .set_parent = pmc_clk_mux_set_parent,
>>>>>>>>> +    .determine_rate = __clk_mux_determine_rate,
>>>>>>>>> +};
>>>>>>>>> +
>>>>>>>>> +static struct clk *
>>>>>>>>> +tegra_pmc_clk_mux_register(const char *name, const char * const
>>>>>>>>> *parent_names,
>>>>>>>>> +               int num_parents, unsigned long flags,
>>>>>>>>> +               unsigned long offset, u32 shift, u32 mask)
>>>>>>>>> +{
>>>>>>>>> +    struct clk_init_data init;
>>>>>>>>> +    struct pmc_clk_mux *mux;
>>>>>>>>> +
>>>>>>>>> +    mux = kzalloc(sizeof(*mux), GFP_KERNEL);
>>>>>>>>> +    if (!mux)
>>>>>>>>> +        return ERR_PTR(-ENOMEM);
>>>>>>>>> +
>>>>>>>>> +    init.name = name;
>>>>>>>>> +    init.ops = &pmc_clk_mux_ops;
>>>>>>>>> +    init.parent_names = parent_names;
>>>>>>>>> +    init.num_parents = num_parents;
>>>>>>>>> +    init.flags = flags;
>>>>>>>>> +
>>>>>>>>> +    mux->hw.init = &init;
>>>>>>>>> +    mux->offs = offset;
>>>>>>>>> +    mux->mask = mask;
>>>>>>>>> +    mux->shift = shift;
>>>>>>>>> +
>>>>>>>>> +    return clk_register(NULL, &mux->hw);
>>>>>>>>> +}
>>>>>>>>> +
>>>>>>>>> +static int pmc_clk_is_enabled(struct clk_hw *hw)
>>>>>>>>> +{
>>>>>>>>> +    struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
>>>>>>>>> +
>>>>>>>>> +    return tegra_pmc_readl(pmc, gate->offs) & 
>>>>>>>>> BIT(gate->shift) ? 1
>>>>>>>>> : 0;
>>>>>>>>> +}
>>>>>>>>> +
>>>>>>>>> +static void pmc_clk_set_state(struct clk_hw *hw, int state)
>>>>>>>>> +{
>>>>>>>>> +    struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
>>>>>>>>> +    u32 val;
>>>>>>>>> +
>>>>>>>>> +    val = tegra_pmc_readl(pmc, gate->offs);
>>>>>>>>> +    val = state ? (val | BIT(gate->shift)) : (val &
>>>>>>>>> ~BIT(gate->shift));
>>>>>>>>> +    tegra_pmc_writel(pmc, val, gate->offs);
>>>>>>>>> +    pmc_clk_fence_udelay(gate->offs);
>>>>>>>>> +}
>>>>>>>>> +
>>>>>>>>> +static int pmc_clk_enable(struct clk_hw *hw)
>>>>>>>>> +{
>>>>>>>>> +    pmc_clk_set_state(hw, 1);
>>>>>>>>> +
>>>>>>>>> +    return 0;
>>>>>>>>> +}
>>>>>>>>> +
>>>>>>>>> +static void pmc_clk_disable(struct clk_hw *hw)
>>>>>>>>> +{
>>>>>>>>> +    pmc_clk_set_state(hw, 0);
>>>>>>>>> +}
>>>>>>>>> +
>>>>>>>>> +static const struct clk_ops pmc_clk_gate_ops = {
>>>>>>>>> +    .is_enabled = pmc_clk_is_enabled,
>>>>>>>>> +    .enable = pmc_clk_enable,
>>>>>>>>> +    .disable = pmc_clk_disable,
>>>>>>>>> +};
>>>>>>>>> +
>>>>>>>>> +static struct clk *
>>>>>>>>> +tegra_pmc_clk_gate_register(const char *name, const char
>>>>>>>>> *parent_name,
>>>>>>>>> +                unsigned long flags, unsigned long offset,
>>>>>>>>> +                u32 shift)
>>>>>>>>> +{
>>>>>>>>> +    struct clk_init_data init;
>>>>>>>>> +    struct pmc_clk_gate *gate;
>>>>>>>>> +
>>>>>>>>> +    gate = kzalloc(sizeof(*gate), GFP_KERNEL);
>>>>>>>>> +    if (!gate)
>>>>>>>>> +        return ERR_PTR(-ENOMEM);
>>>>>>>>> +
>>>>>>>>> +    init.name = name;
>>>>>>>>> +    init.ops = &pmc_clk_gate_ops;
>>>>>>>>> +    init.parent_names = &parent_name;
>>>>>>>>> +    init.num_parents = 1;
>>>>>>>>> +    init.flags = flags;
>>>>>>>>> +
>>>>>>>>> +    gate->hw.init = &init;
>>>>>>>>> +    gate->offs = offset;
>>>>>>>>> +    gate->shift = shift;
>>>>>>>>> +
>>>>>>>>> +    return clk_register(NULL, &gate->hw);
>>>>>>>>> +}
>>>>>>>>> +
>>>>>>>>> +static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
>>>>>>>>> +                     struct device_node *np)
>>>>>>>>> +{
>>>>>>>>> +    struct clk *clkmux, *clk, *parent;
>>>>>>>>> +    struct clk_onecell_data *clk_data;
>>>>>>>>> +    unsigned int num_clks;
>>>>>>>>> +    int i, ret;
>>>>>>>>> +
>>>>>>>>> +    /* each pmc clock output has a mux and a gate */
>>>>>>>>> +    num_clks = pmc->soc->num_pmc_clks * 2;
>>>>>>>>> +
>>>>>>>>> +    if (!num_clks)
>>>>>>>>> +        return;
>>>>>>>>> +
>>>>>>>>> +    clk_data = kmalloc(sizeof(*clk_data), GFP_KERNEL);
>>>>>>>>> +    if (!clk_data)
>>>>>>>>> +        return;
>>>>>>>>> +
>>>>>>>>> +    clk_data->clks = kcalloc(TEGRA_PMC_CLK_MAX,
>>>>>>>>> sizeof(*clk_data->clks),
>>>>>>>>> +                 GFP_KERNEL);
>>>>>>>>> +    if (!clk_data->clks)
>>>>>>>>> +        goto free_clkdata;
>>>>>>>>> +
>>>>>>>>> +    clk_data->clk_num = num_clks;
>>>>>>>>> +
>>>>>>>>> +    for (i = 0; i < pmc->soc->num_pmc_clks; i++) {
>>>>>>>>> +        struct pmc_clk_init_data *data;
>>>>>>>>> +
>>>>>>>>> +        data = pmc->soc->pmc_clks_data + i;
>>>>>>>>> +
>>>>>>>>> +        clkmux = tegra_pmc_clk_mux_register(data->mux_name,
>>>>>>>>> +                            data->parents,
>>>>>>>>> +                            data->num_parents,
>>>>>>>>> + CLK_SET_RATE_NO_REPARENT |
>>>>>>>>> +                            CLK_SET_RATE_PARENT,
>>>>>>>>> +                            PMC_CLK_OUT_CNTRL,
>>>>>>>>> +                            data->mux_shift, 3);
>>>>>>>>> +        if (IS_ERR(clkmux))
>>>>>>>>> +            goto free_clks;
>>>>>>>>> +
>>>>>>>>> +        clk_data->clks[data->mux_id] = clkmux;
>>>>>>>>> +
>>>>>>>>> +        clk = tegra_pmc_clk_gate_register(data->gate_name,
>>>>>>>>> +                          data->mux_name,
>>>>>>>>> +                          CLK_SET_RATE_PARENT,
>>>>>>>>> +                          PMC_CLK_OUT_CNTRL,
>>>>>>>>> +                          data->gate_shift);
>>>>>>>>> +        if (IS_ERR(clk))
>>>>>>>>> +            goto free_clks;
>>>>>>>>> +
>>>>>>>>> +        clk_data->clks[data->gate_id] = clk;
>>>>>>>>> +
>>>>>>>>> +        ret = clk_set_parent(clk, clkmux);
>>>>>>>>> +        if (ret < 0) {
>>>>>>>>> +            pr_err("failed to set parent of %s to %s\n",
>>>>>>>>> +                   __func__, __clk_get_name(clk),
>>>>>>>>> +                   __clk_get_name(clkmux));
>>>>>>>>> +        }
>>>>>>>>> +
>>>>>>>>> +        clk_register_clkdev(clk, data->dev_name, 
>>>>>>>>> data->gate_name);
>>>>>>>>> +
>>>>>>>>> +        /* configure initial clock parent and state */
>>>>>>>>> +        parent = clk_get_sys(data->gate_name,
>>>>>>>>> + data->parents[data->init_parent_index]);
>>>> Couldn't the default parent be defined using "assigned clock" in a
>>>> device-tree? Please see "Assigned clock parents and rates" in the doc.
>>>>
>>>> https://www.kernel.org/doc/Documentation/devicetree/bindings/clock/clock-bindings.txt 
>>>>
>>>>
>>>> Then you could simply use of_clk_set_defaults(pmc->dev->of_node, 
>>>> true).
>>>
>>> Yes, of_clk_add_provider() does of_clk_set_defaults which sets based 
>>> on assigned parents and clock rates.
>>>
>>> This need device tree to specify assigned clock parent properties. 
>>> Will update device tree and remove init parent from the driver.
>>>
>> assigned-clock properties should be set in consumer node of these 
>> clocks and currently these clocks are not used yet.
>>
>> So will just remove init parent from driver and when these clocks are 
>> used device tree can be updated in corresponding consumer node with 
>> these properties.
>>
> How about default ON/OFF init state for the clocks? I see 
> assigned-clock properties for parent and rate only.
>
> But based on existing clock-tegra-pmc driver, I see clk_out_1 is 
> default enabled with extern1 parent for T30 thru T210 platforms.
>
> Peter/Thierry, What was the reason we enable clk_out_1 right from the 
> clock registration?
>
clk_out_1 is for audio and its not required to be enabled during the 
boot and audio driver can enable/disable it.

same with blink 32khz which is used for WIFI. WIFI driver can 
enable/disable during power up/down sequence and technically as per 
design we dont need to have it always on right from the boot.

So can remove out clocks init states from driver once thierry also agree 
on this.

>>>>
>>>>>>>>> +        if (!IS_ERR(parent)) {
>>>>>>>>> +            ret = clk_set_parent(clkmux, parent);
>>>>>>>>> +            if (ret < 0) {
>>>>>>>>> +                pr_err("failed to set parent of %s to %s\n",
>>>>>>>>> +                       __func__, __clk_get_name(clkmux),
>>>>>>>>> +                       __clk_get_name(parent));
>>>>>>>>> +                WARN_ON(1);
>>>>>>>>> +            }
>>>>>>>>> +        }
>>>>>>>>> +
>>>>>>>>> +        if (data->init_state) {
>>>>>>>>> +            if (clk_prepare_enable(clk)) {
>>>>>>>>> +                pr_err("failed to enable %s\n", __func__,
>>>>>>>>> +                       __clk_get_name(clk));
>>>>>>>>> +                WARN_ON(1);
>>>>>> Alternatively you could write it like this:
>>>>>>
>>>>>>      err = clk_prepare_enable(clk);
>>>>>>
>>>>>>      WARN_ON(err, "failed to enable %s: %d\n",
>>>>>>          __clk_get_name(clk), err);
>>>>>>
>>>>>>>> Should be a bit better to move the WARN_ON to the end of errors
>>>>>>>> handling
>>>>>>>> in order to catch all possible errors:
>>>>>>>>
>>>>>>>> @@ -2510,6 +2510,7 @@ static void tegra_pmc_clock_register(struct
>>>>>>>> tegra_pmc *pmc,
>>>>>>>>            return;
>>>>>>>>
>>>>>>>>     free_clks:
>>>>>>>> +       WARN_ON(1);
>>>>>>>>            kfree(clk_data->clks);
>>>>>>>>     free_clkdata:
>>>>>>>>            kfree(clk_data);
>>>>>>> Reason I had WARN_ON right during clk_set_parent failure is to 
>>>>>>> have the
>>>>>>> loop continue for subsequence pmc clocks registration instead of
>>>>>>> terminating all pmc clocks registration.
>>>>>> Ah, okay. Nevertheless this WARN_ON in the end shouldn't be the 
>>>>>> least
>>>>>> (IMO).
>>>>> Hi Dmitry, Just want to be clear on the above comment. Are you
>>>>> suggesting to add additional WARN_ON at the end?
>>>> Yes, it was my suggestion.
>>>>
>>>>> Thought WARN_ON right during corresponding clock failure with warn
>>>>> message showing clock names will be clear and also other clocks still
>>>>> should be registered.
>>>>>
>>>>> To add additional WARN_ON at the end need to track status of each 
>>>>> clock
>>>>> and use that to as warn condition.
>>>> You could add a warning/error message to every point of failure.
>>>>
>>>> Primarily, it is important not to miss a error. Secondarily, it is
>>>> important to make diagnostic message meaningful.
>>>>
>>>> Realistically, I doubt that this chunk of code will ever fail once 
>>>> it is
>>>> known to work well. So it will be nice to have a more detailed
>>>> diagnostics (just in a case), but it shouldn't be a must.
>>>
>>> OK, Will add additional WARN message "failed registering PMC clocks" 
>>> at the end.
>>>

On 12/2/19 4:07 PM, Sowjanya Komatineni wrote:
>
> On 12/2/19 3:14 PM, Sowjanya Komatineni wrote:
>>
>> On 12/2/19 3:10 PM, Sowjanya Komatineni wrote:
>>>
>>> On 12/2/19 2:58 PM, Sowjanya Komatineni wrote:
>>>>
>>>> On 12/2/19 1:50 PM, Dmitry Osipenko wrote:
>>>>> 02.12.2019 23:09, Sowjanya Komatineni пишет:
>>>>>> On 11/28/19 5:25 AM, Dmitry Osipenko wrote:
>>>>>>> 28.11.2019 01:57, Sowjanya Komatineni пишет:
>>>>>>>> On 11/27/19 7:14 AM, Dmitry Osipenko wrote:
>>>>>>>>> 27.11.2019 07:59, Sowjanya Komatineni пишет:
>>>>>>>>>> Tegra210 and prior Tegra PMC has clk_out_1, clk_out_2, 
>>>>>>>>>> clk_out_3 with
>>>>>>>>>> mux and gate for each of these clocks.
>>>>>>>>>>
>>>>>>>>>> Currently these PMC clocks are registered by Tegra clock 
>>>>>>>>>> driver using
>>>>>>>>>> clk_register_mux and clk_register_gate by passing PMC base 
>>>>>>>>>> address
>>>>>>>>>> and register offsets and PMC programming for these clocks 
>>>>>>>>>> happens
>>>>>>>>>> through direct PMC access by the clock driver.
>>>>>>>>>>
>>>>>>>>>> With this, when PMC is in secure mode any direct PMC access 
>>>>>>>>>> from the
>>>>>>>>>> non-secure world does not go through and these clocks will 
>>>>>>>>>> not be
>>>>>>>>>> functional.
>>>>>>>>>>
>>>>>>>>>> This patch adds these clocks registration with PMC as a clock 
>>>>>>>>>> provider
>>>>>>>>>> for these clocks. clk_ops callback implementations for these 
>>>>>>>>>> clocks
>>>>>>>>>> uses tegra_pmc_readl and tegra_pmc_writel which supports PMC
>>>>>>>>>> programming
>>>>>>>>>> in secure mode and non-secure mode.
>>>>>>>>>>
>>>>>>>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>>>>>>>> ---
>>>>>>>>>>     drivers/soc/tegra/pmc.c | 330
>>>>>>>>>> ++++++++++++++++++++++++++++++++++++++++++++++++
>>>>>>>>>>     1 file changed, 330 insertions(+)
>>>>>>>>>>
>>>>>>>>>> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
>>>>>>>>>> index ea0e11a09c12..a353f6d0a832 100644
>>>>>>>>>> --- a/drivers/soc/tegra/pmc.c
>>>>>>>>>> +++ b/drivers/soc/tegra/pmc.c
>>>>>>>>>> @@ -13,6 +13,9 @@
>>>>>>>>>>       #include <linux/arm-smccc.h>
>>>>>>>>>>     #include <linux/clk.h>
>>>>>>>>>> +#include <linux/clk-provider.h>
>>>>>>>>>> +#include <linux/clkdev.h>
>>>>>>>>>> +#include <linux/clk/clk-conf.h>
>>>>>>>>>>     #include <linux/clk/tegra.h>
>>>>>>>>>>     #include <linux/debugfs.h>
>>>>>>>>>>     #include <linux/delay.h>
>>>>>>>>>> @@ -48,6 +51,7 @@
>>>>>>>>>>     #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
>>>>>>>>>>     #include <dt-bindings/gpio/tegra186-gpio.h>
>>>>>>>>>>     #include <dt-bindings/gpio/tegra194-gpio.h>
>>>>>>>>>> +#include <dt-bindings/soc/tegra-pmc.h>
>>>>>>>>>>       #define PMC_CNTRL            0x0
>>>>>>>>>>     #define  PMC_CNTRL_INTR_POLARITY    BIT(17) /* inverts INTR
>>>>>>>>>> polarity */
>>>>>>>>>> @@ -100,6 +104,7 @@
>>>>>>>>>>     #define PMC_WAKE2_STATUS        0x168
>>>>>>>>>>     #define PMC_SW_WAKE2_STATUS        0x16c
>>>>>>>>>>     +#define PMC_CLK_OUT_CNTRL        0x1a8
>>>>>>>>>>     #define PMC_SENSOR_CTRL            0x1b0
>>>>>>>>>>     #define  PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2)
>>>>>>>>>>     #define  PMC_SENSOR_CTRL_ENABLE_RST BIT(1)
>>>>>>>>>> @@ -155,6 +160,91 @@
>>>>>>>>>>     #define  TEGRA_SMC_PMC_READ    0xaa
>>>>>>>>>>     #define  TEGRA_SMC_PMC_WRITE    0xbb
>>>>>>>>>>     +struct pmc_clk_mux {
>>>>>>>>>> +    struct clk_hw    hw;
>>>>>>>>>> +    unsigned long    offs;
>>>>>>>>>> +    u32        mask;
>>>>>>>>>> +    u32        shift;
>>>>>>>>>> +};
>>>>>>>>>> +
>>>>>>>>>> +#define to_pmc_clk_mux(_hw) container_of(_hw, struct 
>>>>>>>>>> pmc_clk_mux, hw)
>>>>>>>>>> +
>>>>>>>>>> +struct pmc_clk_gate {
>>>>>>>>>> +    struct clk_hw    hw;
>>>>>>>>>> +    unsigned long    offs;
>>>>>>>>>> +    u32        shift;
>>>>>>>>>> +};
>>>>>>>>>> +
>>>>>>>>>> +#define to_pmc_clk_gate(_hw) container_of(_hw, struct
>>>>>>>>>> pmc_clk_gate, hw)
>>>>>>>>>> +
>>>>>>>>>> +struct pmc_clk_init_data {
>>>>>>>>>> +    char *mux_name;
>>>>>>>>>> +    char *gate_name;
>>>>>>>>>> +    const char **parents;
>>>>>>>>>> +    int num_parents;
>>>>>>>>>> +    int mux_id;
>>>>>>>>>> +    int gate_id;
>>>>>>>>>> +    char *dev_name;
>>>>>>>>>> +    u8 mux_shift;
>>>>>>>>>> +    u8 gate_shift;
>>>>>>>>>> +    u8 init_parent_index;
>>>>>>>>>> +    int init_state;
>>>>>>>>>> +};
>>>>>>>>>> +
>>>>>>>>>> +static const char *clk_out1_parents[] = { "clk_m", 
>>>>>>>>>> "clk_m_div2",
>>>>>>>>>> +    "clk_m_div4", "extern1",
>>>>>>>>>> +};
>>>>>>>>>> +
>>>>>>>>>> +static const char *clk_out2_parents[] = { "clk_m", 
>>>>>>>>>> "clk_m_div2",
>>>>>>>>>> +    "clk_m_div4", "extern2",
>>>>>>>>>> +};
>>>>>>>>>> +
>>>>>>>>>> +static const char *clk_out3_parents[] = { "clk_m", 
>>>>>>>>>> "clk_m_div2",
>>>>>>>>>> +    "clk_m_div4", "extern3",
>>>>>>>>>> +};
>>>>>>>>>> +
>>>>>>>>>> +static struct pmc_clk_init_data tegra_pmc_clks_data[] = {
>>>>>>>>>> +    {
>>>>>>>>>> +        .mux_name = "clk_out_1_mux",
>>>>>>>>>> +        .gate_name = "clk_out_1",
>>>>>>>>>> +        .parents = clk_out1_parents,
>>>>>>>>>> +        .num_parents = ARRAY_SIZE(clk_out1_parents),
>>>>>>>>>> +        .mux_id = TEGRA_PMC_CLK_OUT_1_MUX,
>>>>>>>>>> +        .gate_id = TEGRA_PMC_CLK_OUT_1,
>>>>>>>>>> +        .dev_name = "extern1",
>>>>>>>>>> +        .mux_shift = 6,
>>>>>>>>>> +        .gate_shift = 2,
>>>>>>>>>> +        .init_parent_index = 3,
>>>>>>>>>> +        .init_state = 1,
>>>>>>>>>> +    },
>>>>>>>>>> +    {
>>>>>>>>>> +        .mux_name = "clk_out_2_mux",
>>>>>>>>>> +        .gate_name = "clk_out_2",
>>>>>>>>>> +        .parents = clk_out2_parents,
>>>>>>>>>> +        .num_parents = ARRAY_SIZE(clk_out2_parents),
>>>>>>>>>> +        .mux_id = TEGRA_PMC_CLK_OUT_2_MUX,
>>>>>>>>>> +        .gate_id = TEGRA_PMC_CLK_OUT_2,
>>>>>>>>>> +        .dev_name = "extern2",
>>>>>>>>>> +        .mux_shift = 14,
>>>>>>>>>> +        .gate_shift = 10,
>>>>>>>>>> +        .init_parent_index = 0,
>>>>>>>>>> +        .init_state = 0,
>>>>>>>>>> +    },
>>>>>>>>>> +    {
>>>>>>>>>> +        .mux_name = "clk_out_3_mux",
>>>>>>>>>> +        .gate_name = "clk_out_3",
>>>>>>>>>> +        .parents = clk_out3_parents,
>>>>>>>>>> +        .num_parents = ARRAY_SIZE(clk_out3_parents),
>>>>>>>>>> +        .mux_id = TEGRA_PMC_CLK_OUT_3_MUX,
>>>>>>>>>> +        .gate_id = TEGRA_PMC_CLK_OUT_3,
>>>>>>>>>> +        .dev_name = "extern3",
>>>>>>>>>> +        .mux_shift = 22,
>>>>>>>>>> +        .gate_shift = 18,
>>>>>>>>>> +        .init_parent_index = 0,
>>>>>>>>>> +        .init_state = 0,
>>>>>>>>>> +    },
>>>>>>>>>> +};
>>>>>>>>>> +
>>>>>>>>>>     struct tegra_powergate {
>>>>>>>>>>         struct generic_pm_domain genpd;
>>>>>>>>>>         struct tegra_pmc *pmc;
>>>>>>>>>> @@ -254,6 +344,9 @@ struct tegra_pmc_soc {
>>>>>>>>>>          */
>>>>>>>>>>         const struct tegra_wake_event *wake_events;
>>>>>>>>>>         unsigned int num_wake_events;
>>>>>>>>>> +
>>>>>>>>>> +    struct pmc_clk_init_data *pmc_clks_data;
>>>>>>>>>> +    unsigned int num_pmc_clks;
>>>>>>>>>>     };
>>>>>>>>>>       static const char * const tegra186_reset_sources[] = {
>>>>>>>>>> @@ -2163,6 +2256,228 @@ static int 
>>>>>>>>>> tegra_pmc_clk_notify_cb(struct
>>>>>>>>>> notifier_block *nb,
>>>>>>>>>>         return NOTIFY_OK;
>>>>>>>>>>     }
>>>>>>>>>>     +static void pmc_clk_fence_udelay(u32 offset)
>>>>>>>>>> +{
>>>>>>>>>> +    tegra_pmc_readl(pmc, offset);
>>>>>>>>>> +    /* pmc clk propagation delay 2 us */
>>>>>>>>>> +    udelay(2);
>>>>>>>>>> +}
>>>>>>>>>> +
>>>>>>>>>> +static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
>>>>>>>>>> +{
>>>>>>>>>> +    struct pmc_clk_mux *mux = to_pmc_clk_mux(hw);
>>>>>>>>>> +    int num_parents = clk_hw_get_num_parents(hw);
>>>>>>>>>> +    u32 val;
>>>>>>>>>> +
>>>>>>>>>> +    val = tegra_pmc_readl(pmc, mux->offs) >> mux->shift;
>>>>>>>>>> +    val &= mux->mask;
>>>>>>>>>> +
>>>>>>>>>> +    if (val >= num_parents)
>>>>>>>>>> +        return -EINVAL;
>>>>>>>>>> +
>>>>>>>>>> +    return val;
>>>>>>>>>> +}
>>>>>>>>>> +
>>>>>>>>>> +static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
>>>>>>>>>> +{
>>>>>>>>>> +    struct pmc_clk_mux *mux = to_pmc_clk_mux(hw);
>>>>>>>>>> +    u32 val;
>>>>>>>>>> +
>>>>>>>>>> +    val = tegra_pmc_readl(pmc, mux->offs);
>>>>>>>>>> +    val &= ~(mux->mask << mux->shift);
>>>>>>>>>> +    val |= index << mux->shift;
>>>>>>>>>> +    tegra_pmc_writel(pmc, val, mux->offs);
>>>>>>>>>> +    pmc_clk_fence_udelay(mux->offs);
>>>>>>>>>> +
>>>>>>>>>> +    return 0;
>>>>>>>>>> +}
>>>>>>>>>> +
>>>>>>>>>> +static const struct clk_ops pmc_clk_mux_ops = {
>>>>>>>>>> +    .get_parent = pmc_clk_mux_get_parent,
>>>>>>>>>> +    .set_parent = pmc_clk_mux_set_parent,
>>>>>>>>>> +    .determine_rate = __clk_mux_determine_rate,
>>>>>>>>>> +};
>>>>>>>>>> +
>>>>>>>>>> +static struct clk *
>>>>>>>>>> +tegra_pmc_clk_mux_register(const char *name, const char * const
>>>>>>>>>> *parent_names,
>>>>>>>>>> +               int num_parents, unsigned long flags,
>>>>>>>>>> +               unsigned long offset, u32 shift, u32 mask)
>>>>>>>>>> +{
>>>>>>>>>> +    struct clk_init_data init;
>>>>>>>>>> +    struct pmc_clk_mux *mux;
>>>>>>>>>> +
>>>>>>>>>> +    mux = kzalloc(sizeof(*mux), GFP_KERNEL);
>>>>>>>>>> +    if (!mux)
>>>>>>>>>> +        return ERR_PTR(-ENOMEM);
>>>>>>>>>> +
>>>>>>>>>> +    init.name = name;
>>>>>>>>>> +    init.ops = &pmc_clk_mux_ops;
>>>>>>>>>> +    init.parent_names = parent_names;
>>>>>>>>>> +    init.num_parents = num_parents;
>>>>>>>>>> +    init.flags = flags;
>>>>>>>>>> +
>>>>>>>>>> +    mux->hw.init = &init;
>>>>>>>>>> +    mux->offs = offset;
>>>>>>>>>> +    mux->mask = mask;
>>>>>>>>>> +    mux->shift = shift;
>>>>>>>>>> +
>>>>>>>>>> +    return clk_register(NULL, &mux->hw);
>>>>>>>>>> +}
>>>>>>>>>> +
>>>>>>>>>> +static int pmc_clk_is_enabled(struct clk_hw *hw)
>>>>>>>>>> +{
>>>>>>>>>> +    struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
>>>>>>>>>> +
>>>>>>>>>> +    return tegra_pmc_readl(pmc, gate->offs) & 
>>>>>>>>>> BIT(gate->shift) ? 1
>>>>>>>>>> : 0;
>>>>>>>>>> +}
>>>>>>>>>> +
>>>>>>>>>> +static void pmc_clk_set_state(struct clk_hw *hw, int state)
>>>>>>>>>> +{
>>>>>>>>>> +    struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
>>>>>>>>>> +    u32 val;
>>>>>>>>>> +
>>>>>>>>>> +    val = tegra_pmc_readl(pmc, gate->offs);
>>>>>>>>>> +    val = state ? (val | BIT(gate->shift)) : (val &
>>>>>>>>>> ~BIT(gate->shift));
>>>>>>>>>> +    tegra_pmc_writel(pmc, val, gate->offs);
>>>>>>>>>> +    pmc_clk_fence_udelay(gate->offs);
>>>>>>>>>> +}
>>>>>>>>>> +
>>>>>>>>>> +static int pmc_clk_enable(struct clk_hw *hw)
>>>>>>>>>> +{
>>>>>>>>>> +    pmc_clk_set_state(hw, 1);
>>>>>>>>>> +
>>>>>>>>>> +    return 0;
>>>>>>>>>> +}
>>>>>>>>>> +
>>>>>>>>>> +static void pmc_clk_disable(struct clk_hw *hw)
>>>>>>>>>> +{
>>>>>>>>>> +    pmc_clk_set_state(hw, 0);
>>>>>>>>>> +}
>>>>>>>>>> +
>>>>>>>>>> +static const struct clk_ops pmc_clk_gate_ops = {
>>>>>>>>>> +    .is_enabled = pmc_clk_is_enabled,
>>>>>>>>>> +    .enable = pmc_clk_enable,
>>>>>>>>>> +    .disable = pmc_clk_disable,
>>>>>>>>>> +};
>>>>>>>>>> +
>>>>>>>>>> +static struct clk *
>>>>>>>>>> +tegra_pmc_clk_gate_register(const char *name, const char
>>>>>>>>>> *parent_name,
>>>>>>>>>> +                unsigned long flags, unsigned long offset,
>>>>>>>>>> +                u32 shift)
>>>>>>>>>> +{
>>>>>>>>>> +    struct clk_init_data init;
>>>>>>>>>> +    struct pmc_clk_gate *gate;
>>>>>>>>>> +
>>>>>>>>>> +    gate = kzalloc(sizeof(*gate), GFP_KERNEL);
>>>>>>>>>> +    if (!gate)
>>>>>>>>>> +        return ERR_PTR(-ENOMEM);
>>>>>>>>>> +
>>>>>>>>>> +    init.name = name;
>>>>>>>>>> +    init.ops = &pmc_clk_gate_ops;
>>>>>>>>>> +    init.parent_names = &parent_name;
>>>>>>>>>> +    init.num_parents = 1;
>>>>>>>>>> +    init.flags = flags;
>>>>>>>>>> +
>>>>>>>>>> +    gate->hw.init = &init;
>>>>>>>>>> +    gate->offs = offset;
>>>>>>>>>> +    gate->shift = shift;
>>>>>>>>>> +
>>>>>>>>>> +    return clk_register(NULL, &gate->hw);
>>>>>>>>>> +}
>>>>>>>>>> +
>>>>>>>>>> +static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
>>>>>>>>>> +                     struct device_node *np)
>>>>>>>>>> +{
>>>>>>>>>> +    struct clk *clkmux, *clk, *parent;
>>>>>>>>>> +    struct clk_onecell_data *clk_data;
>>>>>>>>>> +    unsigned int num_clks;
>>>>>>>>>> +    int i, ret;
>>>>>>>>>> +
>>>>>>>>>> +    /* each pmc clock output has a mux and a gate */
>>>>>>>>>> +    num_clks = pmc->soc->num_pmc_clks * 2;
>>>>>>>>>> +
>>>>>>>>>> +    if (!num_clks)
>>>>>>>>>> +        return;
>>>>>>>>>> +
>>>>>>>>>> +    clk_data = kmalloc(sizeof(*clk_data), GFP_KERNEL);
>>>>>>>>>> +    if (!clk_data)
>>>>>>>>>> +        return;
>>>>>>>>>> +
>>>>>>>>>> +    clk_data->clks = kcalloc(TEGRA_PMC_CLK_MAX,
>>>>>>>>>> sizeof(*clk_data->clks),
>>>>>>>>>> +                 GFP_KERNEL);
>>>>>>>>>> +    if (!clk_data->clks)
>>>>>>>>>> +        goto free_clkdata;
>>>>>>>>>> +
>>>>>>>>>> +    clk_data->clk_num = num_clks;
>>>>>>>>>> +
>>>>>>>>>> +    for (i = 0; i < pmc->soc->num_pmc_clks; i++) {
>>>>>>>>>> +        struct pmc_clk_init_data *data;
>>>>>>>>>> +
>>>>>>>>>> +        data = pmc->soc->pmc_clks_data + i;
>>>>>>>>>> +
>>>>>>>>>> +        clkmux = tegra_pmc_clk_mux_register(data->mux_name,
>>>>>>>>>> +                            data->parents,
>>>>>>>>>> + data->num_parents,
>>>>>>>>>> + CLK_SET_RATE_NO_REPARENT |
>>>>>>>>>> + CLK_SET_RATE_PARENT,
>>>>>>>>>> +                            PMC_CLK_OUT_CNTRL,
>>>>>>>>>> +                            data->mux_shift, 3);
>>>>>>>>>> +        if (IS_ERR(clkmux))
>>>>>>>>>> +            goto free_clks;
>>>>>>>>>> +
>>>>>>>>>> +        clk_data->clks[data->mux_id] = clkmux;
>>>>>>>>>> +
>>>>>>>>>> +        clk = tegra_pmc_clk_gate_register(data->gate_name,
>>>>>>>>>> +                          data->mux_name,
>>>>>>>>>> +                          CLK_SET_RATE_PARENT,
>>>>>>>>>> +                          PMC_CLK_OUT_CNTRL,
>>>>>>>>>> +                          data->gate_shift);
>>>>>>>>>> +        if (IS_ERR(clk))
>>>>>>>>>> +            goto free_clks;
>>>>>>>>>> +
>>>>>>>>>> +        clk_data->clks[data->gate_id] = clk;
>>>>>>>>>> +
>>>>>>>>>> +        ret = clk_set_parent(clk, clkmux);
>>>>>>>>>> +        if (ret < 0) {
>>>>>>>>>> +            pr_err("failed to set parent of %s to %s\n",
>>>>>>>>>> +                   __func__, __clk_get_name(clk),
>>>>>>>>>> +                   __clk_get_name(clkmux));
>>>>>>>>>> +        }
>>>>>>>>>> +
>>>>>>>>>> +        clk_register_clkdev(clk, data->dev_name, 
>>>>>>>>>> data->gate_name);
>>>>>>>>>> +
>>>>>>>>>> +        /* configure initial clock parent and state */
>>>>>>>>>> +        parent = clk_get_sys(data->gate_name,
>>>>>>>>>> + data->parents[data->init_parent_index]);
>>>>> Couldn't the default parent be defined using "assigned clock" in a
>>>>> device-tree? Please see "Assigned clock parents and rates" in the 
>>>>> doc.
>>>>>
>>>>> https://www.kernel.org/doc/Documentation/devicetree/bindings/clock/clock-bindings.txt 
>>>>>
>>>>>
>>>>> Then you could simply use of_clk_set_defaults(pmc->dev->of_node, 
>>>>> true).
>>>>
>>>> Yes, of_clk_add_provider() does of_clk_set_defaults which sets 
>>>> based on assigned parents and clock rates.
>>>>
>>>> This need device tree to specify assigned clock parent properties. 
>>>> Will update device tree and remove init parent from the driver.
>>>>
>>> assigned-clock properties should be set in consumer node of these 
>>> clocks and currently these clocks are not used yet.
>>>
>>> So will just remove init parent from driver and when these clocks 
>>> are used device tree can be updated in corresponding consumer node 
>>> with these properties.
>>>
>> How about default ON/OFF init state for the clocks? I see 
>> assigned-clock properties for parent and rate only.
>>
>> But based on existing clock-tegra-pmc driver, I see clk_out_1 is 
>> default enabled with extern1 parent for T30 thru T210 platforms.
>>
>> Peter/Thierry, What was the reason we enable clk_out_1 right from the 
>> clock registration?
>>
> clk_out_1 is for audio and its not required to be enabled during the 
> boot and audio driver can enable/disable it.
>
> same with blink 32khz which is used for WIFI. WIFI driver can 
> enable/disable during power up/down sequence and technically as per 
> design we dont need to have it always on right from the boot.
>
> So can remove out clocks init states from driver once thierry also 
> agree on this.
>
Hi Dmitry,

Looking at audio driver, it doesn't take care of mclk which is from 
clk_out_1 and expects mclk to be always on.

So probably we should have this init state enables in pmc driver for 
32Khz and clk_out's to not break existing functionality.

Regarding using assigned-clock properties for init parent and removing 
init parent from driver, it also needs consumer node in device tree to 
be updated to specify assigned-clock properties for default/init parent.

This breaks device tree ABI as prior Tegra210 supports audio driver.


>>>>>>>>>> +        if (!IS_ERR(parent)) {
>>>>>>>>>> +            ret = clk_set_parent(clkmux, parent);
>>>>>>>>>> +            if (ret < 0) {
>>>>>>>>>> +                pr_err("failed to set parent of %s to %s\n",
>>>>>>>>>> +                       __func__, __clk_get_name(clkmux),
>>>>>>>>>> +                       __clk_get_name(parent));
>>>>>>>>>> +                WARN_ON(1);
>>>>>>>>>> +            }
>>>>>>>>>> +        }
>>>>>>>>>> +
>>>>>>>>>> +        if (data->init_state) {
>>>>>>>>>> +            if (clk_prepare_enable(clk)) {
>>>>>>>>>> +                pr_err("failed to enable %s\n", __func__,
>>>>>>>>>> +                       __clk_get_name(clk));
>>>>>>>>>> +                WARN_ON(1);
>>>>>>> Alternatively you could write it like this:
>>>>>>>
>>>>>>>      err = clk_prepare_enable(clk);
>>>>>>>
>>>>>>>      WARN_ON(err, "failed to enable %s: %d\n",
>>>>>>>          __clk_get_name(clk), err);
>>>>>>>
>>>>>>>>> Should be a bit better to move the WARN_ON to the end of errors
>>>>>>>>> handling
>>>>>>>>> in order to catch all possible errors:
>>>>>>>>>
>>>>>>>>> @@ -2510,6 +2510,7 @@ static void tegra_pmc_clock_register(struct
>>>>>>>>> tegra_pmc *pmc,
>>>>>>>>>            return;
>>>>>>>>>
>>>>>>>>>     free_clks:
>>>>>>>>> +       WARN_ON(1);
>>>>>>>>>            kfree(clk_data->clks);
>>>>>>>>>     free_clkdata:
>>>>>>>>>            kfree(clk_data);
>>>>>>>> Reason I had WARN_ON right during clk_set_parent failure is to 
>>>>>>>> have the
>>>>>>>> loop continue for subsequence pmc clocks registration instead of
>>>>>>>> terminating all pmc clocks registration.
>>>>>>> Ah, okay. Nevertheless this WARN_ON in the end shouldn't be the 
>>>>>>> least
>>>>>>> (IMO).
>>>>>> Hi Dmitry, Just want to be clear on the above comment. Are you
>>>>>> suggesting to add additional WARN_ON at the end?
>>>>> Yes, it was my suggestion.
>>>>>
>>>>>> Thought WARN_ON right during corresponding clock failure with warn
>>>>>> message showing clock names will be clear and also other clocks 
>>>>>> still
>>>>>> should be registered.
>>>>>>
>>>>>> To add additional WARN_ON at the end need to track status of each 
>>>>>> clock
>>>>>> and use that to as warn condition.
>>>>> You could add a warning/error message to every point of failure.
>>>>>
>>>>> Primarily, it is important not to miss a error. Secondarily, it is
>>>>> important to make diagnostic message meaningful.
>>>>>
>>>>> Realistically, I doubt that this chunk of code will ever fail once 
>>>>> it is
>>>>> known to work well. So it will be nice to have a more detailed
>>>>> diagnostics (just in a case), but it shouldn't be a must.
>>>>
>>>> OK, Will add additional WARN message "failed registering PMC 
>>>> clocks" at the end.
>>>>

03.12.2019 19:45, Sowjanya Komatineni пишет:
> 
> On 12/2/19 4:07 PM, Sowjanya Komatineni wrote:
>>
>> On 12/2/19 3:14 PM, Sowjanya Komatineni wrote:
>>>
>>> On 12/2/19 3:10 PM, Sowjanya Komatineni wrote:
>>>>
>>>> On 12/2/19 2:58 PM, Sowjanya Komatineni wrote:
>>>>>
>>>>> On 12/2/19 1:50 PM, Dmitry Osipenko wrote:
>>>>>> 02.12.2019 23:09, Sowjanya Komatineni пишет:
>>>>>>> On 11/28/19 5:25 AM, Dmitry Osipenko wrote:
>>>>>>>> 28.11.2019 01:57, Sowjanya Komatineni пишет:
>>>>>>>>> On 11/27/19 7:14 AM, Dmitry Osipenko wrote:
>>>>>>>>>> 27.11.2019 07:59, Sowjanya Komatineni пишет:
>>>>>>>>>>> Tegra210 and prior Tegra PMC has clk_out_1, clk_out_2,
>>>>>>>>>>> clk_out_3 with
>>>>>>>>>>> mux and gate for each of these clocks.
>>>>>>>>>>>
>>>>>>>>>>> Currently these PMC clocks are registered by Tegra clock
>>>>>>>>>>> driver using
>>>>>>>>>>> clk_register_mux and clk_register_gate by passing PMC base
>>>>>>>>>>> address
>>>>>>>>>>> and register offsets and PMC programming for these clocks
>>>>>>>>>>> happens
>>>>>>>>>>> through direct PMC access by the clock driver.
>>>>>>>>>>>
>>>>>>>>>>> With this, when PMC is in secure mode any direct PMC access
>>>>>>>>>>> from the
>>>>>>>>>>> non-secure world does not go through and these clocks will
>>>>>>>>>>> not be
>>>>>>>>>>> functional.
>>>>>>>>>>>
>>>>>>>>>>> This patch adds these clocks registration with PMC as a clock
>>>>>>>>>>> provider
>>>>>>>>>>> for these clocks. clk_ops callback implementations for these
>>>>>>>>>>> clocks
>>>>>>>>>>> uses tegra_pmc_readl and tegra_pmc_writel which supports PMC
>>>>>>>>>>> programming
>>>>>>>>>>> in secure mode and non-secure mode.
>>>>>>>>>>>
>>>>>>>>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>>>>>>>>> ---
>>>>>>>>>>>     drivers/soc/tegra/pmc.c | 330
>>>>>>>>>>> ++++++++++++++++++++++++++++++++++++++++++++++++
>>>>>>>>>>>     1 file changed, 330 insertions(+)
>>>>>>>>>>>
>>>>>>>>>>> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
>>>>>>>>>>> index ea0e11a09c12..a353f6d0a832 100644
>>>>>>>>>>> --- a/drivers/soc/tegra/pmc.c
>>>>>>>>>>> +++ b/drivers/soc/tegra/pmc.c
>>>>>>>>>>> @@ -13,6 +13,9 @@
>>>>>>>>>>>       #include <linux/arm-smccc.h>
>>>>>>>>>>>     #include <linux/clk.h>
>>>>>>>>>>> +#include <linux/clk-provider.h>
>>>>>>>>>>> +#include <linux/clkdev.h>
>>>>>>>>>>> +#include <linux/clk/clk-conf.h>
>>>>>>>>>>>     #include <linux/clk/tegra.h>
>>>>>>>>>>>     #include <linux/debugfs.h>
>>>>>>>>>>>     #include <linux/delay.h>
>>>>>>>>>>> @@ -48,6 +51,7 @@
>>>>>>>>>>>     #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
>>>>>>>>>>>     #include <dt-bindings/gpio/tegra186-gpio.h>
>>>>>>>>>>>     #include <dt-bindings/gpio/tegra194-gpio.h>
>>>>>>>>>>> +#include <dt-bindings/soc/tegra-pmc.h>
>>>>>>>>>>>       #define PMC_CNTRL            0x0
>>>>>>>>>>>     #define  PMC_CNTRL_INTR_POLARITY    BIT(17) /* inverts INTR
>>>>>>>>>>> polarity */
>>>>>>>>>>> @@ -100,6 +104,7 @@
>>>>>>>>>>>     #define PMC_WAKE2_STATUS        0x168
>>>>>>>>>>>     #define PMC_SW_WAKE2_STATUS        0x16c
>>>>>>>>>>>     +#define PMC_CLK_OUT_CNTRL        0x1a8
>>>>>>>>>>>     #define PMC_SENSOR_CTRL            0x1b0
>>>>>>>>>>>     #define  PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2)
>>>>>>>>>>>     #define  PMC_SENSOR_CTRL_ENABLE_RST BIT(1)
>>>>>>>>>>> @@ -155,6 +160,91 @@
>>>>>>>>>>>     #define  TEGRA_SMC_PMC_READ    0xaa
>>>>>>>>>>>     #define  TEGRA_SMC_PMC_WRITE    0xbb
>>>>>>>>>>>     +struct pmc_clk_mux {
>>>>>>>>>>> +    struct clk_hw    hw;
>>>>>>>>>>> +    unsigned long    offs;
>>>>>>>>>>> +    u32        mask;
>>>>>>>>>>> +    u32        shift;
>>>>>>>>>>> +};
>>>>>>>>>>> +
>>>>>>>>>>> +#define to_pmc_clk_mux(_hw) container_of(_hw, struct
>>>>>>>>>>> pmc_clk_mux, hw)
>>>>>>>>>>> +
>>>>>>>>>>> +struct pmc_clk_gate {
>>>>>>>>>>> +    struct clk_hw    hw;
>>>>>>>>>>> +    unsigned long    offs;
>>>>>>>>>>> +    u32        shift;
>>>>>>>>>>> +};
>>>>>>>>>>> +
>>>>>>>>>>> +#define to_pmc_clk_gate(_hw) container_of(_hw, struct
>>>>>>>>>>> pmc_clk_gate, hw)
>>>>>>>>>>> +
>>>>>>>>>>> +struct pmc_clk_init_data {
>>>>>>>>>>> +    char *mux_name;
>>>>>>>>>>> +    char *gate_name;
>>>>>>>>>>> +    const char **parents;
>>>>>>>>>>> +    int num_parents;
>>>>>>>>>>> +    int mux_id;
>>>>>>>>>>> +    int gate_id;
>>>>>>>>>>> +    char *dev_name;
>>>>>>>>>>> +    u8 mux_shift;
>>>>>>>>>>> +    u8 gate_shift;
>>>>>>>>>>> +    u8 init_parent_index;
>>>>>>>>>>> +    int init_state;
>>>>>>>>>>> +};
>>>>>>>>>>> +
>>>>>>>>>>> +static const char *clk_out1_parents[] = { "clk_m",
>>>>>>>>>>> "clk_m_div2",
>>>>>>>>>>> +    "clk_m_div4", "extern1",
>>>>>>>>>>> +};
>>>>>>>>>>> +
>>>>>>>>>>> +static const char *clk_out2_parents[] = { "clk_m",
>>>>>>>>>>> "clk_m_div2",
>>>>>>>>>>> +    "clk_m_div4", "extern2",
>>>>>>>>>>> +};
>>>>>>>>>>> +
>>>>>>>>>>> +static const char *clk_out3_parents[] = { "clk_m",
>>>>>>>>>>> "clk_m_div2",
>>>>>>>>>>> +    "clk_m_div4", "extern3",
>>>>>>>>>>> +};
>>>>>>>>>>> +
>>>>>>>>>>> +static struct pmc_clk_init_data tegra_pmc_clks_data[] = {
>>>>>>>>>>> +    {
>>>>>>>>>>> +        .mux_name = "clk_out_1_mux",
>>>>>>>>>>> +        .gate_name = "clk_out_1",
>>>>>>>>>>> +        .parents = clk_out1_parents,
>>>>>>>>>>> +        .num_parents = ARRAY_SIZE(clk_out1_parents),
>>>>>>>>>>> +        .mux_id = TEGRA_PMC_CLK_OUT_1_MUX,
>>>>>>>>>>> +        .gate_id = TEGRA_PMC_CLK_OUT_1,
>>>>>>>>>>> +        .dev_name = "extern1",
>>>>>>>>>>> +        .mux_shift = 6,
>>>>>>>>>>> +        .gate_shift = 2,
>>>>>>>>>>> +        .init_parent_index = 3,
>>>>>>>>>>> +        .init_state = 1,
>>>>>>>>>>> +    },
>>>>>>>>>>> +    {
>>>>>>>>>>> +        .mux_name = "clk_out_2_mux",
>>>>>>>>>>> +        .gate_name = "clk_out_2",
>>>>>>>>>>> +        .parents = clk_out2_parents,
>>>>>>>>>>> +        .num_parents = ARRAY_SIZE(clk_out2_parents),
>>>>>>>>>>> +        .mux_id = TEGRA_PMC_CLK_OUT_2_MUX,
>>>>>>>>>>> +        .gate_id = TEGRA_PMC_CLK_OUT_2,
>>>>>>>>>>> +        .dev_name = "extern2",
>>>>>>>>>>> +        .mux_shift = 14,
>>>>>>>>>>> +        .gate_shift = 10,
>>>>>>>>>>> +        .init_parent_index = 0,
>>>>>>>>>>> +        .init_state = 0,
>>>>>>>>>>> +    },
>>>>>>>>>>> +    {
>>>>>>>>>>> +        .mux_name = "clk_out_3_mux",
>>>>>>>>>>> +        .gate_name = "clk_out_3",
>>>>>>>>>>> +        .parents = clk_out3_parents,
>>>>>>>>>>> +        .num_parents = ARRAY_SIZE(clk_out3_parents),
>>>>>>>>>>> +        .mux_id = TEGRA_PMC_CLK_OUT_3_MUX,
>>>>>>>>>>> +        .gate_id = TEGRA_PMC_CLK_OUT_3,
>>>>>>>>>>> +        .dev_name = "extern3",
>>>>>>>>>>> +        .mux_shift = 22,
>>>>>>>>>>> +        .gate_shift = 18,
>>>>>>>>>>> +        .init_parent_index = 0,
>>>>>>>>>>> +        .init_state = 0,
>>>>>>>>>>> +    },
>>>>>>>>>>> +};
>>>>>>>>>>> +
>>>>>>>>>>>     struct tegra_powergate {
>>>>>>>>>>>         struct generic_pm_domain genpd;
>>>>>>>>>>>         struct tegra_pmc *pmc;
>>>>>>>>>>> @@ -254,6 +344,9 @@ struct tegra_pmc_soc {
>>>>>>>>>>>          */
>>>>>>>>>>>         const struct tegra_wake_event *wake_events;
>>>>>>>>>>>         unsigned int num_wake_events;
>>>>>>>>>>> +
>>>>>>>>>>> +    struct pmc_clk_init_data *pmc_clks_data;
>>>>>>>>>>> +    unsigned int num_pmc_clks;
>>>>>>>>>>>     };
>>>>>>>>>>>       static const char * const tegra186_reset_sources[] = {
>>>>>>>>>>> @@ -2163,6 +2256,228 @@ static int
>>>>>>>>>>> tegra_pmc_clk_notify_cb(struct
>>>>>>>>>>> notifier_block *nb,
>>>>>>>>>>>         return NOTIFY_OK;
>>>>>>>>>>>     }
>>>>>>>>>>>     +static void pmc_clk_fence_udelay(u32 offset)
>>>>>>>>>>> +{
>>>>>>>>>>> +    tegra_pmc_readl(pmc, offset);
>>>>>>>>>>> +    /* pmc clk propagation delay 2 us */
>>>>>>>>>>> +    udelay(2);
>>>>>>>>>>> +}
>>>>>>>>>>> +
>>>>>>>>>>> +static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
>>>>>>>>>>> +{
>>>>>>>>>>> +    struct pmc_clk_mux *mux = to_pmc_clk_mux(hw);
>>>>>>>>>>> +    int num_parents = clk_hw_get_num_parents(hw);
>>>>>>>>>>> +    u32 val;
>>>>>>>>>>> +
>>>>>>>>>>> +    val = tegra_pmc_readl(pmc, mux->offs) >> mux->shift;
>>>>>>>>>>> +    val &= mux->mask;
>>>>>>>>>>> +
>>>>>>>>>>> +    if (val >= num_parents)
>>>>>>>>>>> +        return -EINVAL;
>>>>>>>>>>> +
>>>>>>>>>>> +    return val;
>>>>>>>>>>> +}
>>>>>>>>>>> +
>>>>>>>>>>> +static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
>>>>>>>>>>> +{
>>>>>>>>>>> +    struct pmc_clk_mux *mux = to_pmc_clk_mux(hw);
>>>>>>>>>>> +    u32 val;
>>>>>>>>>>> +
>>>>>>>>>>> +    val = tegra_pmc_readl(pmc, mux->offs);
>>>>>>>>>>> +    val &= ~(mux->mask << mux->shift);
>>>>>>>>>>> +    val |= index << mux->shift;
>>>>>>>>>>> +    tegra_pmc_writel(pmc, val, mux->offs);
>>>>>>>>>>> +    pmc_clk_fence_udelay(mux->offs);
>>>>>>>>>>> +
>>>>>>>>>>> +    return 0;
>>>>>>>>>>> +}
>>>>>>>>>>> +
>>>>>>>>>>> +static const struct clk_ops pmc_clk_mux_ops = {
>>>>>>>>>>> +    .get_parent = pmc_clk_mux_get_parent,
>>>>>>>>>>> +    .set_parent = pmc_clk_mux_set_parent,
>>>>>>>>>>> +    .determine_rate = __clk_mux_determine_rate,
>>>>>>>>>>> +};
>>>>>>>>>>> +
>>>>>>>>>>> +static struct clk *
>>>>>>>>>>> +tegra_pmc_clk_mux_register(const char *name, const char * const
>>>>>>>>>>> *parent_names,
>>>>>>>>>>> +               int num_parents, unsigned long flags,
>>>>>>>>>>> +               unsigned long offset, u32 shift, u32 mask)
>>>>>>>>>>> +{
>>>>>>>>>>> +    struct clk_init_data init;
>>>>>>>>>>> +    struct pmc_clk_mux *mux;
>>>>>>>>>>> +
>>>>>>>>>>> +    mux = kzalloc(sizeof(*mux), GFP_KERNEL);
>>>>>>>>>>> +    if (!mux)
>>>>>>>>>>> +        return ERR_PTR(-ENOMEM);
>>>>>>>>>>> +
>>>>>>>>>>> +    init.name = name;
>>>>>>>>>>> +    init.ops = &pmc_clk_mux_ops;
>>>>>>>>>>> +    init.parent_names = parent_names;
>>>>>>>>>>> +    init.num_parents = num_parents;
>>>>>>>>>>> +    init.flags = flags;
>>>>>>>>>>> +
>>>>>>>>>>> +    mux->hw.init = &init;
>>>>>>>>>>> +    mux->offs = offset;
>>>>>>>>>>> +    mux->mask = mask;
>>>>>>>>>>> +    mux->shift = shift;
>>>>>>>>>>> +
>>>>>>>>>>> +    return clk_register(NULL, &mux->hw);
>>>>>>>>>>> +}
>>>>>>>>>>> +
>>>>>>>>>>> +static int pmc_clk_is_enabled(struct clk_hw *hw)
>>>>>>>>>>> +{
>>>>>>>>>>> +    struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
>>>>>>>>>>> +
>>>>>>>>>>> +    return tegra_pmc_readl(pmc, gate->offs) &
>>>>>>>>>>> BIT(gate->shift) ? 1
>>>>>>>>>>> : 0;
>>>>>>>>>>> +}
>>>>>>>>>>> +
>>>>>>>>>>> +static void pmc_clk_set_state(struct clk_hw *hw, int state)
>>>>>>>>>>> +{
>>>>>>>>>>> +    struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
>>>>>>>>>>> +    u32 val;
>>>>>>>>>>> +
>>>>>>>>>>> +    val = tegra_pmc_readl(pmc, gate->offs);
>>>>>>>>>>> +    val = state ? (val | BIT(gate->shift)) : (val &
>>>>>>>>>>> ~BIT(gate->shift));
>>>>>>>>>>> +    tegra_pmc_writel(pmc, val, gate->offs);
>>>>>>>>>>> +    pmc_clk_fence_udelay(gate->offs);
>>>>>>>>>>> +}
>>>>>>>>>>> +
>>>>>>>>>>> +static int pmc_clk_enable(struct clk_hw *hw)
>>>>>>>>>>> +{
>>>>>>>>>>> +    pmc_clk_set_state(hw, 1);
>>>>>>>>>>> +
>>>>>>>>>>> +    return 0;
>>>>>>>>>>> +}
>>>>>>>>>>> +
>>>>>>>>>>> +static void pmc_clk_disable(struct clk_hw *hw)
>>>>>>>>>>> +{
>>>>>>>>>>> +    pmc_clk_set_state(hw, 0);
>>>>>>>>>>> +}
>>>>>>>>>>> +
>>>>>>>>>>> +static const struct clk_ops pmc_clk_gate_ops = {
>>>>>>>>>>> +    .is_enabled = pmc_clk_is_enabled,
>>>>>>>>>>> +    .enable = pmc_clk_enable,
>>>>>>>>>>> +    .disable = pmc_clk_disable,
>>>>>>>>>>> +};
>>>>>>>>>>> +
>>>>>>>>>>> +static struct clk *
>>>>>>>>>>> +tegra_pmc_clk_gate_register(const char *name, const char
>>>>>>>>>>> *parent_name,
>>>>>>>>>>> +                unsigned long flags, unsigned long offset,
>>>>>>>>>>> +                u32 shift)
>>>>>>>>>>> +{
>>>>>>>>>>> +    struct clk_init_data init;
>>>>>>>>>>> +    struct pmc_clk_gate *gate;
>>>>>>>>>>> +
>>>>>>>>>>> +    gate = kzalloc(sizeof(*gate), GFP_KERNEL);
>>>>>>>>>>> +    if (!gate)
>>>>>>>>>>> +        return ERR_PTR(-ENOMEM);
>>>>>>>>>>> +
>>>>>>>>>>> +    init.name = name;
>>>>>>>>>>> +    init.ops = &pmc_clk_gate_ops;
>>>>>>>>>>> +    init.parent_names = &parent_name;
>>>>>>>>>>> +    init.num_parents = 1;
>>>>>>>>>>> +    init.flags = flags;
>>>>>>>>>>> +
>>>>>>>>>>> +    gate->hw.init = &init;
>>>>>>>>>>> +    gate->offs = offset;
>>>>>>>>>>> +    gate->shift = shift;
>>>>>>>>>>> +
>>>>>>>>>>> +    return clk_register(NULL, &gate->hw);
>>>>>>>>>>> +}
>>>>>>>>>>> +
>>>>>>>>>>> +static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
>>>>>>>>>>> +                     struct device_node *np)
>>>>>>>>>>> +{
>>>>>>>>>>> +    struct clk *clkmux, *clk, *parent;
>>>>>>>>>>> +    struct clk_onecell_data *clk_data;
>>>>>>>>>>> +    unsigned int num_clks;
>>>>>>>>>>> +    int i, ret;
>>>>>>>>>>> +
>>>>>>>>>>> +    /* each pmc clock output has a mux and a gate */
>>>>>>>>>>> +    num_clks = pmc->soc->num_pmc_clks * 2;
>>>>>>>>>>> +
>>>>>>>>>>> +    if (!num_clks)
>>>>>>>>>>> +        return;
>>>>>>>>>>> +
>>>>>>>>>>> +    clk_data = kmalloc(sizeof(*clk_data), GFP_KERNEL);
>>>>>>>>>>> +    if (!clk_data)
>>>>>>>>>>> +        return;
>>>>>>>>>>> +
>>>>>>>>>>> +    clk_data->clks = kcalloc(TEGRA_PMC_CLK_MAX,
>>>>>>>>>>> sizeof(*clk_data->clks),
>>>>>>>>>>> +                 GFP_KERNEL);
>>>>>>>>>>> +    if (!clk_data->clks)
>>>>>>>>>>> +        goto free_clkdata;
>>>>>>>>>>> +
>>>>>>>>>>> +    clk_data->clk_num = num_clks;
>>>>>>>>>>> +
>>>>>>>>>>> +    for (i = 0; i < pmc->soc->num_pmc_clks; i++) {
>>>>>>>>>>> +        struct pmc_clk_init_data *data;
>>>>>>>>>>> +
>>>>>>>>>>> +        data = pmc->soc->pmc_clks_data + i;
>>>>>>>>>>> +
>>>>>>>>>>> +        clkmux = tegra_pmc_clk_mux_register(data->mux_name,
>>>>>>>>>>> +                            data->parents,
>>>>>>>>>>> + data->num_parents,
>>>>>>>>>>> + CLK_SET_RATE_NO_REPARENT |
>>>>>>>>>>> + CLK_SET_RATE_PARENT,
>>>>>>>>>>> +                            PMC_CLK_OUT_CNTRL,
>>>>>>>>>>> +                            data->mux_shift, 3);
>>>>>>>>>>> +        if (IS_ERR(clkmux))
>>>>>>>>>>> +            goto free_clks;
>>>>>>>>>>> +
>>>>>>>>>>> +        clk_data->clks[data->mux_id] = clkmux;
>>>>>>>>>>> +
>>>>>>>>>>> +        clk = tegra_pmc_clk_gate_register(data->gate_name,
>>>>>>>>>>> +                          data->mux_name,
>>>>>>>>>>> +                          CLK_SET_RATE_PARENT,
>>>>>>>>>>> +                          PMC_CLK_OUT_CNTRL,
>>>>>>>>>>> +                          data->gate_shift);
>>>>>>>>>>> +        if (IS_ERR(clk))
>>>>>>>>>>> +            goto free_clks;
>>>>>>>>>>> +
>>>>>>>>>>> +        clk_data->clks[data->gate_id] = clk;
>>>>>>>>>>> +
>>>>>>>>>>> +        ret = clk_set_parent(clk, clkmux);
>>>>>>>>>>> +        if (ret < 0) {
>>>>>>>>>>> +            pr_err("failed to set parent of %s to %s\n",
>>>>>>>>>>> +                   __func__, __clk_get_name(clk),
>>>>>>>>>>> +                   __clk_get_name(clkmux));
>>>>>>>>>>> +        }
>>>>>>>>>>> +
>>>>>>>>>>> +        clk_register_clkdev(clk, data->dev_name,
>>>>>>>>>>> data->gate_name);
>>>>>>>>>>> +
>>>>>>>>>>> +        /* configure initial clock parent and state */
>>>>>>>>>>> +        parent = clk_get_sys(data->gate_name,
>>>>>>>>>>> + data->parents[data->init_parent_index]);
>>>>>> Couldn't the default parent be defined using "assigned clock" in a
>>>>>> device-tree? Please see "Assigned clock parents and rates" in the
>>>>>> doc.
>>>>>>
>>>>>> https://www.kernel.org/doc/Documentation/devicetree/bindings/clock/clock-bindings.txt
>>>>>>
>>>>>>
>>>>>> Then you could simply use of_clk_set_defaults(pmc->dev->of_node,
>>>>>> true).
>>>>>
>>>>> Yes, of_clk_add_provider() does of_clk_set_defaults which sets
>>>>> based on assigned parents and clock rates.
>>>>>
>>>>> This need device tree to specify assigned clock parent properties.
>>>>> Will update device tree and remove init parent from the driver.
>>>>>
>>>> assigned-clock properties should be set in consumer node of these
>>>> clocks and currently these clocks are not used yet.
>>>>
>>>> So will just remove init parent from driver and when these clocks
>>>> are used device tree can be updated in corresponding consumer node
>>>> with these properties.
>>>>
>>> How about default ON/OFF init state for the clocks? I see
>>> assigned-clock properties for parent and rate only.
>>>
>>> But based on existing clock-tegra-pmc driver, I see clk_out_1 is
>>> default enabled with extern1 parent for T30 thru T210 platforms.
>>>
>>> Peter/Thierry, What was the reason we enable clk_out_1 right from the
>>> clock registration?
>>>
>> clk_out_1 is for audio and its not required to be enabled during the
>> boot and audio driver can enable/disable it.
>>
>> same with blink 32khz which is used for WIFI. WIFI driver can
>> enable/disable during power up/down sequence and technically as per
>> design we dont need to have it always on right from the boot.
>>
>> So can remove out clocks init states from driver once thierry also
>> agree on this.
>>
> Hi Dmitry,
> 
> Looking at audio driver, it doesn't take care of mclk which is from
> clk_out_1 and expects mclk to be always on.
> 
> So probably we should have this init state enables in pmc driver for
> 32Khz and clk_out's to not break existing functionality.

Hello Sowjanya,

IIUC, it's a bug in the device-trees and sound's MCLK actually should be
set to CLK_OUT_1 of PMC instead of CaR's EXTPERIPH1. If that's the case,
then the device-trees need to be fixed.

> Regarding using assigned-clock properties for init parent and removing
> init parent from driver, it also needs consumer node in device tree to
> be updated to specify assigned-clock properties for default/init parent.
> 
> This breaks device tree ABI as prior Tegra210 supports audio driver.

So it's the sound node which should have had the assigned clocks in
device-tree in order to define route for the audio MCLK clock from CaR
to PMC.

Given that the audio clocks configuration is the same for all of the
currently supported boards, I think it will be better to remove the
entire audio clocks initialization from the clk drivers and move it all
to the audio driver. It could be something like this:

int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data,
			  struct device *dev)
{
	...

	if (!of_find_property(dev->of_node, "assigned-clock-parents", NULL) &&
	    tegra_get_chip_id() > TEGRA20) {
		clk_extern1 = clk_get(dev, "extern1");
		...
		clk_set_parent(clk_extern1, clk_pll_a_out0);
		...
		clk_put(data->clk_cdev1);

		data->clk_cdev1 = clk_out_1;
	}
	...

So now the old device-trees will cointinue to work and new could have
the assigned-clocks and set MCLK to CLK_OUT_1.

[snip]

On 12/4/19 5:39 AM, Dmitry Osipenko wrote:
> 03.12.2019 19:45, Sowjanya Komatineni пишет:
>> On 12/2/19 4:07 PM, Sowjanya Komatineni wrote:
>>> On 12/2/19 3:14 PM, Sowjanya Komatineni wrote:
>>>> On 12/2/19 3:10 PM, Sowjanya Komatineni wrote:
>>>>> On 12/2/19 2:58 PM, Sowjanya Komatineni wrote:
>>>>>> On 12/2/19 1:50 PM, Dmitry Osipenko wrote:
>>>>>>> 02.12.2019 23:09, Sowjanya Komatineni пишет:
>>>>>>>> On 11/28/19 5:25 AM, Dmitry Osipenko wrote:
>>>>>>>>> 28.11.2019 01:57, Sowjanya Komatineni пишет:
>>>>>>>>>> On 11/27/19 7:14 AM, Dmitry Osipenko wrote:
>>>>>>>>>>> 27.11.2019 07:59, Sowjanya Komatineni пишет:
>>>>>>>>>>>> Tegra210 and prior Tegra PMC has clk_out_1, clk_out_2,
>>>>>>>>>>>> clk_out_3 with
>>>>>>>>>>>> mux and gate for each of these clocks.
>>>>>>>>>>>>
>>>>>>>>>>>> Currently these PMC clocks are registered by Tegra clock
>>>>>>>>>>>> driver using
>>>>>>>>>>>> clk_register_mux and clk_register_gate by passing PMC base
>>>>>>>>>>>> address
>>>>>>>>>>>> and register offsets and PMC programming for these clocks
>>>>>>>>>>>> happens
>>>>>>>>>>>> through direct PMC access by the clock driver.
>>>>>>>>>>>>
>>>>>>>>>>>> With this, when PMC is in secure mode any direct PMC access
>>>>>>>>>>>> from the
>>>>>>>>>>>> non-secure world does not go through and these clocks will
>>>>>>>>>>>> not be
>>>>>>>>>>>> functional.
>>>>>>>>>>>>
>>>>>>>>>>>> This patch adds these clocks registration with PMC as a clock
>>>>>>>>>>>> provider
>>>>>>>>>>>> for these clocks. clk_ops callback implementations for these
>>>>>>>>>>>> clocks
>>>>>>>>>>>> uses tegra_pmc_readl and tegra_pmc_writel which supports PMC
>>>>>>>>>>>> programming
>>>>>>>>>>>> in secure mode and non-secure mode.
>>>>>>>>>>>>
>>>>>>>>>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>>>>>>>>>> ---
>>>>>>>>>>>>      drivers/soc/tegra/pmc.c | 330
>>>>>>>>>>>> ++++++++++++++++++++++++++++++++++++++++++++++++
>>>>>>>>>>>>      1 file changed, 330 insertions(+)
>>>>>>>>>>>>
>>>>>>>>>>>> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
>>>>>>>>>>>> index ea0e11a09c12..a353f6d0a832 100644
>>>>>>>>>>>> --- a/drivers/soc/tegra/pmc.c
>>>>>>>>>>>> +++ b/drivers/soc/tegra/pmc.c
>>>>>>>>>>>> @@ -13,6 +13,9 @@
>>>>>>>>>>>>        #include <linux/arm-smccc.h>
>>>>>>>>>>>>      #include <linux/clk.h>
>>>>>>>>>>>> +#include <linux/clk-provider.h>
>>>>>>>>>>>> +#include <linux/clkdev.h>
>>>>>>>>>>>> +#include <linux/clk/clk-conf.h>
>>>>>>>>>>>>      #include <linux/clk/tegra.h>
>>>>>>>>>>>>      #include <linux/debugfs.h>
>>>>>>>>>>>>      #include <linux/delay.h>
>>>>>>>>>>>> @@ -48,6 +51,7 @@
>>>>>>>>>>>>      #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
>>>>>>>>>>>>      #include <dt-bindings/gpio/tegra186-gpio.h>
>>>>>>>>>>>>      #include <dt-bindings/gpio/tegra194-gpio.h>
>>>>>>>>>>>> +#include <dt-bindings/soc/tegra-pmc.h>
>>>>>>>>>>>>        #define PMC_CNTRL            0x0
>>>>>>>>>>>>      #define  PMC_CNTRL_INTR_POLARITY    BIT(17) /* inverts INTR
>>>>>>>>>>>> polarity */
>>>>>>>>>>>> @@ -100,6 +104,7 @@
>>>>>>>>>>>>      #define PMC_WAKE2_STATUS        0x168
>>>>>>>>>>>>      #define PMC_SW_WAKE2_STATUS        0x16c
>>>>>>>>>>>>      +#define PMC_CLK_OUT_CNTRL        0x1a8
>>>>>>>>>>>>      #define PMC_SENSOR_CTRL            0x1b0
>>>>>>>>>>>>      #define  PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2)
>>>>>>>>>>>>      #define  PMC_SENSOR_CTRL_ENABLE_RST BIT(1)
>>>>>>>>>>>> @@ -155,6 +160,91 @@
>>>>>>>>>>>>      #define  TEGRA_SMC_PMC_READ    0xaa
>>>>>>>>>>>>      #define  TEGRA_SMC_PMC_WRITE    0xbb
>>>>>>>>>>>>      +struct pmc_clk_mux {
>>>>>>>>>>>> +    struct clk_hw    hw;
>>>>>>>>>>>> +    unsigned long    offs;
>>>>>>>>>>>> +    u32        mask;
>>>>>>>>>>>> +    u32        shift;
>>>>>>>>>>>> +};
>>>>>>>>>>>> +
>>>>>>>>>>>> +#define to_pmc_clk_mux(_hw) container_of(_hw, struct
>>>>>>>>>>>> pmc_clk_mux, hw)
>>>>>>>>>>>> +
>>>>>>>>>>>> +struct pmc_clk_gate {
>>>>>>>>>>>> +    struct clk_hw    hw;
>>>>>>>>>>>> +    unsigned long    offs;
>>>>>>>>>>>> +    u32        shift;
>>>>>>>>>>>> +};
>>>>>>>>>>>> +
>>>>>>>>>>>> +#define to_pmc_clk_gate(_hw) container_of(_hw, struct
>>>>>>>>>>>> pmc_clk_gate, hw)
>>>>>>>>>>>> +
>>>>>>>>>>>> +struct pmc_clk_init_data {
>>>>>>>>>>>> +    char *mux_name;
>>>>>>>>>>>> +    char *gate_name;
>>>>>>>>>>>> +    const char **parents;
>>>>>>>>>>>> +    int num_parents;
>>>>>>>>>>>> +    int mux_id;
>>>>>>>>>>>> +    int gate_id;
>>>>>>>>>>>> +    char *dev_name;
>>>>>>>>>>>> +    u8 mux_shift;
>>>>>>>>>>>> +    u8 gate_shift;
>>>>>>>>>>>> +    u8 init_parent_index;
>>>>>>>>>>>> +    int init_state;
>>>>>>>>>>>> +};
>>>>>>>>>>>> +
>>>>>>>>>>>> +static const char *clk_out1_parents[] = { "clk_m",
>>>>>>>>>>>> "clk_m_div2",
>>>>>>>>>>>> +    "clk_m_div4", "extern1",
>>>>>>>>>>>> +};
>>>>>>>>>>>> +
>>>>>>>>>>>> +static const char *clk_out2_parents[] = { "clk_m",
>>>>>>>>>>>> "clk_m_div2",
>>>>>>>>>>>> +    "clk_m_div4", "extern2",
>>>>>>>>>>>> +};
>>>>>>>>>>>> +
>>>>>>>>>>>> +static const char *clk_out3_parents[] = { "clk_m",
>>>>>>>>>>>> "clk_m_div2",
>>>>>>>>>>>> +    "clk_m_div4", "extern3",
>>>>>>>>>>>> +};
>>>>>>>>>>>> +
>>>>>>>>>>>> +static struct pmc_clk_init_data tegra_pmc_clks_data[] = {
>>>>>>>>>>>> +    {
>>>>>>>>>>>> +        .mux_name = "clk_out_1_mux",
>>>>>>>>>>>> +        .gate_name = "clk_out_1",
>>>>>>>>>>>> +        .parents = clk_out1_parents,
>>>>>>>>>>>> +        .num_parents = ARRAY_SIZE(clk_out1_parents),
>>>>>>>>>>>> +        .mux_id = TEGRA_PMC_CLK_OUT_1_MUX,
>>>>>>>>>>>> +        .gate_id = TEGRA_PMC_CLK_OUT_1,
>>>>>>>>>>>> +        .dev_name = "extern1",
>>>>>>>>>>>> +        .mux_shift = 6,
>>>>>>>>>>>> +        .gate_shift = 2,
>>>>>>>>>>>> +        .init_parent_index = 3,
>>>>>>>>>>>> +        .init_state = 1,
>>>>>>>>>>>> +    },
>>>>>>>>>>>> +    {
>>>>>>>>>>>> +        .mux_name = "clk_out_2_mux",
>>>>>>>>>>>> +        .gate_name = "clk_out_2",
>>>>>>>>>>>> +        .parents = clk_out2_parents,
>>>>>>>>>>>> +        .num_parents = ARRAY_SIZE(clk_out2_parents),
>>>>>>>>>>>> +        .mux_id = TEGRA_PMC_CLK_OUT_2_MUX,
>>>>>>>>>>>> +        .gate_id = TEGRA_PMC_CLK_OUT_2,
>>>>>>>>>>>> +        .dev_name = "extern2",
>>>>>>>>>>>> +        .mux_shift = 14,
>>>>>>>>>>>> +        .gate_shift = 10,
>>>>>>>>>>>> +        .init_parent_index = 0,
>>>>>>>>>>>> +        .init_state = 0,
>>>>>>>>>>>> +    },
>>>>>>>>>>>> +    {
>>>>>>>>>>>> +        .mux_name = "clk_out_3_mux",
>>>>>>>>>>>> +        .gate_name = "clk_out_3",
>>>>>>>>>>>> +        .parents = clk_out3_parents,
>>>>>>>>>>>> +        .num_parents = ARRAY_SIZE(clk_out3_parents),
>>>>>>>>>>>> +        .mux_id = TEGRA_PMC_CLK_OUT_3_MUX,
>>>>>>>>>>>> +        .gate_id = TEGRA_PMC_CLK_OUT_3,
>>>>>>>>>>>> +        .dev_name = "extern3",
>>>>>>>>>>>> +        .mux_shift = 22,
>>>>>>>>>>>> +        .gate_shift = 18,
>>>>>>>>>>>> +        .init_parent_index = 0,
>>>>>>>>>>>> +        .init_state = 0,
>>>>>>>>>>>> +    },
>>>>>>>>>>>> +};
>>>>>>>>>>>> +
>>>>>>>>>>>>      struct tegra_powergate {
>>>>>>>>>>>>          struct generic_pm_domain genpd;
>>>>>>>>>>>>          struct tegra_pmc *pmc;
>>>>>>>>>>>> @@ -254,6 +344,9 @@ struct tegra_pmc_soc {
>>>>>>>>>>>>           */
>>>>>>>>>>>>          const struct tegra_wake_event *wake_events;
>>>>>>>>>>>>          unsigned int num_wake_events;
>>>>>>>>>>>> +
>>>>>>>>>>>> +    struct pmc_clk_init_data *pmc_clks_data;
>>>>>>>>>>>> +    unsigned int num_pmc_clks;
>>>>>>>>>>>>      };
>>>>>>>>>>>>        static const char * const tegra186_reset_sources[] = {
>>>>>>>>>>>> @@ -2163,6 +2256,228 @@ static int
>>>>>>>>>>>> tegra_pmc_clk_notify_cb(struct
>>>>>>>>>>>> notifier_block *nb,
>>>>>>>>>>>>          return NOTIFY_OK;
>>>>>>>>>>>>      }
>>>>>>>>>>>>      +static void pmc_clk_fence_udelay(u32 offset)
>>>>>>>>>>>> +{
>>>>>>>>>>>> +    tegra_pmc_readl(pmc, offset);
>>>>>>>>>>>> +    /* pmc clk propagation delay 2 us */
>>>>>>>>>>>> +    udelay(2);
>>>>>>>>>>>> +}
>>>>>>>>>>>> +
>>>>>>>>>>>> +static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
>>>>>>>>>>>> +{
>>>>>>>>>>>> +    struct pmc_clk_mux *mux = to_pmc_clk_mux(hw);
>>>>>>>>>>>> +    int num_parents = clk_hw_get_num_parents(hw);
>>>>>>>>>>>> +    u32 val;
>>>>>>>>>>>> +
>>>>>>>>>>>> +    val = tegra_pmc_readl(pmc, mux->offs) >> mux->shift;
>>>>>>>>>>>> +    val &= mux->mask;
>>>>>>>>>>>> +
>>>>>>>>>>>> +    if (val >= num_parents)
>>>>>>>>>>>> +        return -EINVAL;
>>>>>>>>>>>> +
>>>>>>>>>>>> +    return val;
>>>>>>>>>>>> +}
>>>>>>>>>>>> +
>>>>>>>>>>>> +static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
>>>>>>>>>>>> +{
>>>>>>>>>>>> +    struct pmc_clk_mux *mux = to_pmc_clk_mux(hw);
>>>>>>>>>>>> +    u32 val;
>>>>>>>>>>>> +
>>>>>>>>>>>> +    val = tegra_pmc_readl(pmc, mux->offs);
>>>>>>>>>>>> +    val &= ~(mux->mask << mux->shift);
>>>>>>>>>>>> +    val |= index << mux->shift;
>>>>>>>>>>>> +    tegra_pmc_writel(pmc, val, mux->offs);
>>>>>>>>>>>> +    pmc_clk_fence_udelay(mux->offs);
>>>>>>>>>>>> +
>>>>>>>>>>>> +    return 0;
>>>>>>>>>>>> +}
>>>>>>>>>>>> +
>>>>>>>>>>>> +static const struct clk_ops pmc_clk_mux_ops = {
>>>>>>>>>>>> +    .get_parent = pmc_clk_mux_get_parent,
>>>>>>>>>>>> +    .set_parent = pmc_clk_mux_set_parent,
>>>>>>>>>>>> +    .determine_rate = __clk_mux_determine_rate,
>>>>>>>>>>>> +};
>>>>>>>>>>>> +
>>>>>>>>>>>> +static struct clk *
>>>>>>>>>>>> +tegra_pmc_clk_mux_register(const char *name, const char * const
>>>>>>>>>>>> *parent_names,
>>>>>>>>>>>> +               int num_parents, unsigned long flags,
>>>>>>>>>>>> +               unsigned long offset, u32 shift, u32 mask)
>>>>>>>>>>>> +{
>>>>>>>>>>>> +    struct clk_init_data init;
>>>>>>>>>>>> +    struct pmc_clk_mux *mux;
>>>>>>>>>>>> +
>>>>>>>>>>>> +    mux = kzalloc(sizeof(*mux), GFP_KERNEL);
>>>>>>>>>>>> +    if (!mux)
>>>>>>>>>>>> +        return ERR_PTR(-ENOMEM);
>>>>>>>>>>>> +
>>>>>>>>>>>> +    init.name = name;
>>>>>>>>>>>> +    init.ops = &pmc_clk_mux_ops;
>>>>>>>>>>>> +    init.parent_names = parent_names;
>>>>>>>>>>>> +    init.num_parents = num_parents;
>>>>>>>>>>>> +    init.flags = flags;
>>>>>>>>>>>> +
>>>>>>>>>>>> +    mux->hw.init = &init;
>>>>>>>>>>>> +    mux->offs = offset;
>>>>>>>>>>>> +    mux->mask = mask;
>>>>>>>>>>>> +    mux->shift = shift;
>>>>>>>>>>>> +
>>>>>>>>>>>> +    return clk_register(NULL, &mux->hw);
>>>>>>>>>>>> +}
>>>>>>>>>>>> +
>>>>>>>>>>>> +static int pmc_clk_is_enabled(struct clk_hw *hw)
>>>>>>>>>>>> +{
>>>>>>>>>>>> +    struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
>>>>>>>>>>>> +
>>>>>>>>>>>> +    return tegra_pmc_readl(pmc, gate->offs) &
>>>>>>>>>>>> BIT(gate->shift) ? 1
>>>>>>>>>>>> : 0;
>>>>>>>>>>>> +}
>>>>>>>>>>>> +
>>>>>>>>>>>> +static void pmc_clk_set_state(struct clk_hw *hw, int state)
>>>>>>>>>>>> +{
>>>>>>>>>>>> +    struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
>>>>>>>>>>>> +    u32 val;
>>>>>>>>>>>> +
>>>>>>>>>>>> +    val = tegra_pmc_readl(pmc, gate->offs);
>>>>>>>>>>>> +    val = state ? (val | BIT(gate->shift)) : (val &
>>>>>>>>>>>> ~BIT(gate->shift));
>>>>>>>>>>>> +    tegra_pmc_writel(pmc, val, gate->offs);
>>>>>>>>>>>> +    pmc_clk_fence_udelay(gate->offs);
>>>>>>>>>>>> +}
>>>>>>>>>>>> +
>>>>>>>>>>>> +static int pmc_clk_enable(struct clk_hw *hw)
>>>>>>>>>>>> +{
>>>>>>>>>>>> +    pmc_clk_set_state(hw, 1);
>>>>>>>>>>>> +
>>>>>>>>>>>> +    return 0;
>>>>>>>>>>>> +}
>>>>>>>>>>>> +
>>>>>>>>>>>> +static void pmc_clk_disable(struct clk_hw *hw)
>>>>>>>>>>>> +{
>>>>>>>>>>>> +    pmc_clk_set_state(hw, 0);
>>>>>>>>>>>> +}
>>>>>>>>>>>> +
>>>>>>>>>>>> +static const struct clk_ops pmc_clk_gate_ops = {
>>>>>>>>>>>> +    .is_enabled = pmc_clk_is_enabled,
>>>>>>>>>>>> +    .enable = pmc_clk_enable,
>>>>>>>>>>>> +    .disable = pmc_clk_disable,
>>>>>>>>>>>> +};
>>>>>>>>>>>> +
>>>>>>>>>>>> +static struct clk *
>>>>>>>>>>>> +tegra_pmc_clk_gate_register(const char *name, const char
>>>>>>>>>>>> *parent_name,
>>>>>>>>>>>> +                unsigned long flags, unsigned long offset,
>>>>>>>>>>>> +                u32 shift)
>>>>>>>>>>>> +{
>>>>>>>>>>>> +    struct clk_init_data init;
>>>>>>>>>>>> +    struct pmc_clk_gate *gate;
>>>>>>>>>>>> +
>>>>>>>>>>>> +    gate = kzalloc(sizeof(*gate), GFP_KERNEL);
>>>>>>>>>>>> +    if (!gate)
>>>>>>>>>>>> +        return ERR_PTR(-ENOMEM);
>>>>>>>>>>>> +
>>>>>>>>>>>> +    init.name = name;
>>>>>>>>>>>> +    init.ops = &pmc_clk_gate_ops;
>>>>>>>>>>>> +    init.parent_names = &parent_name;
>>>>>>>>>>>> +    init.num_parents = 1;
>>>>>>>>>>>> +    init.flags = flags;
>>>>>>>>>>>> +
>>>>>>>>>>>> +    gate->hw.init = &init;
>>>>>>>>>>>> +    gate->offs = offset;
>>>>>>>>>>>> +    gate->shift = shift;
>>>>>>>>>>>> +
>>>>>>>>>>>> +    return clk_register(NULL, &gate->hw);
>>>>>>>>>>>> +}
>>>>>>>>>>>> +
>>>>>>>>>>>> +static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
>>>>>>>>>>>> +                     struct device_node *np)
>>>>>>>>>>>> +{
>>>>>>>>>>>> +    struct clk *clkmux, *clk, *parent;
>>>>>>>>>>>> +    struct clk_onecell_data *clk_data;
>>>>>>>>>>>> +    unsigned int num_clks;
>>>>>>>>>>>> +    int i, ret;
>>>>>>>>>>>> +
>>>>>>>>>>>> +    /* each pmc clock output has a mux and a gate */
>>>>>>>>>>>> +    num_clks = pmc->soc->num_pmc_clks * 2;
>>>>>>>>>>>> +
>>>>>>>>>>>> +    if (!num_clks)
>>>>>>>>>>>> +        return;
>>>>>>>>>>>> +
>>>>>>>>>>>> +    clk_data = kmalloc(sizeof(*clk_data), GFP_KERNEL);
>>>>>>>>>>>> +    if (!clk_data)
>>>>>>>>>>>> +        return;
>>>>>>>>>>>> +
>>>>>>>>>>>> +    clk_data->clks = kcalloc(TEGRA_PMC_CLK_MAX,
>>>>>>>>>>>> sizeof(*clk_data->clks),
>>>>>>>>>>>> +                 GFP_KERNEL);
>>>>>>>>>>>> +    if (!clk_data->clks)
>>>>>>>>>>>> +        goto free_clkdata;
>>>>>>>>>>>> +
>>>>>>>>>>>> +    clk_data->clk_num = num_clks;
>>>>>>>>>>>> +
>>>>>>>>>>>> +    for (i = 0; i < pmc->soc->num_pmc_clks; i++) {
>>>>>>>>>>>> +        struct pmc_clk_init_data *data;
>>>>>>>>>>>> +
>>>>>>>>>>>> +        data = pmc->soc->pmc_clks_data + i;
>>>>>>>>>>>> +
>>>>>>>>>>>> +        clkmux = tegra_pmc_clk_mux_register(data->mux_name,
>>>>>>>>>>>> +                            data->parents,
>>>>>>>>>>>> + data->num_parents,
>>>>>>>>>>>> + CLK_SET_RATE_NO_REPARENT |
>>>>>>>>>>>> + CLK_SET_RATE_PARENT,
>>>>>>>>>>>> +                            PMC_CLK_OUT_CNTRL,
>>>>>>>>>>>> +                            data->mux_shift, 3);
>>>>>>>>>>>> +        if (IS_ERR(clkmux))
>>>>>>>>>>>> +            goto free_clks;
>>>>>>>>>>>> +
>>>>>>>>>>>> +        clk_data->clks[data->mux_id] = clkmux;
>>>>>>>>>>>> +
>>>>>>>>>>>> +        clk = tegra_pmc_clk_gate_register(data->gate_name,
>>>>>>>>>>>> +                          data->mux_name,
>>>>>>>>>>>> +                          CLK_SET_RATE_PARENT,
>>>>>>>>>>>> +                          PMC_CLK_OUT_CNTRL,
>>>>>>>>>>>> +                          data->gate_shift);
>>>>>>>>>>>> +        if (IS_ERR(clk))
>>>>>>>>>>>> +            goto free_clks;
>>>>>>>>>>>> +
>>>>>>>>>>>> +        clk_data->clks[data->gate_id] = clk;
>>>>>>>>>>>> +
>>>>>>>>>>>> +        ret = clk_set_parent(clk, clkmux);
>>>>>>>>>>>> +        if (ret < 0) {
>>>>>>>>>>>> +            pr_err("failed to set parent of %s to %s\n",
>>>>>>>>>>>> +                   __func__, __clk_get_name(clk),
>>>>>>>>>>>> +                   __clk_get_name(clkmux));
>>>>>>>>>>>> +        }
>>>>>>>>>>>> +
>>>>>>>>>>>> +        clk_register_clkdev(clk, data->dev_name,
>>>>>>>>>>>> data->gate_name);
>>>>>>>>>>>> +
>>>>>>>>>>>> +        /* configure initial clock parent and state */
>>>>>>>>>>>> +        parent = clk_get_sys(data->gate_name,
>>>>>>>>>>>> + data->parents[data->init_parent_index]);
>>>>>>> Couldn't the default parent be defined using "assigned clock" in a
>>>>>>> device-tree? Please see "Assigned clock parents and rates" in the
>>>>>>> doc.
>>>>>>>
>>>>>>> https://www.kernel.org/doc/Documentation/devicetree/bindings/clock/clock-bindings.txt
>>>>>>>
>>>>>>>
>>>>>>> Then you could simply use of_clk_set_defaults(pmc->dev->of_node,
>>>>>>> true).
>>>>>> Yes, of_clk_add_provider() does of_clk_set_defaults which sets
>>>>>> based on assigned parents and clock rates.
>>>>>>
>>>>>> This need device tree to specify assigned clock parent properties.
>>>>>> Will update device tree and remove init parent from the driver.
>>>>>>
>>>>> assigned-clock properties should be set in consumer node of these
>>>>> clocks and currently these clocks are not used yet.
>>>>>
>>>>> So will just remove init parent from driver and when these clocks
>>>>> are used device tree can be updated in corresponding consumer node
>>>>> with these properties.
>>>>>
>>>> How about default ON/OFF init state for the clocks? I see
>>>> assigned-clock properties for parent and rate only.
>>>>
>>>> But based on existing clock-tegra-pmc driver, I see clk_out_1 is
>>>> default enabled with extern1 parent for T30 thru T210 platforms.
>>>>
>>>> Peter/Thierry, What was the reason we enable clk_out_1 right from the
>>>> clock registration?
>>>>
>>> clk_out_1 is for audio and its not required to be enabled during the
>>> boot and audio driver can enable/disable it.
>>>
>>> same with blink 32khz which is used for WIFI. WIFI driver can
>>> enable/disable during power up/down sequence and technically as per
>>> design we dont need to have it always on right from the boot.
>>>
>>> So can remove out clocks init states from driver once thierry also
>>> agree on this.
>>>
>> Hi Dmitry,
>>
>> Looking at audio driver, it doesn't take care of mclk which is from
>> clk_out_1 and expects mclk to be always on.
>>
>> So probably we should have this init state enables in pmc driver for
>> 32Khz and clk_out's to not break existing functionality.
> Hello Sowjanya,
>
> IIUC, it's a bug in the device-trees and sound's MCLK actually should be
> set to CLK_OUT_1 of PMC instead of CaR's EXTPERIPH1. If that's the case,
> then the device-trees need to be fixed.

OK, will have this in v3

>> Regarding using assigned-clock properties for init parent and removing
>> init parent from driver, it also needs consumer node in device tree to
>> be updated to specify assigned-clock properties for default/init parent.
>>
>> This breaks device tree ABI as prior Tegra210 supports audio driver.
> So it's the sound node which should have had the assigned clocks in
> device-tree in order to define route for the audio MCLK clock from CaR
> to PMC.
>
> Given that the audio clocks configuration is the same for all of the
> currently supported boards, I think it will be better to remove the
> entire audio clocks initialization from the clk drivers and move it all
> to the audio driver. It could be something like this:
>
> int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data,
> 			  struct device *dev)
> {
> 	...
>
> 	if (!of_find_property(dev->of_node, "assigned-clock-parents", NULL) &&
> 	    tegra_get_chip_id() > TEGRA20) {
> 		clk_extern1 = clk_get(dev, "extern1");
> 		...
> 		clk_set_parent(clk_extern1, clk_pll_a_out0);
> 		...
> 		clk_put(data->clk_cdev1);
>
> 		data->clk_cdev1 = clk_out_1;
> 	}
> 	...
>
> So now the old device-trees will cointinue to work and new could have
> the assigned-clocks and set MCLK to CLK_OUT_1.
>
> [snip]

Will update clk-tegra, pmc and audio driver to move init state 
configuration for extern1 and clk_out_1 into audio driver and will use 
assigned clock properties in device tree.

On 12/4/19 8:02 AM, Sowjanya Komatineni wrote:
>
> On 12/4/19 5:39 AM, Dmitry Osipenko wrote:
>> 03.12.2019 19:45, Sowjanya Komatineni пишет:
>>> On 12/2/19 4:07 PM, Sowjanya Komatineni wrote:
>>>> On 12/2/19 3:14 PM, Sowjanya Komatineni wrote:
>>>>> On 12/2/19 3:10 PM, Sowjanya Komatineni wrote:
>>>>>> On 12/2/19 2:58 PM, Sowjanya Komatineni wrote:
>>>>>>> On 12/2/19 1:50 PM, Dmitry Osipenko wrote:
>>>>>>>> 02.12.2019 23:09, Sowjanya Komatineni пишет:
>>>>>>>>> On 11/28/19 5:25 AM, Dmitry Osipenko wrote:
>>>>>>>>>> 28.11.2019 01:57, Sowjanya Komatineni пишет:
>>>>>>>>>>> On 11/27/19 7:14 AM, Dmitry Osipenko wrote:
>>>>>>>>>>>> 27.11.2019 07:59, Sowjanya Komatineni пишет:
>>>>>>>>>>>>> Tegra210 and prior Tegra PMC has clk_out_1, clk_out_2,
>>>>>>>>>>>>> clk_out_3 with
>>>>>>>>>>>>> mux and gate for each of these clocks.
>>>>>>>>>>>>>
>>>>>>>>>>>>> Currently these PMC clocks are registered by Tegra clock
>>>>>>>>>>>>> driver using
>>>>>>>>>>>>> clk_register_mux and clk_register_gate by passing PMC base
>>>>>>>>>>>>> address
>>>>>>>>>>>>> and register offsets and PMC programming for these clocks
>>>>>>>>>>>>> happens
>>>>>>>>>>>>> through direct PMC access by the clock driver.
>>>>>>>>>>>>>
>>>>>>>>>>>>> With this, when PMC is in secure mode any direct PMC access
>>>>>>>>>>>>> from the
>>>>>>>>>>>>> non-secure world does not go through and these clocks will
>>>>>>>>>>>>> not be
>>>>>>>>>>>>> functional.
>>>>>>>>>>>>>
>>>>>>>>>>>>> This patch adds these clocks registration with PMC as a clock
>>>>>>>>>>>>> provider
>>>>>>>>>>>>> for these clocks. clk_ops callback implementations for these
>>>>>>>>>>>>> clocks
>>>>>>>>>>>>> uses tegra_pmc_readl and tegra_pmc_writel which supports PMC
>>>>>>>>>>>>> programming
>>>>>>>>>>>>> in secure mode and non-secure mode.
>>>>>>>>>>>>>
>>>>>>>>>>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>>>>>>>>>>> ---
>>>>>>>>>>>>>      drivers/soc/tegra/pmc.c | 330
>>>>>>>>>>>>> ++++++++++++++++++++++++++++++++++++++++++++++++
>>>>>>>>>>>>>      1 file changed, 330 insertions(+)
>>>>>>>>>>>>>
>>>>>>>>>>>>> diff --git a/drivers/soc/tegra/pmc.c 
>>>>>>>>>>>>> b/drivers/soc/tegra/pmc.c
>>>>>>>>>>>>> index ea0e11a09c12..a353f6d0a832 100644
>>>>>>>>>>>>> --- a/drivers/soc/tegra/pmc.c
>>>>>>>>>>>>> +++ b/drivers/soc/tegra/pmc.c
>>>>>>>>>>>>> @@ -13,6 +13,9 @@
>>>>>>>>>>>>>        #include <linux/arm-smccc.h>
>>>>>>>>>>>>>      #include <linux/clk.h>
>>>>>>>>>>>>> +#include <linux/clk-provider.h>
>>>>>>>>>>>>> +#include <linux/clkdev.h>
>>>>>>>>>>>>> +#include <linux/clk/clk-conf.h>
>>>>>>>>>>>>>      #include <linux/clk/tegra.h>
>>>>>>>>>>>>>      #include <linux/debugfs.h>
>>>>>>>>>>>>>      #include <linux/delay.h>
>>>>>>>>>>>>> @@ -48,6 +51,7 @@
>>>>>>>>>>>>>      #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
>>>>>>>>>>>>>      #include <dt-bindings/gpio/tegra186-gpio.h>
>>>>>>>>>>>>>      #include <dt-bindings/gpio/tegra194-gpio.h>
>>>>>>>>>>>>> +#include <dt-bindings/soc/tegra-pmc.h>
>>>>>>>>>>>>>        #define PMC_CNTRL            0x0
>>>>>>>>>>>>>      #define  PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR
>>>>>>>>>>>>> polarity */
>>>>>>>>>>>>> @@ -100,6 +104,7 @@
>>>>>>>>>>>>>      #define PMC_WAKE2_STATUS        0x168
>>>>>>>>>>>>>      #define PMC_SW_WAKE2_STATUS 0x16c
>>>>>>>>>>>>>      +#define PMC_CLK_OUT_CNTRL 0x1a8
>>>>>>>>>>>>>      #define PMC_SENSOR_CTRL 0x1b0
>>>>>>>>>>>>>      #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2)
>>>>>>>>>>>>>      #define  PMC_SENSOR_CTRL_ENABLE_RST BIT(1)
>>>>>>>>>>>>> @@ -155,6 +160,91 @@
>>>>>>>>>>>>>      #define  TEGRA_SMC_PMC_READ    0xaa
>>>>>>>>>>>>>      #define  TEGRA_SMC_PMC_WRITE    0xbb
>>>>>>>>>>>>>      +struct pmc_clk_mux {
>>>>>>>>>>>>> +    struct clk_hw    hw;
>>>>>>>>>>>>> +    unsigned long    offs;
>>>>>>>>>>>>> +    u32        mask;
>>>>>>>>>>>>> +    u32        shift;
>>>>>>>>>>>>> +};
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +#define to_pmc_clk_mux(_hw) container_of(_hw, struct
>>>>>>>>>>>>> pmc_clk_mux, hw)
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +struct pmc_clk_gate {
>>>>>>>>>>>>> +    struct clk_hw    hw;
>>>>>>>>>>>>> +    unsigned long    offs;
>>>>>>>>>>>>> +    u32        shift;
>>>>>>>>>>>>> +};
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +#define to_pmc_clk_gate(_hw) container_of(_hw, struct
>>>>>>>>>>>>> pmc_clk_gate, hw)
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +struct pmc_clk_init_data {
>>>>>>>>>>>>> +    char *mux_name;
>>>>>>>>>>>>> +    char *gate_name;
>>>>>>>>>>>>> +    const char **parents;
>>>>>>>>>>>>> +    int num_parents;
>>>>>>>>>>>>> +    int mux_id;
>>>>>>>>>>>>> +    int gate_id;
>>>>>>>>>>>>> +    char *dev_name;
>>>>>>>>>>>>> +    u8 mux_shift;
>>>>>>>>>>>>> +    u8 gate_shift;
>>>>>>>>>>>>> +    u8 init_parent_index;
>>>>>>>>>>>>> +    int init_state;
>>>>>>>>>>>>> +};
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +static const char *clk_out1_parents[] = { "clk_m",
>>>>>>>>>>>>> "clk_m_div2",
>>>>>>>>>>>>> +    "clk_m_div4", "extern1",
>>>>>>>>>>>>> +};
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +static const char *clk_out2_parents[] = { "clk_m",
>>>>>>>>>>>>> "clk_m_div2",
>>>>>>>>>>>>> +    "clk_m_div4", "extern2",
>>>>>>>>>>>>> +};
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +static const char *clk_out3_parents[] = { "clk_m",
>>>>>>>>>>>>> "clk_m_div2",
>>>>>>>>>>>>> +    "clk_m_div4", "extern3",
>>>>>>>>>>>>> +};
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +static struct pmc_clk_init_data tegra_pmc_clks_data[] = {
>>>>>>>>>>>>> +    {
>>>>>>>>>>>>> +        .mux_name = "clk_out_1_mux",
>>>>>>>>>>>>> +        .gate_name = "clk_out_1",
>>>>>>>>>>>>> +        .parents = clk_out1_parents,
>>>>>>>>>>>>> +        .num_parents = ARRAY_SIZE(clk_out1_parents),
>>>>>>>>>>>>> +        .mux_id = TEGRA_PMC_CLK_OUT_1_MUX,
>>>>>>>>>>>>> +        .gate_id = TEGRA_PMC_CLK_OUT_1,
>>>>>>>>>>>>> +        .dev_name = "extern1",
>>>>>>>>>>>>> +        .mux_shift = 6,
>>>>>>>>>>>>> +        .gate_shift = 2,
>>>>>>>>>>>>> +        .init_parent_index = 3,
>>>>>>>>>>>>> +        .init_state = 1,
>>>>>>>>>>>>> +    },
>>>>>>>>>>>>> +    {
>>>>>>>>>>>>> +        .mux_name = "clk_out_2_mux",
>>>>>>>>>>>>> +        .gate_name = "clk_out_2",
>>>>>>>>>>>>> +        .parents = clk_out2_parents,
>>>>>>>>>>>>> +        .num_parents = ARRAY_SIZE(clk_out2_parents),
>>>>>>>>>>>>> +        .mux_id = TEGRA_PMC_CLK_OUT_2_MUX,
>>>>>>>>>>>>> +        .gate_id = TEGRA_PMC_CLK_OUT_2,
>>>>>>>>>>>>> +        .dev_name = "extern2",
>>>>>>>>>>>>> +        .mux_shift = 14,
>>>>>>>>>>>>> +        .gate_shift = 10,
>>>>>>>>>>>>> +        .init_parent_index = 0,
>>>>>>>>>>>>> +        .init_state = 0,
>>>>>>>>>>>>> +    },
>>>>>>>>>>>>> +    {
>>>>>>>>>>>>> +        .mux_name = "clk_out_3_mux",
>>>>>>>>>>>>> +        .gate_name = "clk_out_3",
>>>>>>>>>>>>> +        .parents = clk_out3_parents,
>>>>>>>>>>>>> +        .num_parents = ARRAY_SIZE(clk_out3_parents),
>>>>>>>>>>>>> +        .mux_id = TEGRA_PMC_CLK_OUT_3_MUX,
>>>>>>>>>>>>> +        .gate_id = TEGRA_PMC_CLK_OUT_3,
>>>>>>>>>>>>> +        .dev_name = "extern3",
>>>>>>>>>>>>> +        .mux_shift = 22,
>>>>>>>>>>>>> +        .gate_shift = 18,
>>>>>>>>>>>>> +        .init_parent_index = 0,
>>>>>>>>>>>>> +        .init_state = 0,
>>>>>>>>>>>>> +    },
>>>>>>>>>>>>> +};
>>>>>>>>>>>>> +
>>>>>>>>>>>>>      struct tegra_powergate {
>>>>>>>>>>>>>          struct generic_pm_domain genpd;
>>>>>>>>>>>>>          struct tegra_pmc *pmc;
>>>>>>>>>>>>> @@ -254,6 +344,9 @@ struct tegra_pmc_soc {
>>>>>>>>>>>>>           */
>>>>>>>>>>>>>          const struct tegra_wake_event *wake_events;
>>>>>>>>>>>>>          unsigned int num_wake_events;
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +    struct pmc_clk_init_data *pmc_clks_data;
>>>>>>>>>>>>> +    unsigned int num_pmc_clks;
>>>>>>>>>>>>>      };
>>>>>>>>>>>>>        static const char * const tegra186_reset_sources[] = {
>>>>>>>>>>>>> @@ -2163,6 +2256,228 @@ static int
>>>>>>>>>>>>> tegra_pmc_clk_notify_cb(struct
>>>>>>>>>>>>> notifier_block *nb,
>>>>>>>>>>>>>          return NOTIFY_OK;
>>>>>>>>>>>>>      }
>>>>>>>>>>>>>      +static void pmc_clk_fence_udelay(u32 offset)
>>>>>>>>>>>>> +{
>>>>>>>>>>>>> +    tegra_pmc_readl(pmc, offset);
>>>>>>>>>>>>> +    /* pmc clk propagation delay 2 us */
>>>>>>>>>>>>> +    udelay(2);
>>>>>>>>>>>>> +}
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
>>>>>>>>>>>>> +{
>>>>>>>>>>>>> +    struct pmc_clk_mux *mux = to_pmc_clk_mux(hw);
>>>>>>>>>>>>> +    int num_parents = clk_hw_get_num_parents(hw);
>>>>>>>>>>>>> +    u32 val;
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +    val = tegra_pmc_readl(pmc, mux->offs) >> mux->shift;
>>>>>>>>>>>>> +    val &= mux->mask;
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +    if (val >= num_parents)
>>>>>>>>>>>>> +        return -EINVAL;
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +    return val;
>>>>>>>>>>>>> +}
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 
>>>>>>>>>>>>> index)
>>>>>>>>>>>>> +{
>>>>>>>>>>>>> +    struct pmc_clk_mux *mux = to_pmc_clk_mux(hw);
>>>>>>>>>>>>> +    u32 val;
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +    val = tegra_pmc_readl(pmc, mux->offs);
>>>>>>>>>>>>> +    val &= ~(mux->mask << mux->shift);
>>>>>>>>>>>>> +    val |= index << mux->shift;
>>>>>>>>>>>>> +    tegra_pmc_writel(pmc, val, mux->offs);
>>>>>>>>>>>>> +    pmc_clk_fence_udelay(mux->offs);
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +    return 0;
>>>>>>>>>>>>> +}
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +static const struct clk_ops pmc_clk_mux_ops = {
>>>>>>>>>>>>> +    .get_parent = pmc_clk_mux_get_parent,
>>>>>>>>>>>>> +    .set_parent = pmc_clk_mux_set_parent,
>>>>>>>>>>>>> +    .determine_rate = __clk_mux_determine_rate,
>>>>>>>>>>>>> +};
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +static struct clk *
>>>>>>>>>>>>> +tegra_pmc_clk_mux_register(const char *name, const char * 
>>>>>>>>>>>>> const
>>>>>>>>>>>>> *parent_names,
>>>>>>>>>>>>> +               int num_parents, unsigned long flags,
>>>>>>>>>>>>> +               unsigned long offset, u32 shift, u32 mask)
>>>>>>>>>>>>> +{
>>>>>>>>>>>>> +    struct clk_init_data init;
>>>>>>>>>>>>> +    struct pmc_clk_mux *mux;
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +    mux = kzalloc(sizeof(*mux), GFP_KERNEL);
>>>>>>>>>>>>> +    if (!mux)
>>>>>>>>>>>>> +        return ERR_PTR(-ENOMEM);
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +    init.name = name;
>>>>>>>>>>>>> +    init.ops = &pmc_clk_mux_ops;
>>>>>>>>>>>>> +    init.parent_names = parent_names;
>>>>>>>>>>>>> +    init.num_parents = num_parents;
>>>>>>>>>>>>> +    init.flags = flags;
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +    mux->hw.init = &init;
>>>>>>>>>>>>> +    mux->offs = offset;
>>>>>>>>>>>>> +    mux->mask = mask;
>>>>>>>>>>>>> +    mux->shift = shift;
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +    return clk_register(NULL, &mux->hw);
>>>>>>>>>>>>> +}
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +static int pmc_clk_is_enabled(struct clk_hw *hw)
>>>>>>>>>>>>> +{
>>>>>>>>>>>>> +    struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +    return tegra_pmc_readl(pmc, gate->offs) &
>>>>>>>>>>>>> BIT(gate->shift) ? 1
>>>>>>>>>>>>> : 0;
>>>>>>>>>>>>> +}
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +static void pmc_clk_set_state(struct clk_hw *hw, int state)
>>>>>>>>>>>>> +{
>>>>>>>>>>>>> +    struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
>>>>>>>>>>>>> +    u32 val;
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +    val = tegra_pmc_readl(pmc, gate->offs);
>>>>>>>>>>>>> +    val = state ? (val | BIT(gate->shift)) : (val &
>>>>>>>>>>>>> ~BIT(gate->shift));
>>>>>>>>>>>>> +    tegra_pmc_writel(pmc, val, gate->offs);
>>>>>>>>>>>>> +    pmc_clk_fence_udelay(gate->offs);
>>>>>>>>>>>>> +}
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +static int pmc_clk_enable(struct clk_hw *hw)
>>>>>>>>>>>>> +{
>>>>>>>>>>>>> +    pmc_clk_set_state(hw, 1);
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +    return 0;
>>>>>>>>>>>>> +}
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +static void pmc_clk_disable(struct clk_hw *hw)
>>>>>>>>>>>>> +{
>>>>>>>>>>>>> +    pmc_clk_set_state(hw, 0);
>>>>>>>>>>>>> +}
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +static const struct clk_ops pmc_clk_gate_ops = {
>>>>>>>>>>>>> +    .is_enabled = pmc_clk_is_enabled,
>>>>>>>>>>>>> +    .enable = pmc_clk_enable,
>>>>>>>>>>>>> +    .disable = pmc_clk_disable,
>>>>>>>>>>>>> +};
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +static struct clk *
>>>>>>>>>>>>> +tegra_pmc_clk_gate_register(const char *name, const char
>>>>>>>>>>>>> *parent_name,
>>>>>>>>>>>>> +                unsigned long flags, unsigned long offset,
>>>>>>>>>>>>> +                u32 shift)
>>>>>>>>>>>>> +{
>>>>>>>>>>>>> +    struct clk_init_data init;
>>>>>>>>>>>>> +    struct pmc_clk_gate *gate;
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +    gate = kzalloc(sizeof(*gate), GFP_KERNEL);
>>>>>>>>>>>>> +    if (!gate)
>>>>>>>>>>>>> +        return ERR_PTR(-ENOMEM);
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +    init.name = name;
>>>>>>>>>>>>> +    init.ops = &pmc_clk_gate_ops;
>>>>>>>>>>>>> +    init.parent_names = &parent_name;
>>>>>>>>>>>>> +    init.num_parents = 1;
>>>>>>>>>>>>> +    init.flags = flags;
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +    gate->hw.init = &init;
>>>>>>>>>>>>> +    gate->offs = offset;
>>>>>>>>>>>>> +    gate->shift = shift;
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +    return clk_register(NULL, &gate->hw);
>>>>>>>>>>>>> +}
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
>>>>>>>>>>>>> +                     struct device_node *np)
>>>>>>>>>>>>> +{
>>>>>>>>>>>>> +    struct clk *clkmux, *clk, *parent;
>>>>>>>>>>>>> +    struct clk_onecell_data *clk_data;
>>>>>>>>>>>>> +    unsigned int num_clks;
>>>>>>>>>>>>> +    int i, ret;
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +    /* each pmc clock output has a mux and a gate */
>>>>>>>>>>>>> +    num_clks = pmc->soc->num_pmc_clks * 2;
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +    if (!num_clks)
>>>>>>>>>>>>> +        return;
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +    clk_data = kmalloc(sizeof(*clk_data), GFP_KERNEL);
>>>>>>>>>>>>> +    if (!clk_data)
>>>>>>>>>>>>> +        return;
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +    clk_data->clks = kcalloc(TEGRA_PMC_CLK_MAX,
>>>>>>>>>>>>> sizeof(*clk_data->clks),
>>>>>>>>>>>>> +                 GFP_KERNEL);
>>>>>>>>>>>>> +    if (!clk_data->clks)
>>>>>>>>>>>>> +        goto free_clkdata;
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +    clk_data->clk_num = num_clks;
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +    for (i = 0; i < pmc->soc->num_pmc_clks; i++) {
>>>>>>>>>>>>> +        struct pmc_clk_init_data *data;
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +        data = pmc->soc->pmc_clks_data + i;
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +        clkmux = tegra_pmc_clk_mux_register(data->mux_name,
>>>>>>>>>>>>> + data->parents,
>>>>>>>>>>>>> + data->num_parents,
>>>>>>>>>>>>> + CLK_SET_RATE_NO_REPARENT |
>>>>>>>>>>>>> + CLK_SET_RATE_PARENT,
>>>>>>>>>>>>> + PMC_CLK_OUT_CNTRL,
>>>>>>>>>>>>> + data->mux_shift, 3);
>>>>>>>>>>>>> +        if (IS_ERR(clkmux))
>>>>>>>>>>>>> +            goto free_clks;
>>>>>>>>>>>>> +
>>>>>>>>>>>>> + clk_data->clks[data->mux_id] = clkmux;
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +        clk = tegra_pmc_clk_gate_register(data->gate_name,
>>>>>>>>>>>>> + data->mux_name,
>>>>>>>>>>>>> + CLK_SET_RATE_PARENT,
>>>>>>>>>>>>> + PMC_CLK_OUT_CNTRL,
>>>>>>>>>>>>> + data->gate_shift);
>>>>>>>>>>>>> +        if (IS_ERR(clk))
>>>>>>>>>>>>> +            goto free_clks;
>>>>>>>>>>>>> +
>>>>>>>>>>>>> + clk_data->clks[data->gate_id] = clk;
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +        ret = clk_set_parent(clk, clkmux);
>>>>>>>>>>>>> +        if (ret < 0) {
>>>>>>>>>>>>> +            pr_err("failed to set parent of %s to %s\n",
>>>>>>>>>>>>> +                   __func__, __clk_get_name(clk),
>>>>>>>>>>>>> + __clk_get_name(clkmux));
>>>>>>>>>>>>> +        }
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +        clk_register_clkdev(clk, data->dev_name,
>>>>>>>>>>>>> data->gate_name);
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +        /* configure initial clock parent and state */
>>>>>>>>>>>>> +        parent = clk_get_sys(data->gate_name,
>>>>>>>>>>>>> + data->parents[data->init_parent_index]);
>>>>>>>> Couldn't the default parent be defined using "assigned clock" in a
>>>>>>>> device-tree? Please see "Assigned clock parents and rates" in the
>>>>>>>> doc.
>>>>>>>>
>>>>>>>> https://www.kernel.org/doc/Documentation/devicetree/bindings/clock/clock-bindings.txt 
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>> Then you could simply use of_clk_set_defaults(pmc->dev->of_node,
>>>>>>>> true).
>>>>>>> Yes, of_clk_add_provider() does of_clk_set_defaults which sets
>>>>>>> based on assigned parents and clock rates.
>>>>>>>
>>>>>>> This need device tree to specify assigned clock parent properties.
>>>>>>> Will update device tree and remove init parent from the driver.
>>>>>>>
>>>>>> assigned-clock properties should be set in consumer node of these
>>>>>> clocks and currently these clocks are not used yet.
>>>>>>
>>>>>> So will just remove init parent from driver and when these clocks
>>>>>> are used device tree can be updated in corresponding consumer node
>>>>>> with these properties.
>>>>>>
>>>>> How about default ON/OFF init state for the clocks? I see
>>>>> assigned-clock properties for parent and rate only.
>>>>>
>>>>> But based on existing clock-tegra-pmc driver, I see clk_out_1 is
>>>>> default enabled with extern1 parent for T30 thru T210 platforms.
>>>>>
>>>>> Peter/Thierry, What was the reason we enable clk_out_1 right from the
>>>>> clock registration?
>>>>>
>>>> clk_out_1 is for audio and its not required to be enabled during the
>>>> boot and audio driver can enable/disable it.
>>>>
>>>> same with blink 32khz which is used for WIFI. WIFI driver can
>>>> enable/disable during power up/down sequence and technically as per
>>>> design we dont need to have it always on right from the boot.
>>>>
>>>> So can remove out clocks init states from driver once thierry also
>>>> agree on this.
>>>>
>>> Hi Dmitry,
>>>
>>> Looking at audio driver, it doesn't take care of mclk which is from
>>> clk_out_1 and expects mclk to be always on.
>>>
>>> So probably we should have this init state enables in pmc driver for
>>> 32Khz and clk_out's to not break existing functionality.
>> Hello Sowjanya,
>>
>> IIUC, it's a bug in the device-trees and sound's MCLK actually should be
>> set to CLK_OUT_1 of PMC instead of CaR's EXTPERIPH1. If that's the case,
>> then the device-trees need to be fixed.
>
> OK, will have this in v3

Actually if we change mclk to use clk_out_1, then it will break with old 
device trees.

Currently clk_out_1 parent is set to extern1 as init state by the clock 
driver and device tree for sound node is using extern1 as mclk works and 
extern1 itself has enable and disable. But yes implementation wise, its 
incorrect as mclk should really be clk_out_1.

Now, with moving clk_out_1 to tegra PMC, pmc is the clock provider and 
if we now change the device tree to use CLK_OUT_1 as mclk then it will 
break old device tree.

>
>>> Regarding using assigned-clock properties for init parent and removing
>>> init parent from driver, it also needs consumer node in device tree to
>>> be updated to specify assigned-clock properties for default/init 
>>> parent.
>>>
>>> This breaks device tree ABI as prior Tegra210 supports audio driver.
>> So it's the sound node which should have had the assigned clocks in
>> device-tree in order to define route for the audio MCLK clock from CaR
>> to PMC.
>>
>> Given that the audio clocks configuration is the same for all of the
>> currently supported boards, I think it will be better to remove the
>> entire audio clocks initialization from the clk drivers and move it all
>> to the audio driver. It could be something like this:
>>
>> int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data,
>>               struct device *dev)
>> {
>>     ...
>>
>>     if (!of_find_property(dev->of_node, "assigned-clock-parents", 
>> NULL) &&
>>         tegra_get_chip_id() > TEGRA20) {
>>         clk_extern1 = clk_get(dev, "extern1");
>>         ...
>>         clk_set_parent(clk_extern1, clk_pll_a_out0);
>>         ...
>>         clk_put(data->clk_cdev1);
>>
>>         data->clk_cdev1 = clk_out_1;
>>     }
>>     ...
>>
>> So now the old device-trees will cointinue to work and new could have
>> the assigned-clocks and set MCLK to CLK_OUT_1.
>>
>> [snip]
>
> Will update clk-tegra, pmc and audio driver to move init state 
> configuration for extern1 and clk_out_1 into audio driver and will use 
> assigned clock properties in device tree.
>

04.12.2019 23:08, Sowjanya Komatineni пишет:
> 
> On 12/4/19 8:02 AM, Sowjanya Komatineni wrote:
>>
>> On 12/4/19 5:39 AM, Dmitry Osipenko wrote:
>>> 03.12.2019 19:45, Sowjanya Komatineni пишет:
>>>> On 12/2/19 4:07 PM, Sowjanya Komatineni wrote:
>>>>> On 12/2/19 3:14 PM, Sowjanya Komatineni wrote:
>>>>>> On 12/2/19 3:10 PM, Sowjanya Komatineni wrote:
>>>>>>> On 12/2/19 2:58 PM, Sowjanya Komatineni wrote:
>>>>>>>> On 12/2/19 1:50 PM, Dmitry Osipenko wrote:
>>>>>>>>> 02.12.2019 23:09, Sowjanya Komatineni пишет:
>>>>>>>>>> On 11/28/19 5:25 AM, Dmitry Osipenko wrote:
>>>>>>>>>>> 28.11.2019 01:57, Sowjanya Komatineni пишет:
>>>>>>>>>>>> On 11/27/19 7:14 AM, Dmitry Osipenko wrote:
>>>>>>>>>>>>> 27.11.2019 07:59, Sowjanya Komatineni пишет:
>>>>>>>>>>>>>> Tegra210 and prior Tegra PMC has clk_out_1, clk_out_2,
>>>>>>>>>>>>>> clk_out_3 with
>>>>>>>>>>>>>> mux and gate for each of these clocks.
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> Currently these PMC clocks are registered by Tegra clock
>>>>>>>>>>>>>> driver using
>>>>>>>>>>>>>> clk_register_mux and clk_register_gate by passing PMC base
>>>>>>>>>>>>>> address
>>>>>>>>>>>>>> and register offsets and PMC programming for these clocks
>>>>>>>>>>>>>> happens
>>>>>>>>>>>>>> through direct PMC access by the clock driver.
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> With this, when PMC is in secure mode any direct PMC access
>>>>>>>>>>>>>> from the
>>>>>>>>>>>>>> non-secure world does not go through and these clocks will
>>>>>>>>>>>>>> not be
>>>>>>>>>>>>>> functional.
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> This patch adds these clocks registration with PMC as a clock
>>>>>>>>>>>>>> provider
>>>>>>>>>>>>>> for these clocks. clk_ops callback implementations for these
>>>>>>>>>>>>>> clocks
>>>>>>>>>>>>>> uses tegra_pmc_readl and tegra_pmc_writel which supports PMC
>>>>>>>>>>>>>> programming
>>>>>>>>>>>>>> in secure mode and non-secure mode.
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>>>>>>>>>>>> ---
>>>>>>>>>>>>>>      drivers/soc/tegra/pmc.c | 330
>>>>>>>>>>>>>> ++++++++++++++++++++++++++++++++++++++++++++++++
>>>>>>>>>>>>>>      1 file changed, 330 insertions(+)
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> diff --git a/drivers/soc/tegra/pmc.c
>>>>>>>>>>>>>> b/drivers/soc/tegra/pmc.c
>>>>>>>>>>>>>> index ea0e11a09c12..a353f6d0a832 100644
>>>>>>>>>>>>>> --- a/drivers/soc/tegra/pmc.c
>>>>>>>>>>>>>> +++ b/drivers/soc/tegra/pmc.c
>>>>>>>>>>>>>> @@ -13,6 +13,9 @@
>>>>>>>>>>>>>>        #include <linux/arm-smccc.h>
>>>>>>>>>>>>>>      #include <linux/clk.h>
>>>>>>>>>>>>>> +#include <linux/clk-provider.h>
>>>>>>>>>>>>>> +#include <linux/clkdev.h>
>>>>>>>>>>>>>> +#include <linux/clk/clk-conf.h>
>>>>>>>>>>>>>>      #include <linux/clk/tegra.h>
>>>>>>>>>>>>>>      #include <linux/debugfs.h>
>>>>>>>>>>>>>>      #include <linux/delay.h>
>>>>>>>>>>>>>> @@ -48,6 +51,7 @@
>>>>>>>>>>>>>>      #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
>>>>>>>>>>>>>>      #include <dt-bindings/gpio/tegra186-gpio.h>
>>>>>>>>>>>>>>      #include <dt-bindings/gpio/tegra194-gpio.h>
>>>>>>>>>>>>>> +#include <dt-bindings/soc/tegra-pmc.h>
>>>>>>>>>>>>>>        #define PMC_CNTRL            0x0
>>>>>>>>>>>>>>      #define  PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR
>>>>>>>>>>>>>> polarity */
>>>>>>>>>>>>>> @@ -100,6 +104,7 @@
>>>>>>>>>>>>>>      #define PMC_WAKE2_STATUS        0x168
>>>>>>>>>>>>>>      #define PMC_SW_WAKE2_STATUS 0x16c
>>>>>>>>>>>>>>      +#define PMC_CLK_OUT_CNTRL 0x1a8
>>>>>>>>>>>>>>      #define PMC_SENSOR_CTRL 0x1b0
>>>>>>>>>>>>>>      #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2)
>>>>>>>>>>>>>>      #define  PMC_SENSOR_CTRL_ENABLE_RST BIT(1)
>>>>>>>>>>>>>> @@ -155,6 +160,91 @@
>>>>>>>>>>>>>>      #define  TEGRA_SMC_PMC_READ    0xaa
>>>>>>>>>>>>>>      #define  TEGRA_SMC_PMC_WRITE    0xbb
>>>>>>>>>>>>>>      +struct pmc_clk_mux {
>>>>>>>>>>>>>> +    struct clk_hw    hw;
>>>>>>>>>>>>>> +    unsigned long    offs;
>>>>>>>>>>>>>> +    u32        mask;
>>>>>>>>>>>>>> +    u32        shift;
>>>>>>>>>>>>>> +};
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +#define to_pmc_clk_mux(_hw) container_of(_hw, struct
>>>>>>>>>>>>>> pmc_clk_mux, hw)
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +struct pmc_clk_gate {
>>>>>>>>>>>>>> +    struct clk_hw    hw;
>>>>>>>>>>>>>> +    unsigned long    offs;
>>>>>>>>>>>>>> +    u32        shift;
>>>>>>>>>>>>>> +};
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +#define to_pmc_clk_gate(_hw) container_of(_hw, struct
>>>>>>>>>>>>>> pmc_clk_gate, hw)
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +struct pmc_clk_init_data {
>>>>>>>>>>>>>> +    char *mux_name;
>>>>>>>>>>>>>> +    char *gate_name;
>>>>>>>>>>>>>> +    const char **parents;
>>>>>>>>>>>>>> +    int num_parents;
>>>>>>>>>>>>>> +    int mux_id;
>>>>>>>>>>>>>> +    int gate_id;
>>>>>>>>>>>>>> +    char *dev_name;
>>>>>>>>>>>>>> +    u8 mux_shift;
>>>>>>>>>>>>>> +    u8 gate_shift;
>>>>>>>>>>>>>> +    u8 init_parent_index;
>>>>>>>>>>>>>> +    int init_state;
>>>>>>>>>>>>>> +};
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +static const char *clk_out1_parents[] = { "clk_m",
>>>>>>>>>>>>>> "clk_m_div2",
>>>>>>>>>>>>>> +    "clk_m_div4", "extern1",
>>>>>>>>>>>>>> +};
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +static const char *clk_out2_parents[] = { "clk_m",
>>>>>>>>>>>>>> "clk_m_div2",
>>>>>>>>>>>>>> +    "clk_m_div4", "extern2",
>>>>>>>>>>>>>> +};
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +static const char *clk_out3_parents[] = { "clk_m",
>>>>>>>>>>>>>> "clk_m_div2",
>>>>>>>>>>>>>> +    "clk_m_div4", "extern3",
>>>>>>>>>>>>>> +};
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +static struct pmc_clk_init_data tegra_pmc_clks_data[] = {
>>>>>>>>>>>>>> +    {
>>>>>>>>>>>>>> +        .mux_name = "clk_out_1_mux",
>>>>>>>>>>>>>> +        .gate_name = "clk_out_1",
>>>>>>>>>>>>>> +        .parents = clk_out1_parents,
>>>>>>>>>>>>>> +        .num_parents = ARRAY_SIZE(clk_out1_parents),
>>>>>>>>>>>>>> +        .mux_id = TEGRA_PMC_CLK_OUT_1_MUX,
>>>>>>>>>>>>>> +        .gate_id = TEGRA_PMC_CLK_OUT_1,
>>>>>>>>>>>>>> +        .dev_name = "extern1",
>>>>>>>>>>>>>> +        .mux_shift = 6,
>>>>>>>>>>>>>> +        .gate_shift = 2,
>>>>>>>>>>>>>> +        .init_parent_index = 3,
>>>>>>>>>>>>>> +        .init_state = 1,
>>>>>>>>>>>>>> +    },
>>>>>>>>>>>>>> +    {
>>>>>>>>>>>>>> +        .mux_name = "clk_out_2_mux",
>>>>>>>>>>>>>> +        .gate_name = "clk_out_2",
>>>>>>>>>>>>>> +        .parents = clk_out2_parents,
>>>>>>>>>>>>>> +        .num_parents = ARRAY_SIZE(clk_out2_parents),
>>>>>>>>>>>>>> +        .mux_id = TEGRA_PMC_CLK_OUT_2_MUX,
>>>>>>>>>>>>>> +        .gate_id = TEGRA_PMC_CLK_OUT_2,
>>>>>>>>>>>>>> +        .dev_name = "extern2",
>>>>>>>>>>>>>> +        .mux_shift = 14,
>>>>>>>>>>>>>> +        .gate_shift = 10,
>>>>>>>>>>>>>> +        .init_parent_index = 0,
>>>>>>>>>>>>>> +        .init_state = 0,
>>>>>>>>>>>>>> +    },
>>>>>>>>>>>>>> +    {
>>>>>>>>>>>>>> +        .mux_name = "clk_out_3_mux",
>>>>>>>>>>>>>> +        .gate_name = "clk_out_3",
>>>>>>>>>>>>>> +        .parents = clk_out3_parents,
>>>>>>>>>>>>>> +        .num_parents = ARRAY_SIZE(clk_out3_parents),
>>>>>>>>>>>>>> +        .mux_id = TEGRA_PMC_CLK_OUT_3_MUX,
>>>>>>>>>>>>>> +        .gate_id = TEGRA_PMC_CLK_OUT_3,
>>>>>>>>>>>>>> +        .dev_name = "extern3",
>>>>>>>>>>>>>> +        .mux_shift = 22,
>>>>>>>>>>>>>> +        .gate_shift = 18,
>>>>>>>>>>>>>> +        .init_parent_index = 0,
>>>>>>>>>>>>>> +        .init_state = 0,
>>>>>>>>>>>>>> +    },
>>>>>>>>>>>>>> +};
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>      struct tegra_powergate {
>>>>>>>>>>>>>>          struct generic_pm_domain genpd;
>>>>>>>>>>>>>>          struct tegra_pmc *pmc;
>>>>>>>>>>>>>> @@ -254,6 +344,9 @@ struct tegra_pmc_soc {
>>>>>>>>>>>>>>           */
>>>>>>>>>>>>>>          const struct tegra_wake_event *wake_events;
>>>>>>>>>>>>>>          unsigned int num_wake_events;
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +    struct pmc_clk_init_data *pmc_clks_data;
>>>>>>>>>>>>>> +    unsigned int num_pmc_clks;
>>>>>>>>>>>>>>      };
>>>>>>>>>>>>>>        static const char * const tegra186_reset_sources[] = {
>>>>>>>>>>>>>> @@ -2163,6 +2256,228 @@ static int
>>>>>>>>>>>>>> tegra_pmc_clk_notify_cb(struct
>>>>>>>>>>>>>> notifier_block *nb,
>>>>>>>>>>>>>>          return NOTIFY_OK;
>>>>>>>>>>>>>>      }
>>>>>>>>>>>>>>      +static void pmc_clk_fence_udelay(u32 offset)
>>>>>>>>>>>>>> +{
>>>>>>>>>>>>>> +    tegra_pmc_readl(pmc, offset);
>>>>>>>>>>>>>> +    /* pmc clk propagation delay 2 us */
>>>>>>>>>>>>>> +    udelay(2);
>>>>>>>>>>>>>> +}
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
>>>>>>>>>>>>>> +{
>>>>>>>>>>>>>> +    struct pmc_clk_mux *mux = to_pmc_clk_mux(hw);
>>>>>>>>>>>>>> +    int num_parents = clk_hw_get_num_parents(hw);
>>>>>>>>>>>>>> +    u32 val;
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +    val = tegra_pmc_readl(pmc, mux->offs) >> mux->shift;
>>>>>>>>>>>>>> +    val &= mux->mask;
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +    if (val >= num_parents)
>>>>>>>>>>>>>> +        return -EINVAL;
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +    return val;
>>>>>>>>>>>>>> +}
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8
>>>>>>>>>>>>>> index)
>>>>>>>>>>>>>> +{
>>>>>>>>>>>>>> +    struct pmc_clk_mux *mux = to_pmc_clk_mux(hw);
>>>>>>>>>>>>>> +    u32 val;
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +    val = tegra_pmc_readl(pmc, mux->offs);
>>>>>>>>>>>>>> +    val &= ~(mux->mask << mux->shift);
>>>>>>>>>>>>>> +    val |= index << mux->shift;
>>>>>>>>>>>>>> +    tegra_pmc_writel(pmc, val, mux->offs);
>>>>>>>>>>>>>> +    pmc_clk_fence_udelay(mux->offs);
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +    return 0;
>>>>>>>>>>>>>> +}
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +static const struct clk_ops pmc_clk_mux_ops = {
>>>>>>>>>>>>>> +    .get_parent = pmc_clk_mux_get_parent,
>>>>>>>>>>>>>> +    .set_parent = pmc_clk_mux_set_parent,
>>>>>>>>>>>>>> +    .determine_rate = __clk_mux_determine_rate,
>>>>>>>>>>>>>> +};
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +static struct clk *
>>>>>>>>>>>>>> +tegra_pmc_clk_mux_register(const char *name, const char *
>>>>>>>>>>>>>> const
>>>>>>>>>>>>>> *parent_names,
>>>>>>>>>>>>>> +               int num_parents, unsigned long flags,
>>>>>>>>>>>>>> +               unsigned long offset, u32 shift, u32 mask)
>>>>>>>>>>>>>> +{
>>>>>>>>>>>>>> +    struct clk_init_data init;
>>>>>>>>>>>>>> +    struct pmc_clk_mux *mux;
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +    mux = kzalloc(sizeof(*mux), GFP_KERNEL);
>>>>>>>>>>>>>> +    if (!mux)
>>>>>>>>>>>>>> +        return ERR_PTR(-ENOMEM);
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +    init.name = name;
>>>>>>>>>>>>>> +    init.ops = &pmc_clk_mux_ops;
>>>>>>>>>>>>>> +    init.parent_names = parent_names;
>>>>>>>>>>>>>> +    init.num_parents = num_parents;
>>>>>>>>>>>>>> +    init.flags = flags;
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +    mux->hw.init = &init;
>>>>>>>>>>>>>> +    mux->offs = offset;
>>>>>>>>>>>>>> +    mux->mask = mask;
>>>>>>>>>>>>>> +    mux->shift = shift;
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +    return clk_register(NULL, &mux->hw);
>>>>>>>>>>>>>> +}
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +static int pmc_clk_is_enabled(struct clk_hw *hw)
>>>>>>>>>>>>>> +{
>>>>>>>>>>>>>> +    struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +    return tegra_pmc_readl(pmc, gate->offs) &
>>>>>>>>>>>>>> BIT(gate->shift) ? 1
>>>>>>>>>>>>>> : 0;
>>>>>>>>>>>>>> +}
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +static void pmc_clk_set_state(struct clk_hw *hw, int state)
>>>>>>>>>>>>>> +{
>>>>>>>>>>>>>> +    struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
>>>>>>>>>>>>>> +    u32 val;
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +    val = tegra_pmc_readl(pmc, gate->offs);
>>>>>>>>>>>>>> +    val = state ? (val | BIT(gate->shift)) : (val &
>>>>>>>>>>>>>> ~BIT(gate->shift));
>>>>>>>>>>>>>> +    tegra_pmc_writel(pmc, val, gate->offs);
>>>>>>>>>>>>>> +    pmc_clk_fence_udelay(gate->offs);
>>>>>>>>>>>>>> +}
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +static int pmc_clk_enable(struct clk_hw *hw)
>>>>>>>>>>>>>> +{
>>>>>>>>>>>>>> +    pmc_clk_set_state(hw, 1);
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +    return 0;
>>>>>>>>>>>>>> +}
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +static void pmc_clk_disable(struct clk_hw *hw)
>>>>>>>>>>>>>> +{
>>>>>>>>>>>>>> +    pmc_clk_set_state(hw, 0);
>>>>>>>>>>>>>> +}
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +static const struct clk_ops pmc_clk_gate_ops = {
>>>>>>>>>>>>>> +    .is_enabled = pmc_clk_is_enabled,
>>>>>>>>>>>>>> +    .enable = pmc_clk_enable,
>>>>>>>>>>>>>> +    .disable = pmc_clk_disable,
>>>>>>>>>>>>>> +};
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +static struct clk *
>>>>>>>>>>>>>> +tegra_pmc_clk_gate_register(const char *name, const char
>>>>>>>>>>>>>> *parent_name,
>>>>>>>>>>>>>> +                unsigned long flags, unsigned long offset,
>>>>>>>>>>>>>> +                u32 shift)
>>>>>>>>>>>>>> +{
>>>>>>>>>>>>>> +    struct clk_init_data init;
>>>>>>>>>>>>>> +    struct pmc_clk_gate *gate;
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +    gate = kzalloc(sizeof(*gate), GFP_KERNEL);
>>>>>>>>>>>>>> +    if (!gate)
>>>>>>>>>>>>>> +        return ERR_PTR(-ENOMEM);
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +    init.name = name;
>>>>>>>>>>>>>> +    init.ops = &pmc_clk_gate_ops;
>>>>>>>>>>>>>> +    init.parent_names = &parent_name;
>>>>>>>>>>>>>> +    init.num_parents = 1;
>>>>>>>>>>>>>> +    init.flags = flags;
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +    gate->hw.init = &init;
>>>>>>>>>>>>>> +    gate->offs = offset;
>>>>>>>>>>>>>> +    gate->shift = shift;
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +    return clk_register(NULL, &gate->hw);
>>>>>>>>>>>>>> +}
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
>>>>>>>>>>>>>> +                     struct device_node *np)
>>>>>>>>>>>>>> +{
>>>>>>>>>>>>>> +    struct clk *clkmux, *clk, *parent;
>>>>>>>>>>>>>> +    struct clk_onecell_data *clk_data;
>>>>>>>>>>>>>> +    unsigned int num_clks;
>>>>>>>>>>>>>> +    int i, ret;
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +    /* each pmc clock output has a mux and a gate */
>>>>>>>>>>>>>> +    num_clks = pmc->soc->num_pmc_clks * 2;
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +    if (!num_clks)
>>>>>>>>>>>>>> +        return;
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +    clk_data = kmalloc(sizeof(*clk_data), GFP_KERNEL);
>>>>>>>>>>>>>> +    if (!clk_data)
>>>>>>>>>>>>>> +        return;
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +    clk_data->clks = kcalloc(TEGRA_PMC_CLK_MAX,
>>>>>>>>>>>>>> sizeof(*clk_data->clks),
>>>>>>>>>>>>>> +                 GFP_KERNEL);
>>>>>>>>>>>>>> +    if (!clk_data->clks)
>>>>>>>>>>>>>> +        goto free_clkdata;
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +    clk_data->clk_num = num_clks;
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +    for (i = 0; i < pmc->soc->num_pmc_clks; i++) {
>>>>>>>>>>>>>> +        struct pmc_clk_init_data *data;
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +        data = pmc->soc->pmc_clks_data + i;
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +        clkmux = tegra_pmc_clk_mux_register(data->mux_name,
>>>>>>>>>>>>>> + data->parents,
>>>>>>>>>>>>>> + data->num_parents,
>>>>>>>>>>>>>> + CLK_SET_RATE_NO_REPARENT |
>>>>>>>>>>>>>> + CLK_SET_RATE_PARENT,
>>>>>>>>>>>>>> + PMC_CLK_OUT_CNTRL,
>>>>>>>>>>>>>> + data->mux_shift, 3);
>>>>>>>>>>>>>> +        if (IS_ERR(clkmux))
>>>>>>>>>>>>>> +            goto free_clks;
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> + clk_data->clks[data->mux_id] = clkmux;
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +        clk = tegra_pmc_clk_gate_register(data->gate_name,
>>>>>>>>>>>>>> + data->mux_name,
>>>>>>>>>>>>>> + CLK_SET_RATE_PARENT,
>>>>>>>>>>>>>> + PMC_CLK_OUT_CNTRL,
>>>>>>>>>>>>>> + data->gate_shift);
>>>>>>>>>>>>>> +        if (IS_ERR(clk))
>>>>>>>>>>>>>> +            goto free_clks;
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> + clk_data->clks[data->gate_id] = clk;
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +        ret = clk_set_parent(clk, clkmux);
>>>>>>>>>>>>>> +        if (ret < 0) {
>>>>>>>>>>>>>> +            pr_err("failed to set parent of %s to %s\n",
>>>>>>>>>>>>>> +                   __func__, __clk_get_name(clk),
>>>>>>>>>>>>>> + __clk_get_name(clkmux));
>>>>>>>>>>>>>> +        }
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +        clk_register_clkdev(clk, data->dev_name,
>>>>>>>>>>>>>> data->gate_name);
>>>>>>>>>>>>>> +
>>>>>>>>>>>>>> +        /* configure initial clock parent and state */
>>>>>>>>>>>>>> +        parent = clk_get_sys(data->gate_name,
>>>>>>>>>>>>>> + data->parents[data->init_parent_index]);
>>>>>>>>> Couldn't the default parent be defined using "assigned clock" in a
>>>>>>>>> device-tree? Please see "Assigned clock parents and rates" in the
>>>>>>>>> doc.
>>>>>>>>>
>>>>>>>>> https://www.kernel.org/doc/Documentation/devicetree/bindings/clock/clock-bindings.txt
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> Then you could simply use of_clk_set_defaults(pmc->dev->of_node,
>>>>>>>>> true).
>>>>>>>> Yes, of_clk_add_provider() does of_clk_set_defaults which sets
>>>>>>>> based on assigned parents and clock rates.
>>>>>>>>
>>>>>>>> This need device tree to specify assigned clock parent properties.
>>>>>>>> Will update device tree and remove init parent from the driver.
>>>>>>>>
>>>>>>> assigned-clock properties should be set in consumer node of these
>>>>>>> clocks and currently these clocks are not used yet.
>>>>>>>
>>>>>>> So will just remove init parent from driver and when these clocks
>>>>>>> are used device tree can be updated in corresponding consumer node
>>>>>>> with these properties.
>>>>>>>
>>>>>> How about default ON/OFF init state for the clocks? I see
>>>>>> assigned-clock properties for parent and rate only.
>>>>>>
>>>>>> But based on existing clock-tegra-pmc driver, I see clk_out_1 is
>>>>>> default enabled with extern1 parent for T30 thru T210 platforms.
>>>>>>
>>>>>> Peter/Thierry, What was the reason we enable clk_out_1 right from the
>>>>>> clock registration?
>>>>>>
>>>>> clk_out_1 is for audio and its not required to be enabled during the
>>>>> boot and audio driver can enable/disable it.
>>>>>
>>>>> same with blink 32khz which is used for WIFI. WIFI driver can
>>>>> enable/disable during power up/down sequence and technically as per
>>>>> design we dont need to have it always on right from the boot.
>>>>>
>>>>> So can remove out clocks init states from driver once thierry also
>>>>> agree on this.
>>>>>
>>>> Hi Dmitry,
>>>>
>>>> Looking at audio driver, it doesn't take care of mclk which is from
>>>> clk_out_1 and expects mclk to be always on.
>>>>
>>>> So probably we should have this init state enables in pmc driver for
>>>> 32Khz and clk_out's to not break existing functionality.
>>> Hello Sowjanya,
>>>
>>> IIUC, it's a bug in the device-trees and sound's MCLK actually should be
>>> set to CLK_OUT_1 of PMC instead of CaR's EXTPERIPH1. If that's the case,
>>> then the device-trees need to be fixed.
>>
>> OK, will have this in v3
> 
> Actually if we change mclk to use clk_out_1, then it will break with old
> device trees.
> 
> Currently clk_out_1 parent is set to extern1 as init state by the clock
> driver and device tree for sound node is using extern1 as mclk works and
> extern1 itself has enable and disable. But yes implementation wise, its
> incorrect as mclk should really be clk_out_1.
> 
> Now, with moving clk_out_1 to tegra PMC, pmc is the clock provider and
> if we now change the device tree to use CLK_OUT_1 as mclk then it will
> break old device tree.

There souldn't be any problem with enabling CLK_OUT_1 by the audio
driver itself (in the code) if an old device-tree is detected.

	clk_out_1 = clk_get(dev, "clk_out_1");
	clk_set_parent(clk_out_1, clk_extern1);
	...
	data->clk_cdev1 = clk_out_1;

Maybe it will be even better to compare clocks for detection of an older DT:

	if (tegra_get_chip_id() > TEGRA20 &&
	    clk_is_match(data->clk_cdev1, clk_extern1)) {
	...

>>>> Regarding using assigned-clock properties for init parent and removing
>>>> init parent from driver, it also needs consumer node in device tree to
>>>> be updated to specify assigned-clock properties for default/init
>>>> parent.
>>>>
>>>> This breaks device tree ABI as prior Tegra210 supports audio driver.
>>> So it's the sound node which should have had the assigned clocks in
>>> device-tree in order to define route for the audio MCLK clock from CaR
>>> to PMC.
>>>
>>> Given that the audio clocks configuration is the same for all of the
>>> currently supported boards, I think it will be better to remove the
>>> entire audio clocks initialization from the clk drivers and move it all
>>> to the audio driver. It could be something like this:
>>>
>>> int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data,
>>>               struct device *dev)
>>> {
>>>     ...
>>>
>>>     if (!of_find_property(dev->of_node, "assigned-clock-parents",
>>> NULL) &&
>>>         tegra_get_chip_id() > TEGRA20) {
>>>         clk_extern1 = clk_get(dev, "extern1");
>>>         ...
>>>         clk_set_parent(clk_extern1, clk_pll_a_out0);
>>>         ...
>>>         clk_put(data->clk_cdev1);
>>>
>>>         data->clk_cdev1 = clk_out_1;
>>>     }
>>>     ...
>>>
>>> So now the old device-trees will cointinue to work and new could have
>>> the assigned-clocks and set MCLK to CLK_OUT_1.
>>>
>>> [snip]
>>
>> Will update clk-tegra, pmc and audio driver to move init state
>> configuration for extern1 and clk_out_1 into audio driver and will use
>> assigned clock properties in device tree.
>>

On 12/4/19 12:28 PM, Dmitry Osipenko wrote:
> 04.12.2019 23:08, Sowjanya Komatineni пишет:
>> On 12/4/19 8:02 AM, Sowjanya Komatineni wrote:
>>> On 12/4/19 5:39 AM, Dmitry Osipenko wrote:
>>>> 03.12.2019 19:45, Sowjanya Komatineni пишет:
>>>>> On 12/2/19 4:07 PM, Sowjanya Komatineni wrote:
>>>>>> On 12/2/19 3:14 PM, Sowjanya Komatineni wrote:
>>>>>>> On 12/2/19 3:10 PM, Sowjanya Komatineni wrote:
>>>>>>>> On 12/2/19 2:58 PM, Sowjanya Komatineni wrote:
>>>>>>>>> On 12/2/19 1:50 PM, Dmitry Osipenko wrote:
>>>>>>>>>> 02.12.2019 23:09, Sowjanya Komatineni пишет:
>>>>>>>>>>> On 11/28/19 5:25 AM, Dmitry Osipenko wrote:
>>>>>>>>>>>> 28.11.2019 01:57, Sowjanya Komatineni пишет:
>>>>>>>>>>>>> On 11/27/19 7:14 AM, Dmitry Osipenko wrote:
>>>>>>>>>>>>>> 27.11.2019 07:59, Sowjanya Komatineni пишет:
>>>>>>>>>>>>>>> Tegra210 and prior Tegra PMC has clk_out_1, clk_out_2,
>>>>>>>>>>>>>>> clk_out_3 with
>>>>>>>>>>>>>>> mux and gate for each of these clocks.
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> Currently these PMC clocks are registered by Tegra clock
>>>>>>>>>>>>>>> driver using
>>>>>>>>>>>>>>> clk_register_mux and clk_register_gate by passing PMC base
>>>>>>>>>>>>>>> address
>>>>>>>>>>>>>>> and register offsets and PMC programming for these clocks
>>>>>>>>>>>>>>> happens
>>>>>>>>>>>>>>> through direct PMC access by the clock driver.
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> With this, when PMC is in secure mode any direct PMC access
>>>>>>>>>>>>>>> from the
>>>>>>>>>>>>>>> non-secure world does not go through and these clocks will
>>>>>>>>>>>>>>> not be
>>>>>>>>>>>>>>> functional.
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> This patch adds these clocks registration with PMC as a clock
>>>>>>>>>>>>>>> provider
>>>>>>>>>>>>>>> for these clocks. clk_ops callback implementations for these
>>>>>>>>>>>>>>> clocks
>>>>>>>>>>>>>>> uses tegra_pmc_readl and tegra_pmc_writel which supports PMC
>>>>>>>>>>>>>>> programming
>>>>>>>>>>>>>>> in secure mode and non-secure mode.
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>>>>>>>>>>>>> ---
>>>>>>>>>>>>>>>       drivers/soc/tegra/pmc.c | 330
>>>>>>>>>>>>>>> ++++++++++++++++++++++++++++++++++++++++++++++++
>>>>>>>>>>>>>>>       1 file changed, 330 insertions(+)
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> diff --git a/drivers/soc/tegra/pmc.c
>>>>>>>>>>>>>>> b/drivers/soc/tegra/pmc.c
>>>>>>>>>>>>>>> index ea0e11a09c12..a353f6d0a832 100644
>>>>>>>>>>>>>>> --- a/drivers/soc/tegra/pmc.c
>>>>>>>>>>>>>>> +++ b/drivers/soc/tegra/pmc.c
>>>>>>>>>>>>>>> @@ -13,6 +13,9 @@
>>>>>>>>>>>>>>>         #include <linux/arm-smccc.h>
>>>>>>>>>>>>>>>       #include <linux/clk.h>
>>>>>>>>>>>>>>> +#include <linux/clk-provider.h>
>>>>>>>>>>>>>>> +#include <linux/clkdev.h>
>>>>>>>>>>>>>>> +#include <linux/clk/clk-conf.h>
>>>>>>>>>>>>>>>       #include <linux/clk/tegra.h>
>>>>>>>>>>>>>>>       #include <linux/debugfs.h>
>>>>>>>>>>>>>>>       #include <linux/delay.h>
>>>>>>>>>>>>>>> @@ -48,6 +51,7 @@
>>>>>>>>>>>>>>>       #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
>>>>>>>>>>>>>>>       #include <dt-bindings/gpio/tegra186-gpio.h>
>>>>>>>>>>>>>>>       #include <dt-bindings/gpio/tegra194-gpio.h>
>>>>>>>>>>>>>>> +#include <dt-bindings/soc/tegra-pmc.h>
>>>>>>>>>>>>>>>         #define PMC_CNTRL            0x0
>>>>>>>>>>>>>>>       #define  PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR
>>>>>>>>>>>>>>> polarity */
>>>>>>>>>>>>>>> @@ -100,6 +104,7 @@
>>>>>>>>>>>>>>>       #define PMC_WAKE2_STATUS        0x168
>>>>>>>>>>>>>>>       #define PMC_SW_WAKE2_STATUS 0x16c
>>>>>>>>>>>>>>>       +#define PMC_CLK_OUT_CNTRL 0x1a8
>>>>>>>>>>>>>>>       #define PMC_SENSOR_CTRL 0x1b0
>>>>>>>>>>>>>>>       #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2)
>>>>>>>>>>>>>>>       #define  PMC_SENSOR_CTRL_ENABLE_RST BIT(1)
>>>>>>>>>>>>>>> @@ -155,6 +160,91 @@
>>>>>>>>>>>>>>>       #define  TEGRA_SMC_PMC_READ    0xaa
>>>>>>>>>>>>>>>       #define  TEGRA_SMC_PMC_WRITE    0xbb
>>>>>>>>>>>>>>>       +struct pmc_clk_mux {
>>>>>>>>>>>>>>> +    struct clk_hw    hw;
>>>>>>>>>>>>>>> +    unsigned long    offs;
>>>>>>>>>>>>>>> +    u32        mask;
>>>>>>>>>>>>>>> +    u32        shift;
>>>>>>>>>>>>>>> +};
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +#define to_pmc_clk_mux(_hw) container_of(_hw, struct
>>>>>>>>>>>>>>> pmc_clk_mux, hw)
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +struct pmc_clk_gate {
>>>>>>>>>>>>>>> +    struct clk_hw    hw;
>>>>>>>>>>>>>>> +    unsigned long    offs;
>>>>>>>>>>>>>>> +    u32        shift;
>>>>>>>>>>>>>>> +};
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +#define to_pmc_clk_gate(_hw) container_of(_hw, struct
>>>>>>>>>>>>>>> pmc_clk_gate, hw)
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +struct pmc_clk_init_data {
>>>>>>>>>>>>>>> +    char *mux_name;
>>>>>>>>>>>>>>> +    char *gate_name;
>>>>>>>>>>>>>>> +    const char **parents;
>>>>>>>>>>>>>>> +    int num_parents;
>>>>>>>>>>>>>>> +    int mux_id;
>>>>>>>>>>>>>>> +    int gate_id;
>>>>>>>>>>>>>>> +    char *dev_name;
>>>>>>>>>>>>>>> +    u8 mux_shift;
>>>>>>>>>>>>>>> +    u8 gate_shift;
>>>>>>>>>>>>>>> +    u8 init_parent_index;
>>>>>>>>>>>>>>> +    int init_state;
>>>>>>>>>>>>>>> +};
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +static const char *clk_out1_parents[] = { "clk_m",
>>>>>>>>>>>>>>> "clk_m_div2",
>>>>>>>>>>>>>>> +    "clk_m_div4", "extern1",
>>>>>>>>>>>>>>> +};
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +static const char *clk_out2_parents[] = { "clk_m",
>>>>>>>>>>>>>>> "clk_m_div2",
>>>>>>>>>>>>>>> +    "clk_m_div4", "extern2",
>>>>>>>>>>>>>>> +};
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +static const char *clk_out3_parents[] = { "clk_m",
>>>>>>>>>>>>>>> "clk_m_div2",
>>>>>>>>>>>>>>> +    "clk_m_div4", "extern3",
>>>>>>>>>>>>>>> +};
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +static struct pmc_clk_init_data tegra_pmc_clks_data[] = {
>>>>>>>>>>>>>>> +    {
>>>>>>>>>>>>>>> +        .mux_name = "clk_out_1_mux",
>>>>>>>>>>>>>>> +        .gate_name = "clk_out_1",
>>>>>>>>>>>>>>> +        .parents = clk_out1_parents,
>>>>>>>>>>>>>>> +        .num_parents = ARRAY_SIZE(clk_out1_parents),
>>>>>>>>>>>>>>> +        .mux_id = TEGRA_PMC_CLK_OUT_1_MUX,
>>>>>>>>>>>>>>> +        .gate_id = TEGRA_PMC_CLK_OUT_1,
>>>>>>>>>>>>>>> +        .dev_name = "extern1",
>>>>>>>>>>>>>>> +        .mux_shift = 6,
>>>>>>>>>>>>>>> +        .gate_shift = 2,
>>>>>>>>>>>>>>> +        .init_parent_index = 3,
>>>>>>>>>>>>>>> +        .init_state = 1,
>>>>>>>>>>>>>>> +    },
>>>>>>>>>>>>>>> +    {
>>>>>>>>>>>>>>> +        .mux_name = "clk_out_2_mux",
>>>>>>>>>>>>>>> +        .gate_name = "clk_out_2",
>>>>>>>>>>>>>>> +        .parents = clk_out2_parents,
>>>>>>>>>>>>>>> +        .num_parents = ARRAY_SIZE(clk_out2_parents),
>>>>>>>>>>>>>>> +        .mux_id = TEGRA_PMC_CLK_OUT_2_MUX,
>>>>>>>>>>>>>>> +        .gate_id = TEGRA_PMC_CLK_OUT_2,
>>>>>>>>>>>>>>> +        .dev_name = "extern2",
>>>>>>>>>>>>>>> +        .mux_shift = 14,
>>>>>>>>>>>>>>> +        .gate_shift = 10,
>>>>>>>>>>>>>>> +        .init_parent_index = 0,
>>>>>>>>>>>>>>> +        .init_state = 0,
>>>>>>>>>>>>>>> +    },
>>>>>>>>>>>>>>> +    {
>>>>>>>>>>>>>>> +        .mux_name = "clk_out_3_mux",
>>>>>>>>>>>>>>> +        .gate_name = "clk_out_3",
>>>>>>>>>>>>>>> +        .parents = clk_out3_parents,
>>>>>>>>>>>>>>> +        .num_parents = ARRAY_SIZE(clk_out3_parents),
>>>>>>>>>>>>>>> +        .mux_id = TEGRA_PMC_CLK_OUT_3_MUX,
>>>>>>>>>>>>>>> +        .gate_id = TEGRA_PMC_CLK_OUT_3,
>>>>>>>>>>>>>>> +        .dev_name = "extern3",
>>>>>>>>>>>>>>> +        .mux_shift = 22,
>>>>>>>>>>>>>>> +        .gate_shift = 18,
>>>>>>>>>>>>>>> +        .init_parent_index = 0,
>>>>>>>>>>>>>>> +        .init_state = 0,
>>>>>>>>>>>>>>> +    },
>>>>>>>>>>>>>>> +};
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>>       struct tegra_powergate {
>>>>>>>>>>>>>>>           struct generic_pm_domain genpd;
>>>>>>>>>>>>>>>           struct tegra_pmc *pmc;
>>>>>>>>>>>>>>> @@ -254,6 +344,9 @@ struct tegra_pmc_soc {
>>>>>>>>>>>>>>>            */
>>>>>>>>>>>>>>>           const struct tegra_wake_event *wake_events;
>>>>>>>>>>>>>>>           unsigned int num_wake_events;
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +    struct pmc_clk_init_data *pmc_clks_data;
>>>>>>>>>>>>>>> +    unsigned int num_pmc_clks;
>>>>>>>>>>>>>>>       };
>>>>>>>>>>>>>>>         static const char * const tegra186_reset_sources[] = {
>>>>>>>>>>>>>>> @@ -2163,6 +2256,228 @@ static int
>>>>>>>>>>>>>>> tegra_pmc_clk_notify_cb(struct
>>>>>>>>>>>>>>> notifier_block *nb,
>>>>>>>>>>>>>>>           return NOTIFY_OK;
>>>>>>>>>>>>>>>       }
>>>>>>>>>>>>>>>       +static void pmc_clk_fence_udelay(u32 offset)
>>>>>>>>>>>>>>> +{
>>>>>>>>>>>>>>> +    tegra_pmc_readl(pmc, offset);
>>>>>>>>>>>>>>> +    /* pmc clk propagation delay 2 us */
>>>>>>>>>>>>>>> +    udelay(2);
>>>>>>>>>>>>>>> +}
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
>>>>>>>>>>>>>>> +{
>>>>>>>>>>>>>>> +    struct pmc_clk_mux *mux = to_pmc_clk_mux(hw);
>>>>>>>>>>>>>>> +    int num_parents = clk_hw_get_num_parents(hw);
>>>>>>>>>>>>>>> +    u32 val;
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +    val = tegra_pmc_readl(pmc, mux->offs) >> mux->shift;
>>>>>>>>>>>>>>> +    val &= mux->mask;
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +    if (val >= num_parents)
>>>>>>>>>>>>>>> +        return -EINVAL;
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +    return val;
>>>>>>>>>>>>>>> +}
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8
>>>>>>>>>>>>>>> index)
>>>>>>>>>>>>>>> +{
>>>>>>>>>>>>>>> +    struct pmc_clk_mux *mux = to_pmc_clk_mux(hw);
>>>>>>>>>>>>>>> +    u32 val;
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +    val = tegra_pmc_readl(pmc, mux->offs);
>>>>>>>>>>>>>>> +    val &= ~(mux->mask << mux->shift);
>>>>>>>>>>>>>>> +    val |= index << mux->shift;
>>>>>>>>>>>>>>> +    tegra_pmc_writel(pmc, val, mux->offs);
>>>>>>>>>>>>>>> +    pmc_clk_fence_udelay(mux->offs);
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +    return 0;
>>>>>>>>>>>>>>> +}
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +static const struct clk_ops pmc_clk_mux_ops = {
>>>>>>>>>>>>>>> +    .get_parent = pmc_clk_mux_get_parent,
>>>>>>>>>>>>>>> +    .set_parent = pmc_clk_mux_set_parent,
>>>>>>>>>>>>>>> +    .determine_rate = __clk_mux_determine_rate,
>>>>>>>>>>>>>>> +};
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +static struct clk *
>>>>>>>>>>>>>>> +tegra_pmc_clk_mux_register(const char *name, const char *
>>>>>>>>>>>>>>> const
>>>>>>>>>>>>>>> *parent_names,
>>>>>>>>>>>>>>> +               int num_parents, unsigned long flags,
>>>>>>>>>>>>>>> +               unsigned long offset, u32 shift, u32 mask)
>>>>>>>>>>>>>>> +{
>>>>>>>>>>>>>>> +    struct clk_init_data init;
>>>>>>>>>>>>>>> +    struct pmc_clk_mux *mux;
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +    mux = kzalloc(sizeof(*mux), GFP_KERNEL);
>>>>>>>>>>>>>>> +    if (!mux)
>>>>>>>>>>>>>>> +        return ERR_PTR(-ENOMEM);
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +    init.name = name;
>>>>>>>>>>>>>>> +    init.ops = &pmc_clk_mux_ops;
>>>>>>>>>>>>>>> +    init.parent_names = parent_names;
>>>>>>>>>>>>>>> +    init.num_parents = num_parents;
>>>>>>>>>>>>>>> +    init.flags = flags;
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +    mux->hw.init = &init;
>>>>>>>>>>>>>>> +    mux->offs = offset;
>>>>>>>>>>>>>>> +    mux->mask = mask;
>>>>>>>>>>>>>>> +    mux->shift = shift;
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +    return clk_register(NULL, &mux->hw);
>>>>>>>>>>>>>>> +}
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +static int pmc_clk_is_enabled(struct clk_hw *hw)
>>>>>>>>>>>>>>> +{
>>>>>>>>>>>>>>> +    struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +    return tegra_pmc_readl(pmc, gate->offs) &
>>>>>>>>>>>>>>> BIT(gate->shift) ? 1
>>>>>>>>>>>>>>> : 0;
>>>>>>>>>>>>>>> +}
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +static void pmc_clk_set_state(struct clk_hw *hw, int state)
>>>>>>>>>>>>>>> +{
>>>>>>>>>>>>>>> +    struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
>>>>>>>>>>>>>>> +    u32 val;
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +    val = tegra_pmc_readl(pmc, gate->offs);
>>>>>>>>>>>>>>> +    val = state ? (val | BIT(gate->shift)) : (val &
>>>>>>>>>>>>>>> ~BIT(gate->shift));
>>>>>>>>>>>>>>> +    tegra_pmc_writel(pmc, val, gate->offs);
>>>>>>>>>>>>>>> +    pmc_clk_fence_udelay(gate->offs);
>>>>>>>>>>>>>>> +}
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +static int pmc_clk_enable(struct clk_hw *hw)
>>>>>>>>>>>>>>> +{
>>>>>>>>>>>>>>> +    pmc_clk_set_state(hw, 1);
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +    return 0;
>>>>>>>>>>>>>>> +}
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +static void pmc_clk_disable(struct clk_hw *hw)
>>>>>>>>>>>>>>> +{
>>>>>>>>>>>>>>> +    pmc_clk_set_state(hw, 0);
>>>>>>>>>>>>>>> +}
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +static const struct clk_ops pmc_clk_gate_ops = {
>>>>>>>>>>>>>>> +    .is_enabled = pmc_clk_is_enabled,
>>>>>>>>>>>>>>> +    .enable = pmc_clk_enable,
>>>>>>>>>>>>>>> +    .disable = pmc_clk_disable,
>>>>>>>>>>>>>>> +};
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +static struct clk *
>>>>>>>>>>>>>>> +tegra_pmc_clk_gate_register(const char *name, const char
>>>>>>>>>>>>>>> *parent_name,
>>>>>>>>>>>>>>> +                unsigned long flags, unsigned long offset,
>>>>>>>>>>>>>>> +                u32 shift)
>>>>>>>>>>>>>>> +{
>>>>>>>>>>>>>>> +    struct clk_init_data init;
>>>>>>>>>>>>>>> +    struct pmc_clk_gate *gate;
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +    gate = kzalloc(sizeof(*gate), GFP_KERNEL);
>>>>>>>>>>>>>>> +    if (!gate)
>>>>>>>>>>>>>>> +        return ERR_PTR(-ENOMEM);
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +    init.name = name;
>>>>>>>>>>>>>>> +    init.ops = &pmc_clk_gate_ops;
>>>>>>>>>>>>>>> +    init.parent_names = &parent_name;
>>>>>>>>>>>>>>> +    init.num_parents = 1;
>>>>>>>>>>>>>>> +    init.flags = flags;
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +    gate->hw.init = &init;
>>>>>>>>>>>>>>> +    gate->offs = offset;
>>>>>>>>>>>>>>> +    gate->shift = shift;
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +    return clk_register(NULL, &gate->hw);
>>>>>>>>>>>>>>> +}
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
>>>>>>>>>>>>>>> +                     struct device_node *np)
>>>>>>>>>>>>>>> +{
>>>>>>>>>>>>>>> +    struct clk *clkmux, *clk, *parent;
>>>>>>>>>>>>>>> +    struct clk_onecell_data *clk_data;
>>>>>>>>>>>>>>> +    unsigned int num_clks;
>>>>>>>>>>>>>>> +    int i, ret;
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +    /* each pmc clock output has a mux and a gate */
>>>>>>>>>>>>>>> +    num_clks = pmc->soc->num_pmc_clks * 2;
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +    if (!num_clks)
>>>>>>>>>>>>>>> +        return;
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +    clk_data = kmalloc(sizeof(*clk_data), GFP_KERNEL);
>>>>>>>>>>>>>>> +    if (!clk_data)
>>>>>>>>>>>>>>> +        return;
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +    clk_data->clks = kcalloc(TEGRA_PMC_CLK_MAX,
>>>>>>>>>>>>>>> sizeof(*clk_data->clks),
>>>>>>>>>>>>>>> +                 GFP_KERNEL);
>>>>>>>>>>>>>>> +    if (!clk_data->clks)
>>>>>>>>>>>>>>> +        goto free_clkdata;
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +    clk_data->clk_num = num_clks;
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +    for (i = 0; i < pmc->soc->num_pmc_clks; i++) {
>>>>>>>>>>>>>>> +        struct pmc_clk_init_data *data;
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +        data = pmc->soc->pmc_clks_data + i;
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +        clkmux = tegra_pmc_clk_mux_register(data->mux_name,
>>>>>>>>>>>>>>> + data->parents,
>>>>>>>>>>>>>>> + data->num_parents,
>>>>>>>>>>>>>>> + CLK_SET_RATE_NO_REPARENT |
>>>>>>>>>>>>>>> + CLK_SET_RATE_PARENT,
>>>>>>>>>>>>>>> + PMC_CLK_OUT_CNTRL,
>>>>>>>>>>>>>>> + data->mux_shift, 3);
>>>>>>>>>>>>>>> +        if (IS_ERR(clkmux))
>>>>>>>>>>>>>>> +            goto free_clks;
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> + clk_data->clks[data->mux_id] = clkmux;
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +        clk = tegra_pmc_clk_gate_register(data->gate_name,
>>>>>>>>>>>>>>> + data->mux_name,
>>>>>>>>>>>>>>> + CLK_SET_RATE_PARENT,
>>>>>>>>>>>>>>> + PMC_CLK_OUT_CNTRL,
>>>>>>>>>>>>>>> + data->gate_shift);
>>>>>>>>>>>>>>> +        if (IS_ERR(clk))
>>>>>>>>>>>>>>> +            goto free_clks;
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> + clk_data->clks[data->gate_id] = clk;
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +        ret = clk_set_parent(clk, clkmux);
>>>>>>>>>>>>>>> +        if (ret < 0) {
>>>>>>>>>>>>>>> +            pr_err("failed to set parent of %s to %s\n",
>>>>>>>>>>>>>>> +                   __func__, __clk_get_name(clk),
>>>>>>>>>>>>>>> + __clk_get_name(clkmux));
>>>>>>>>>>>>>>> +        }
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +        clk_register_clkdev(clk, data->dev_name,
>>>>>>>>>>>>>>> data->gate_name);
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +        /* configure initial clock parent and state */
>>>>>>>>>>>>>>> +        parent = clk_get_sys(data->gate_name,
>>>>>>>>>>>>>>> + data->parents[data->init_parent_index]);
>>>>>>>>>> Couldn't the default parent be defined using "assigned clock" in a
>>>>>>>>>> device-tree? Please see "Assigned clock parents and rates" in the
>>>>>>>>>> doc.
>>>>>>>>>>
>>>>>>>>>> https://www.kernel.org/doc/Documentation/devicetree/bindings/clock/clock-bindings.txt
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> Then you could simply use of_clk_set_defaults(pmc->dev->of_node,
>>>>>>>>>> true).
>>>>>>>>> Yes, of_clk_add_provider() does of_clk_set_defaults which sets
>>>>>>>>> based on assigned parents and clock rates.
>>>>>>>>>
>>>>>>>>> This need device tree to specify assigned clock parent properties.
>>>>>>>>> Will update device tree and remove init parent from the driver.
>>>>>>>>>
>>>>>>>> assigned-clock properties should be set in consumer node of these
>>>>>>>> clocks and currently these clocks are not used yet.
>>>>>>>>
>>>>>>>> So will just remove init parent from driver and when these clocks
>>>>>>>> are used device tree can be updated in corresponding consumer node
>>>>>>>> with these properties.
>>>>>>>>
>>>>>>> How about default ON/OFF init state for the clocks? I see
>>>>>>> assigned-clock properties for parent and rate only.
>>>>>>>
>>>>>>> But based on existing clock-tegra-pmc driver, I see clk_out_1 is
>>>>>>> default enabled with extern1 parent for T30 thru T210 platforms.
>>>>>>>
>>>>>>> Peter/Thierry, What was the reason we enable clk_out_1 right from the
>>>>>>> clock registration?
>>>>>>>
>>>>>> clk_out_1 is for audio and its not required to be enabled during the
>>>>>> boot and audio driver can enable/disable it.
>>>>>>
>>>>>> same with blink 32khz which is used for WIFI. WIFI driver can
>>>>>> enable/disable during power up/down sequence and technically as per
>>>>>> design we dont need to have it always on right from the boot.
>>>>>>
>>>>>> So can remove out clocks init states from driver once thierry also
>>>>>> agree on this.
>>>>>>
>>>>> Hi Dmitry,
>>>>>
>>>>> Looking at audio driver, it doesn't take care of mclk which is from
>>>>> clk_out_1 and expects mclk to be always on.
>>>>>
>>>>> So probably we should have this init state enables in pmc driver for
>>>>> 32Khz and clk_out's to not break existing functionality.
>>>> Hello Sowjanya,
>>>>
>>>> IIUC, it's a bug in the device-trees and sound's MCLK actually should be
>>>> set to CLK_OUT_1 of PMC instead of CaR's EXTPERIPH1. If that's the case,
>>>> then the device-trees need to be fixed.
>>> OK, will have this in v3
>> Actually if we change mclk to use clk_out_1, then it will break with old
>> device trees.
>>
>> Currently clk_out_1 parent is set to extern1 as init state by the clock
>> driver and device tree for sound node is using extern1 as mclk works and
>> extern1 itself has enable and disable. But yes implementation wise, its
>> incorrect as mclk should really be clk_out_1.
>>
>> Now, with moving clk_out_1 to tegra PMC, pmc is the clock provider and
>> if we now change the device tree to use CLK_OUT_1 as mclk then it will
>> break old device tree.
> There souldn't be any problem with enabling CLK_OUT_1 by the audio
> driver itself (in the code) if an old device-tree is detected.
>
> 	clk_out_1 = clk_get(dev, "clk_out_1");
> 	clk_set_parent(clk_out_1, clk_extern1);
> 	...
> 	data->clk_cdev1 = clk_out_1;
>
> Maybe it will be even better to compare clocks for detection of an older DT:
>
> 	if (tegra_get_chip_id() > TEGRA20 &&
> 	    clk_is_match(data->clk_cdev1, clk_extern1)) {
> 	...
>
we can do parent init in audio driver which is not an issue.

But I was saying we can keep extern1 as mclk in device tree instead of 
changing to clk_out_1 from pmc as it will break old device tree becasue 
we moved clk_out_1 from clock driver to pmc driver.

once we do init parent in audio driver, we still can use extern1 as mclk 
in device tree.

mclk -> clk_out_1 -> extern1 -> plla_out0 -> plla

with init of clk_out_1 parent to extern1, mclk can use extern1 handle 
for rate/enable/disable clk operations

>>>>> Regarding using assigned-clock properties for init parent and removing
>>>>> init parent from driver, it also needs consumer node in device tree to
>>>>> be updated to specify assigned-clock properties for default/init
>>>>> parent.
>>>>>
>>>>> This breaks device tree ABI as prior Tegra210 supports audio driver.
>>>> So it's the sound node which should have had the assigned clocks in
>>>> device-tree in order to define route for the audio MCLK clock from CaR
>>>> to PMC.
>>>>
>>>> Given that the audio clocks configuration is the same for all of the
>>>> currently supported boards, I think it will be better to remove the
>>>> entire audio clocks initialization from the clk drivers and move it all
>>>> to the audio driver. It could be something like this:
>>>>
>>>> int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data,
>>>>                struct device *dev)
>>>> {
>>>>      ...
>>>>
>>>>      if (!of_find_property(dev->of_node, "assigned-clock-parents",
>>>> NULL) &&
>>>>          tegra_get_chip_id() > TEGRA20) {
>>>>          clk_extern1 = clk_get(dev, "extern1");
>>>>          ...
>>>>          clk_set_parent(clk_extern1, clk_pll_a_out0);
>>>>          ...
>>>>          clk_put(data->clk_cdev1);
>>>>
>>>>          data->clk_cdev1 = clk_out_1;
>>>>      }
>>>>      ...
>>>>
>>>> So now the old device-trees will cointinue to work and new could have
>>>> the assigned-clocks and set MCLK to CLK_OUT_1.
>>>>
>>>> [snip]
>>> Will update clk-tegra, pmc and audio driver to move init state
>>> configuration for extern1 and clk_out_1 into audio driver and will use
>>> assigned clock properties in device tree.
>>>