| Message ID | 1562711090-900-1-git-send-email-thor.thayer@linux.intel.com |
|---|---|
| Headers | show |
| Series | Stratix10 SDRAM Common EDAC Framework | expand |
On 7/9/19 5:24 PM, thor.thayer@linux.intel.com wrote: > From: Thor Thayer <thor.thayer@linux.intel.com> > > Use the common Altera EDAC Device Framework for the SDRAM so that > Double Bit Error Addresses can be tracked for SDRAM. > This also simplifies the device tree. > > Thor Thayer (3): > Documentation: dt: edac: Add reg to S10 SDRAM node > arm64: dts: Stratix10: Include regs in SDRAM ECC node > EDAC, altera: Use common framework for Stratix10 SDRAM ECC > > .../devicetree/bindings/edac/socfpga-eccmgr.txt | 4 ++- > arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 9 ++---- > drivers/edac/altera_edac.c | 32 ++++++++++++++++++++-- > drivers/edac/altera_edac.h | 25 ++++++++++++++++- > 4 files changed, 58 insertions(+), 12 deletions(-) > Please disregard this patchset, there is a simpler solution.
On 7/9/19 5:24 PM, thor.thayer@linux.intel.com wrote: > From: Thor Thayer <thor.thayer@linux.intel.com> > > Include the regs directly in the SDRAM node instead of using > a syscon. The Stratix10 SDRAM ECC registers are partitioned > away from other Sys Manager registers so the syscon is no > longer needed for Stratix10. > > Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> > --- > arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 9 ++------- > 1 file changed, 2 insertions(+), 7 deletions(-) > > diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi > index 4b0f674df849..a1e9545de3d3 100644 > --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi > +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi > @@ -517,11 +517,6 @@ > status = "disabled"; > }; > > - sdr: sdr@f8011100 { > - compatible = "altr,sdr-ctl", "syscon"; > - reg = <0xf8011100 0xc0>; > - }; > - > eccmgr { > compatible = "altr,socfpga-s10-ecc-manager", > "altr,socfpga-a10-ecc-manager"; > @@ -533,9 +528,9 @@ > #interrupt-cells = <2>; > ranges; > > - sdramedac { > + sdramedac@0xf8011100 { > compatible = "altr,sdram-edac-s10"; > - altr,sdr-syscon = <&sdr>; > + reg = <0xf8011100 0xc0>; > interrupts = <16 4>; > }; > > Please disregard this patch, there is a simpler solution that I will submit shortly.
From: Thor Thayer <thor.thayer@linux.intel.com> Use the common Altera EDAC Device Framework for the SDRAM so that Double Bit Error Addresses can be tracked for SDRAM. This also simplifies the device tree. Thor Thayer (3): Documentation: dt: edac: Add reg to S10 SDRAM node arm64: dts: Stratix10: Include regs in SDRAM ECC node EDAC, altera: Use common framework for Stratix10 SDRAM ECC .../devicetree/bindings/edac/socfpga-eccmgr.txt | 4 ++- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 9 ++---- drivers/edac/altera_edac.c | 32 ++++++++++++++++++++-- drivers/edac/altera_edac.h | 25 ++++++++++++++++- 4 files changed, 58 insertions(+), 12 deletions(-)