From patchwork Mon Mar 12 11:40:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Preetham Chandru Ramchandra X-Patchwork-Id: 884440 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nvidia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 400GJq6ZYnz9sSf for ; Mon, 12 Mar 2018 22:40:59 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751247AbeCLLk5 (ORCPT ); Mon, 12 Mar 2018 07:40:57 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:15737 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751232AbeCLLk4 (ORCPT ); Mon, 12 Mar 2018 07:40:56 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Mon, 12 Mar 2018 04:40:54 -0700 Received: from HQMAIL107.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 12 Mar 2018 04:40:56 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 12 Mar 2018 04:40:56 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Mon, 12 Mar 2018 11:40:56 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server id 15.0.1347.2 via Frontend Transport; Mon, 12 Mar 2018 11:40:55 +0000 Received: from pchandru-pc.nvidia.com (Not Verified[10.24.37.8]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 12 Mar 2018 04:40:55 -0700 From: Preetham Chandru Ramchandra To: , , , , CC: , , , , , , Preetham Ramchandra Subject: [PATCH V8 0/9] Refactor and add AHCI support for Tegra210 Date: Mon, 12 Mar 2018 17:10:29 +0530 Message-ID: <1520854838-21779-1-git-send-email-pchandru@nvidia.com> X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Preetham Ramchandra 1. ADD AHCI support for Tegra210 2. Extend the Tegra AHCI controller device tree binding with Tegra210 3. Update initialization sequence 4. Initialize regulators based on chip 5. Disable DevSlp 6. Disable DIPM Acked-by: Thierry Reding Acked-by: Thierry Reding Acked-by: Thierry Reding Acked-by: Thierry Reding Acked-by: Thierry Reding Acked-by: Thierry Reding Tested-by: Thierry Reding --- Preetham Ramchandra (9): dt-bindings: Tegra210: add binding documentation arm64: tegra: Add SATA node for Tegra210 arm64: tegra: Enable AHCI on Jetson TX1 ata: ahci_tegra: Update initialization sequence ata: ahci_tegra: initialize regulators from soc struct ata: ahci_tegra: disable devslp for Tegra124 ata: ahci_tegra: disable DIPM ata: ahci_tegra: Add AHCI support for Tegra210 ata: change Tegra124 to Tegra .../bindings/ata/nvidia,tegra124-ahci.txt | 36 ++- arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 5 + arch/arm64/boot/dts/nvidia/tegra210.dtsi | 16 + drivers/ata/Kconfig | 4 +- drivers/ata/ahci_tegra.c | 359 ++++++++++++++++----- 5 files changed, 330 insertions(+), 90 deletions(-)