From patchwork Thu Sep 25 13:27:29 2008 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "D. Herrendoerfer" X-Patchwork-Id: 1524 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [127.0.0.1]) by ozlabs.org (Postfix) with ESMTP id 33745DE1E3 for ; Thu, 25 Sep 2008 23:30:19 +1000 (EST) X-Original-To: cbe-oss-dev@ozlabs.org Delivered-To: cbe-oss-dev@ozlabs.org Received: from mtagate5.de.ibm.com (mtagate5.de.ibm.com [195.212.29.154]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "mtagate5.de.ibm.com", Issuer "Equifax" (verified OK)) by ozlabs.org (Postfix) with ESMTPS id 9C7C2DDF0A for ; Thu, 25 Sep 2008 23:30:08 +1000 (EST) Received: from d12nrmr1607.megacenter.de.ibm.com (d12nrmr1607.megacenter.de.ibm.com [9.149.167.49]) by mtagate5.de.ibm.com (8.13.8/8.13.8) with ESMTP id m8PDSGac119236 for ; Thu, 25 Sep 2008 13:28:16 GMT Received: from d12av02.megacenter.de.ibm.com (d12av02.megacenter.de.ibm.com [9.149.165.228]) by d12nrmr1607.megacenter.de.ibm.com (8.13.8/8.13.8/NCO v9.1) with ESMTP id m8PDRxrG2965706 for ; Thu, 25 Sep 2008 15:28:16 +0200 Received: from d12av02.megacenter.de.ibm.com (loopback [127.0.0.1]) by d12av02.megacenter.de.ibm.com (8.12.11.20060308/8.13.3) with ESMTP id m8PDRuRF018583 for ; Thu, 25 Sep 2008 15:27:56 +0200 Received: from dyn-9-152-210-41.boeblingen.de.ibm.com (dyn-9-152-210-41.boeblingen.de.ibm.com [9.152.210.41]) by d12av02.megacenter.de.ibm.com (8.12.11.20060308/8.12.11) with ESMTP id m8PDRuPW017630; Thu, 25 Sep 2008 15:27:56 +0200 Message-Id: <20AA09B7-D403-4D7C-AA0B-41E8D5ECBE94@herrendoerfer.name> From: "D. Herrendoerfer" To: Kazunori Asayama In-Reply-To: <48D3A4DE.7050201@sm.sony.co.jp> Mime-Version: 1.0 (Apple Message framework v929.2) Date: Thu, 25 Sep 2008 15:27:29 +0200 References: <1221826522.4440.9.camel@localhost> <48D3A4DE.7050201@sm.sony.co.jp> X-Mailer: Apple Mail (2.929.2) Cc: CBE Development Subject: [Cbe-oss-dev] [PATCH]libspe2: add SPE_CPU_TYPE query to spe_cpu_info_get X-BeenThere: cbe-oss-dev@ozlabs.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Discussion about Open Source Software for the Cell Broadband Engine List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: cbe-oss-dev-bounces+patchwork-incoming=ozlabs.org@ozlabs.org Errors-To: cbe-oss-dev-bounces+patchwork-incoming=ozlabs.org@ozlabs.org Resending, Asayama-san you were right. This patch adds the SPE_CPU_TYPE query to the spe_cpu_info_get() function. The list of EDP capable CPUs is quite short, if anyone has more information about PVR values please send them to me. Signed-off-by: D.Herrendoerfer Index: libspe2/spebase/info.h =================================================================== --- libspe2/spebase/info.h (revision 133) +++ libspe2/spebase/info.h (working copy) @@ -27,5 +27,12 @@ int _base_spe_count_physical_cpus(int cpu_node); int _base_spe_count_physical_spes(int cpu_node); int _base_spe_count_usable_spes(int cpu_node); +int _base_spe_read_cpu_type(int cpu_node); + +/* Here is a list of edp capable PVRs + * Known non-EDP are: 0x0070 0501 ( PS3, QS20, QS21 ) + * Known EPD capable: 0x0070 3000 ( QS22 ) + */ +unsigned long pvr_list_edp[] = {0x00703000, 0}; #endif Index: libspe2/spebase/info.c =================================================================== --- libspe2/spebase/info.c (revision 133) +++ libspe2/spebase/info.c (working copy) @@ -103,6 +103,24 @@ int _base_spe_count_physical_spes(int cp return ret; } +/* Since there are no mixed-type CPU systems at this time the cpu node + * is currently ignored, and a result is generated that returns the + * feature set of the currently running CPU. + */ +int _base_spe_read_cpu_type(int cpu_node) +{ + unsigned long pvr; + int i=0; + + asm volatile ("mfpvr %0" : "=r"(pvr)); + + while (pvr_list_edp[i] != 0) { + if (pvr_list_edp[i++] == pvr) + return SPE_CPU_IS_CELLEDP; + } + + return SPE_CPU_IS_CELLBE; +} int _base_spe_cpu_info_get(int info_requested, int cpu_node) { int ret = 0; @@ -118,6 +136,9 @@ int _base_spe_cpu_info_get(int info_requ case SPE_COUNT_USABLE_SPES: ret = _base_spe_count_usable_spes(cpu_node); break; + case SPE_CPU_TYPE: + ret = _base_spe_read_cpu_type(cpu_node); + break; default: errno = EINVAL; ret = -1; Index: libspe2/libspe2-types.h =================================================================== --- libspe2/libspe2-types.h (revision 133) +++ libspe2/libspe2-types.h (working copy) @@ -262,10 +262,13 @@ enum ps_area { SPE_MSSYNC_AREA, SPE_MFC_ #define SPE_CALLBACK_UPDATE 2 - #define SPE_COUNT_PHYSICAL_CPU_NODES 1 #define SPE_COUNT_PHYSICAL_SPES 2 #define SPE_COUNT_USABLE_SPES 3 +#define SPE_CPU_TYPE 4 + +#define SPE_CPU_IS_CELLBE 1 +#define SPE_CPU_IS_CELLEDP 2 /** * Signal Targets