new file mode 100644
@@ -0,0 +1,71 @@
+diff --git a/deps/v8/src/heap/base/asm/x64/push_registers_asm.cc b/deps/v8/src/heap/base/asm/x64/push_registers_asm.cc
+index 9780b877..bffc8516 100644
+--- a/deps/v8/src/heap/base/asm/x64/push_registers_asm.cc
++++ b/deps/v8/src/heap/base/asm/x64/push_registers_asm.cc
+@@ -16,6 +16,45 @@
+ // GN toolchain (e.g. ChromeOS) and not provide them.
+ // _WIN64 Defined as 1 when the compilation target is 64-bit ARM or x64.
+ // Otherwise, undefined.
++#ifdef ARCH_IS_32BIT
++// stuff copied from 'deps/v8/src/heap/base/asm/ia32/push_registers_asm.cc'
++
++asm(
++#ifdef _WIN32
++ ".globl _PushAllRegistersAndIterateStack \n"
++ "_PushAllRegistersAndIterateStack: \n"
++#else // !_WIN32
++ ".globl PushAllRegistersAndIterateStack \n"
++ ".type PushAllRegistersAndIterateStack, %function \n"
++ ".hidden PushAllRegistersAndIterateStack \n"
++ "PushAllRegistersAndIterateStack: \n"
++#endif // !_WIN32
++ // [ IterateStackCallback ]
++ // [ StackVisitor* ]
++ // [ Stack* ]
++ // [ ret ]
++ // ebp is callee-saved. Maintain proper frame pointer for debugging.
++ " push %ebp \n"
++ " movl %esp, %ebp \n"
++ " push %ebx \n"
++ " push %esi \n"
++ " push %edi \n"
++ // Save 3rd parameter (IterateStackCallback).
++ " movl 28(%esp), %ecx \n"
++ // Pass 3rd parameter as esp (stack pointer).
++ " push %esp \n"
++ // Pass 2nd parameter (StackVisitor*).
++ " push 28(%esp) \n"
++ // Pass 1st parameter (Stack*).
++ " push 28(%esp) \n"
++ " call *%ecx \n"
++ // Pop the callee-saved registers.
++ " addl $24, %esp \n"
++ // Restore rbp as it was used as frame pointer.
++ " pop %ebp \n"
++ " ret \n");
++#else
++
+ #ifdef _WIN64
+
+ // We maintain 16-byte alignment at calls. There is an 8-byte return address
+@@ -104,3 +143,5 @@ asm(
+ " ret \n");
+
+ #endif // !_WIN64
++
++#endif // ! ARCH_IS_32BIT
+diff --git a/tools/v8_gypfiles/toolchain.gypi b/tools/v8_gypfiles/toolchain.gypi
+index ecbd63b5..0dfda084 100644
+--- a/tools/v8_gypfiles/toolchain.gypi
++++ b/tools/v8_gypfiles/toolchain.gypi
+@@ -1034,8 +1034,8 @@
+ 'cflags': [ '-m31' ],
+ 'ldflags': [ '-m31' ]
+ },{
+- 'cflags': [ '-m32' ],
+- 'ldflags': [ '-m32' ]
++ 'cflags': [ '-m32', '-DARCH_IS_32BIT' ],
++ 'ldflags': [ '-m32', '-DARCH_IS_32BIT' ]
+ }],
+ ],
+ }],
When gcc is run with -m32, the IA32 assembler doesn't understand 64-bit assembly. What happens is, that the bi-arch stuff won't seem to select the ia32 assembly-code when cross-building for a 32 bit target. It will try to build the host-tools with 'gcc -m32', but it still will try to compile the x64 assembly push_registers. This patch adds a 'ARCH_IS_32BIT' #define along side the -m32 flag and will select the code in the x64 push_registers assembly file. The undesired part is that we'll need to copy+paste the assembly code into the x64 file. Signed-off-by: Alexandru Ardelean <ardeleanalex@gmail.com> --- ...-x64-cross-compile-for-32-bit-target.patch | 71 +++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 package/nodejs/0003-fix-host-x64-cross-compile-for-32-bit-target.patch