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d="scan'208";a="146809706" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 08 Sep 2020 19:33:33 +0800 IronPort-SDR: YEagOmp47IzjnLk/YuxhUgrk7V04zlu2b4IRcadeoJFukqGPDZ6pqPB9IsYDVvGmyfFSGUkwtD DwDsd+f9QBJA== Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Sep 2020 04:19:58 -0700 IronPort-SDR: PTzqR1EPBCLRRu8j3/+M4bPA3FumUYtXuK1eohiIKzeY5HUsVMwUorAGDWvXDUdU0zzR5wKGN1 pcnvu9vmh+Og== WDCIronportException: Internal Received: from cnf002038.ad.shared (HELO localhost.hgst.com) ([10.84.70.94]) by uls-op-cesaip02.wdc.com with ESMTP; 08 Sep 2020 04:33:30 -0700 From: Damien Le Moal To: buildroot@buildroot.org Date: Tue, 8 Sep 2020 20:33:20 +0900 Message-Id: <20200908113324.1022230-3-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200908113324.1022230-1-damien.lemoal@wdc.com> References: <20200908113324.1022230-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Subject: [Buildroot] [PATCH v2 2/6] arch/config: Make RISC-V MMU optional X-BeenThere: buildroot@busybox.net X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion and development of buildroot List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Carlos Eduardo , Alistair Francis , Drew Fustini , Thomas Petazzoni , Romain Naour , Christoph Hellwig , Thomas De Schampheleire Errors-To: buildroot-bounces@busybox.net Sender: "buildroot" Linux supports No-MMU RISC-V since kernel version 5.8. Make MMU optional to enable building for RISC-V boards that do not have one. Signed-off-by: Damien Le Moal Reviewed-by: Alistair Francis --- arch/Config.in | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/Config.in b/arch/Config.in index 0707c076e2..4a2787c350 100644 --- a/arch/Config.in +++ b/arch/Config.in @@ -210,7 +210,7 @@ config BR2_powerpc64le config BR2_riscv bool "RISCV" - select BR2_ARCH_HAS_MMU_MANDATORY + select BR2_ARCH_HAS_MMU_OPTIONAL select BR2_ARCH_NEEDS_GCC_AT_LEAST_7 help RISC-V is an open, free Instruction Set Architecture created