From patchwork Sat Jun 2 22:09:43 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Martin X-Patchwork-Id: 162466 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from fraxinus.osuosl.org (fraxinus.osuosl.org [140.211.166.137]) by ozlabs.org (Postfix) with ESMTP id 7547EB6FA9 for ; Sun, 3 Jun 2012 08:11:17 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by fraxinus.osuosl.org (Postfix) with ESMTP id 665ECFFC6F; Sat, 2 Jun 2012 22:11:16 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from fraxinus.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id y9kF7f-TsuUz; Sat, 2 Jun 2012 22:11:09 +0000 (UTC) Received: from ash.osuosl.org (ash.osuosl.org [140.211.166.34]) by fraxinus.osuosl.org (Postfix) with ESMTP id AD31010BA57; Sat, 2 Jun 2012 22:10:53 +0000 (UTC) X-Original-To: buildroot@lists.busybox.net Delivered-To: buildroot@osuosl.org Received: from whitealder.osuosl.org (whitealder.osuosl.org [140.211.166.138]) by ash.osuosl.org (Postfix) with ESMTP id 598038F753 for ; Sat, 2 Jun 2012 22:10:52 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by whitealder.osuosl.org (Postfix) with ESMTP id 566278D6FD for ; Sat, 2 Jun 2012 22:10:52 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from whitealder.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id NZxmY0ZoJlIo for ; Sat, 2 Jun 2012 22:10:48 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from mail-wg0-f53.google.com (mail-wg0-f53.google.com [74.125.82.53]) by whitealder.osuosl.org (Postfix) with ESMTPS id 1CD848D6BC for ; Sat, 2 Jun 2012 22:10:47 +0000 (UTC) Received: by wgbfm10 with SMTP id fm10so2737433wgb.10 for ; Sat, 02 Jun 2012 15:10:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=0XKZaz9v3JLrTa8eiCQ1I+3aQUVFD83v3g4iyhzga3o=; b=PlIMOmlKSsZYc8GTReLhkxZYAUlekk1MclSH4SUsuT6crqol9vpEIkUjH9efVo0R/M FfN8jAe6XW3Nk/29F5BEwyrU9sB5LoR9ykhzPcyQfADJlzpEkFHSPG+8oEfyNXV3L82o loZnzxiHndB0CGoYQRCFt8rumPJv8RkNKcYCPORnI61fv/ei19D1BB8Bp32d1iACpiTT NWem2Guxp/3Z3+q0WkBU19rT8ZksoExrDFqnfxR9ayp97yC43bCgIQaG2UfIhXDaLhc8 ACkY3IoUuuuT6dZ/TVgkOvu4vfbJ21GS7D/mTVJgwx2fFr+a8HjmV01PVnLLtD52F1a3 1JFw== Received: by 10.216.140.33 with SMTP id d33mr6204118wej.113.1338675046322; Sat, 02 Jun 2012 15:10:46 -0700 (PDT) Received: from localhost.localdomain (ivr94-4-82-229-165-48.fbx.proxad.net. [82.229.165.48]) by mx.google.com with ESMTPS id i10sm12505433wiy.10.2012.06.02.15.10.44 (version=SSLv3 cipher=OTHER); Sat, 02 Jun 2012 15:10:45 -0700 (PDT) From: Samuel Martin To: buildroot@busybox.net Date: Sun, 3 Jun 2012 00:09:43 +0200 Message-Id: <1338674987-2053-2-git-send-email-s.martin49@gmail.com> X-Mailer: git-send-email 1.7.10.3 In-Reply-To: <1338674987-2053-1-git-send-email-s.martin49@gmail.com> References: <1338674987-2053-1-git-send-email-s.martin49@gmail.com> Subject: [Buildroot] [PATCH v2 1/5] target: add symbols for i386/x86_64 cpu features X-BeenThere: buildroot@busybox.net X-Mailman-Version: 2.1.14 Precedence: list List-Id: Discussion and development of buildroot List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: buildroot-bounces@busybox.net Sender: buildroot-bounces@busybox.net Selecting the target architecture variant automatically selects the appropriated set of features. Signed-off-by: Samuel Martin diff --git a/target/Config.in.arch b/target/Config.in.arch index 25ff750..9908b58 100644 --- a/target/Config.in.arch +++ b/target/Config.in.arch @@ -242,7 +242,7 @@ choice default BR2_mips_1 if BR2_mipsel help Specific CPU variant to use - + 64bit cabable: 3, 4, 64, 64r2 non-64bit capable: 1, 2, 32, 32r2 @@ -325,6 +325,31 @@ endchoice # gcc builds libstdc++ differently depending on the # host tuplet given to it, so let people choose # + +# i386/x86_64 cpu features +config BR2_CPU_HAS_MMX + bool +config BR2_CPU_HAS_SSE + bool +config BR2_CPU_HAS_SSE2 + bool +config BR2_CPU_HAS_SSE3 + bool +config BR2_CPU_HAS_SSSE3 + bool +config BR2_CPU_HAS_SSE41 + bool +config BR2_CPU_HAS_SSE42 + bool +config BR2_CPU_HAS_SSE4 + bool +config BR2_CPU_HAS_SSE4A + bool +config BR2_CPU_HAS_3DNOW + bool +config BR2_CPU_HAS_ABM + bool + choice prompt "Target Architecture Variant" depends on BR2_i386 @@ -344,46 +369,106 @@ config BR2_x86_pentiumpro bool "pentium pro" config BR2_x86_pentium_mmx bool "pentium MMX" + select BR2_CPU_HAS_MMX config BR2_x86_pentium_m bool "pentium mobile" config BR2_x86_pentium2 bool "pentium2" + select BR2_CPU_HAS_MMX config BR2_x86_pentium3 bool "pentium3" + select BR2_CPU_HAS_MMX + select BR2_CPU_HAS_SSE config BR2_x86_pentium4 bool "pentium4" + select BR2_CPU_HAS_MMX + select BR2_CPU_HAS_SSE + select BR2_CPU_HAS_SSE2 config BR2_x86_prescott bool "prescott" + select BR2_CPU_HAS_MMX + select BR2_CPU_HAS_SSE + select BR2_CPU_HAS_SSE2 + select BR2_CPU_HAS_SSE3 config BR2_x86_nocona bool "nocona" + select BR2_CPU_HAS_MMX + select BR2_CPU_HAS_SSE + select BR2_CPU_HAS_SSE2 + select BR2_CPU_HAS_SSE3 config BR2_x86_core2 bool "core2" + select BR2_CPU_HAS_MMX + select BR2_CPU_HAS_SSE + select BR2_CPU_HAS_SSE2 + select BR2_CPU_HAS_SSE3 + select BR2_CPU_HAS_SSSE3 config BR2_x86_atom bool "atom" + select BR2_CPU_HAS_MMX + select BR2_CPU_HAS_SSE + select BR2_CPU_HAS_SSE2 + select BR2_CPU_HAS_SSE3 + select BR2_CPU_HAS_SSSE3 config BR2_x86_k6 bool "k6" + select BR2_CPU_HAS_MMX config BR2_x86_k6_2 bool "k6-2" + select BR2_CPU_HAS_MMX + select BR2_CPU_HAS_3DNOW config BR2_x86_athlon bool "athlon" + select BR2_CPU_HAS_MMX + select BR2_CPU_HAS_3DNOW config BR2_x86_athlon_4 bool "athlon-4" + select BR2_CPU_HAS_MMX + select BR2_CPU_HAS_3DNOW + select BR2_CPU_HAS_SSE config BR2_x86_opteron bool "opteron" + select BR2_CPU_HAS_MMX + select BR2_CPU_HAS_3DNOW + select BR2_CPU_HAS_SSE + select BR2_CPU_HAS_SSE2 config BR2_x86_opteron_sse3 bool "opteron w/ SSE3" + select BR2_CPU_HAS_MMX + select BR2_CPU_HAS_3DNOW + select BR2_CPU_HAS_SSE + select BR2_CPU_HAS_SSE2 + select BR2_CPU_HAS_SSE3 config BR2_x86_barcelona bool "barcelona" + select BR2_CPU_HAS_MMX + select BR2_CPU_HAS_3DNOW + select BR2_CPU_HAS_SSE + select BR2_CPU_HAS_SSE2 + select BR2_CPU_HAS_SSE3 + select BR2_CPU_HAS_SSE4A + select BR2_CPU_HAS_ABM config BR2_x86_geode bool "geode" + # Don't include MMX support because there several variant of geode + # processor, some with MMX support, some without. + # See: http://en.wikipedia.org/wiki/Geode_%28processor%29 + select BR2_CPU_HAS_3DNOW config BR2_x86_c3 bool "Via/Cyrix C3 (Samuel/Ezra cores)" + select BR2_CPU_HAS_MMX + select BR2_CPU_HAS_3DNOW config BR2_x86_c32 bool "Via C3-2 (Nehemiah cores)" + select BR2_CPU_HAS_MMX + select BR2_CPU_HAS_SSE config BR2_x86_winchip_c6 bool "IDT Winchip C6" + select BR2_CPU_HAS_MMX config BR2_x86_winchip2 bool "IDT Winchip 2" + select BR2_CPU_HAS_MMX + select BR2_CPU_HAS_3DNOW endchoice choice @@ -397,16 +482,46 @@ config BR2_x86_64_generic bool "generic" config BR2_x86_64_barcelona bool "barcelona" + select BR2_CPU_HAS_MMX + select BR2_CPU_HAS_3DNOW + select BR2_CPU_HAS_SSE + select BR2_CPU_HAS_SSE2 + select BR2_CPU_HAS_SSE3 + select BR2_CPU_HAS_SSE4A + select BR2_CPU_HAS_ABM config BR2_x86_64_opteron_sse3 bool "opteron w/ sse3" + select BR2_CPU_HAS_MMX + select BR2_CPU_HAS_3DNOW + select BR2_CPU_HAS_SSE + select BR2_CPU_HAS_SSE2 + select BR2_CPU_HAS_SSE3 config BR2_x86_64_opteron bool "opteron" + select BR2_CPU_HAS_MMX + select BR2_CPU_HAS_3DNOW + select BR2_CPU_HAS_SSE + select BR2_CPU_HAS_SSE2 config BR2_x86_64_nocona bool "nocona" + select BR2_CPU_HAS_MMX + select BR2_CPU_HAS_SSE + select BR2_CPU_HAS_SSE2 + select BR2_CPU_HAS_SSE3 config BR2_x86_64_core2 bool "core2" + select BR2_CPU_HAS_MMX + select BR2_CPU_HAS_SSE + select BR2_CPU_HAS_SSE2 + select BR2_CPU_HAS_SSE3 + select BR2_CPU_HAS_SSSE3 config BR2_x86_64_atom bool "atom" + select BR2_CPU_HAS_MMX + select BR2_CPU_HAS_SSE + select BR2_CPU_HAS_SSE2 + select BR2_CPU_HAS_SSE3 + select BR2_CPU_HAS_SSSE3 endchoice choice