From patchwork Thu Jun 9 10:45:43 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kirill Batuzov X-Patchwork-Id: 99721 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id B9E0EB6FB9 for ; Thu, 9 Jun 2011 20:51:53 +1000 (EST) Received: from localhost ([::1]:42462 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QUcq6-0006EM-Ax for incoming@patchwork.ozlabs.org; Thu, 09 Jun 2011 06:51:50 -0400 Received: from eggs.gnu.org ([140.186.70.92]:47209) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QUckg-0005eg-DG for qemu-devel@nongnu.org; Thu, 09 Jun 2011 06:46:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QUcke-0008D6-Nr for qemu-devel@nongnu.org; Thu, 09 Jun 2011 06:46:14 -0400 Received: from smtp.ispras.ru ([83.149.198.202]:52097) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QUckd-0008CJ-VN for qemu-devel@nongnu.org; Thu, 09 Jun 2011 06:46:12 -0400 Received: from ispserv.ispras.ru (ispserv.ispras.ru [83.149.198.72]) by smtp.ispras.ru (Postfix) with ESMTP id 9DC1B5D4145; Thu, 9 Jun 2011 14:41:04 +0400 (MSD) Received: from bulbul.intra.ispras.ru (winnie.ispras.ru [83.149.198.236]) by ispserv.ispras.ru (Postfix) with ESMTP id 0BC3B3FC5C; Thu, 9 Jun 2011 14:45:59 +0400 (MSD) From: Kirill Batuzov To: qemu-devel@nongnu.org Date: Thu, 9 Jun 2011 14:45:43 +0400 Message-Id: <1307616344-27161-6-git-send-email-batuzovk@ispras.ru> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1307616344-27161-1-git-send-email-batuzovk@ispras.ru> References: <1307616344-27161-1-git-send-email-batuzovk@ispras.ru> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6, seldom 2.4 (older, 4) X-Received-From: 83.149.198.202 Cc: zhur@ispras.ru Subject: [Qemu-devel] [PATCH v2 5/6] Do constant folding for shift operations. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Perform constant forlding for SHR, SHL, SAR, ROTR, ROTL operations. Signed-off-by: Kirill Batuzov --- tcg/optimize.c | 86 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 86 insertions(+), 0 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 0bd8c78..653f399 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -95,6 +95,11 @@ static int op_bits(int op) case INDEX_op_and_i32: case INDEX_op_or_i32: case INDEX_op_xor_i32: + case INDEX_op_shl_i32: + case INDEX_op_shr_i32: + case INDEX_op_sar_i32: + case INDEX_op_rotl_i32: + case INDEX_op_rotr_i32: return 32; #if TCG_TARGET_REG_BITS == 64 case INDEX_op_mov_i64: @@ -104,6 +109,11 @@ static int op_bits(int op) case INDEX_op_and_i64: case INDEX_op_or_i64: case INDEX_op_xor_i64: + case INDEX_op_shl_i64: + case INDEX_op_shr_i64: + case INDEX_op_sar_i64: + case INDEX_op_rotl_i64: + case INDEX_op_rotr_i64: return 64; #endif default: @@ -177,6 +187,62 @@ static TCGArg do_constant_folding_2(int op, TCGArg x, TCGArg y) #endif return x ^ y; + case INDEX_op_shl_i32: +#if TCG_TARGET_REG_BITS == 64 + y &= 0xffffffff; + case INDEX_op_shl_i64: +#endif + return x << y; + + case INDEX_op_shr_i32: +#if TCG_TARGET_REG_BITS == 64 + x &= 0xffffffff; + y &= 0xffffffff; + case INDEX_op_shr_i64: +#endif + /* Assuming TCGArg to be unsigned */ + return x >> y; + + case INDEX_op_sar_i32: +#if TCG_TARGET_REG_BITS == 64 + x &= 0xffffffff; + y &= 0xffffffff; +#endif + return (int32_t)x >> (int32_t)y; + +#if TCG_TARGET_REG_BITS == 64 + case INDEX_op_sar_i64: + return (int64_t)x >> (int64_t)y; +#endif + + case INDEX_op_rotr_i32: +#if TCG_TARGET_REG_BITS == 64 + x &= 0xffffffff; + y &= 0xffffffff; +#endif + x = (x << (32 - y)) | (x >> y); + return x; + +#if TCG_TARGET_REG_BITS == 64 + case INDEX_op_rotr_i64: + x = (x << (64 - y)) | (x >> y); + return x; +#endif + + case INDEX_op_rotl_i32: +#if TCG_TARGET_REG_BITS == 64 + x &= 0xffffffff; + y &= 0xffffffff; +#endif + x = (x << y) | (x >> (32 - y)); + return x; + +#if TCG_TARGET_REG_BITS == 64 + case INDEX_op_rotl_i64: + x = (x << y) | (x >> (64 - y)); + return x; +#endif + default: fprintf(stderr, "Unrecognized operation %d in do_constant_folding.\n", op); @@ -246,8 +312,18 @@ static TCGArg *tcg_constant_folding(TCGContext *s, uint16_t *tcg_opc_ptr, } /* Fallthrough */ case INDEX_op_sub_i32: + case INDEX_op_shl_i32: + case INDEX_op_shr_i32: + case INDEX_op_sar_i32: + case INDEX_op_rotl_i32: + case INDEX_op_rotr_i32: #if TCG_TARGET_REG_BITS == 64 case INDEX_op_sub_i64: + case INDEX_op_shl_i64: + case INDEX_op_shr_i64: + case INDEX_op_sar_i64: + case INDEX_op_rotl_i64: + case INDEX_op_rotr_i64: #endif if (temps[args[1]].state == TCG_TEMP_CONST) { /* Proceed with possible constant folding. */ @@ -377,6 +453,11 @@ static TCGArg *tcg_constant_folding(TCGContext *s, uint16_t *tcg_opc_ptr, case INDEX_op_add_i32: case INDEX_op_sub_i32: case INDEX_op_mul_i32: + case INDEX_op_shl_i32: + case INDEX_op_shr_i32: + case INDEX_op_sar_i32: + case INDEX_op_rotl_i32: + case INDEX_op_rotr_i32: #if TCG_TARGET_REG_BITS == 64 case INDEX_op_and_i64: case INDEX_op_or_i64: @@ -384,6 +465,11 @@ static TCGArg *tcg_constant_folding(TCGContext *s, uint16_t *tcg_opc_ptr, case INDEX_op_add_i64: case INDEX_op_sub_i64: case INDEX_op_mul_i64: + case INDEX_op_shl_i64: + case INDEX_op_shr_i64: + case INDEX_op_sar_i64: + case INDEX_op_rotl_i64: + case INDEX_op_rotr_i64: #endif if (temps[args[1]].state == TCG_TEMP_CONST && temps[args[2]].state == TCG_TEMP_CONST) {