| Message ID | 1542097327-6629-16-git-send-email-bmeng.cn@gmail.com |
|---|---|
| State | Superseded |
| Delegated to: | Andes |
| Headers | show |
| Series | riscv: Adding RISC-V CPU and timer driver | expand |
On Tue, 2018-11-13 at 00:22 -0800, Bin Meng wrote: > At present the trap handler returns to M-mode only. Change to > returning to previous privilege level instead. > > Signed-off-by: Bin Meng <bmeng.cn@gmail.com> > --- > > arch/riscv/cpu/mtrap.S | 3 --- > 1 file changed, 3 deletions(-) > Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
diff --git a/arch/riscv/cpu/mtrap.S b/arch/riscv/cpu/mtrap.S index 6c0eac6..c9010c7 100644 --- a/arch/riscv/cpu/mtrap.S +++ b/arch/riscv/cpu/mtrap.S @@ -68,9 +68,6 @@ trap_entry: jal handle_trap csrw mepc, a0 - /* Remain in M-mode after mret */ - li t0, MSTATUS_MPP - csrs mstatus, t0 LREG x1, 1 * REGBYTES(sp) LREG x3, 3 * REGBYTES(sp) LREG x4, 4 * REGBYTES(sp)
At present the trap handler returns to M-mode only. Change to returning to previous privilege level instead. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> --- arch/riscv/cpu/mtrap.S | 3 --- 1 file changed, 3 deletions(-)