[U-Boot,08/19] riscv: Enlarge the default SYS_MALLOC_F_LEN

Message ID	1542097327-6629-9-git-send-email-bmeng.cn@gmail.com
State	Superseded
Delegated to:	Andes
Headers	show Return-Path: <u-boot-bounces@lists.denx.de> From: Bin Meng <bmeng.cn@gmail.com> To: Rick Chen <rick@andestech.com>, Simon Glass <sjg@chromium.org>, Lukas Auer <lukas.auer@aisec.fraunhofer.de>, U-Boot Mailing List <u-boot@lists.denx.de> Date: Tue, 13 Nov 2018 00:21:56 -0800 Message-Id: <1542097327-6629-9-git-send-email-bmeng.cn@gmail.com> In-Reply-To: <1542097327-6629-1-git-send-email-bmeng.cn@gmail.com> References: <1542097327-6629-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH 08/19] riscv: Enlarge the default SYS_MALLOC_F_LEN Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
Series	riscv: Adding RISC-V CPU and timer driver \| expand [U-Boot,00/19] riscv: Adding RISC-V CPU and timer driver [U-Boot,01/19] riscv: add Kconfig entries for the code model [U-Boot,02/19] dm: cpu: Add timebase frequency to the platdata [U-Boot,03/19] riscv: qemu: Create a simple-bus driver for the soc node [U-Boot,04/19] cpu: Add a RISC-V CPU driver [U-Boot,05/19] riscv: Add a SYSCON driver for Core Local Interruptor [U-Boot,06/19] timer: Add driver for RISC-V privileged architecture defined timer [U-Boot,07/19] riscv: kconfig: Allow platform to specify Kconfig options [U-Boot,08/19] riscv: Enlarge the default SYS_MALLOC_F_LEN [U-Boot,09/19] riscv: qemu: Probe cpus during boot [U-Boot,10/19] riscv: Add CSR numbers [U-Boot,11/19] riscv: Add exception codes for xcause register [U-Boot,12/19] riscv: Do some basic architecture level cpu initialization [U-Boot,13/19] riscv: Move trap handler codes to mtrap.S [U-Boot,14/19] riscv: Fix context restore before returning from trap handler [U-Boot,15/19] riscv: Return to previous privilege level after trap handling [U-Boot,16/19] riscv: Adjust the _exit_trap() position to come before handle_trap() [U-Boot,17/19] riscv: Pass correct exception code to _exit_trap() [U-Boot,18/19] riscv: Refactor handle_trap() a little for future extension [U-Boot,19/19] riscv: Allow U-Boot to run on hart 0 only

Message ID

1542097327-6629-9-git-send-email-bmeng.cn@gmail.com

State

Superseded

Delegated to:

Andes

Headers

From: Bin Meng <bmeng.cn@gmail.com>
To: Rick Chen <rick@andestech.com>, Simon Glass <sjg@chromium.org>,
	Lukas Auer <lukas.auer@aisec.fraunhofer.de>,
	U-Boot Mailing List <u-boot@lists.denx.de>
Date: Tue, 13 Nov 2018 00:21:56 -0800
Message-Id: <1542097327-6629-9-git-send-email-bmeng.cn@gmail.com>
In-Reply-To: <1542097327-6629-1-git-send-email-bmeng.cn@gmail.com>
References: <1542097327-6629-1-git-send-email-bmeng.cn@gmail.com>
Subject: [U-Boot] [PATCH 08/19] riscv: Enlarge the default SYS_MALLOC_F_LEN
Precedence: list
MIME-Version: 1.0
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: base64
Errors-To: u-boot-bounces@lists.denx.de
Sender: "U-Boot" <u-boot-bounces@lists.denx.de>

Series

riscv: Adding RISC-V CPU and timer driver | expand

Comments

Lukas Auer Nov. 14, 2018, 10:11 p.m. UTC | #1

On Tue, 2018-11-13 at 00:21 -0800, Bin Meng wrote:
> Increase the heap size for the pre-relocation stage, so that CPU
> driver can be loaded.
> 
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
> 
>  arch/riscv/Kconfig | 3 +++
>  1 file changed, 3 insertions(+)
> 

Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 4292ffd..f020060 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -87,4 +87,7 @@  config RISCV_CLINT
 	  The CLINT block holds memory-mapped control and status registers
 	  associated with software and timer interrupts.
 
+config SYS_MALLOC_F_LEN
+	default 0x1000
+
 endmenu

[U-Boot,08/19] riscv: Enlarge the default SYS_MALLOC_F_LEN

Commit Message

Comments

Patch