| Message ID | 20181111233622.8976-5-f4bug@amsat.org |
|---|---|
| State | New |
| Headers | show |
| Series | decodetree: Add tokens to ease checking ISA flags | expand |
On 11/12/18 12:36 AM, Philippe Mathieu-Daudé wrote: > The DisasContext is already initialized from the CPUMIPSState in > mips_tr_init_disas_context(). > > Suggested-by: Richard Henderson <rth@twiddle.net> > Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > --- > target/mips/translate.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/target/mips/translate.c b/target/mips/translate.c index f5e8d0b4d2..e726f3ec00 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16534,7 +16534,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) check_insn(ctx, ASE_MIPS3D); /* Fall through */ do_cp1branch: - if (env->CP0_Config1 & (1 << CP0C1_FP)) { + if (ctx->CP0_Config1 & (1 << CP0C1_FP)) { check_cp1_enabled(ctx); gen_compute_branch1(ctx, mips32_op, (ctx->opcode >> 18) & 0x7, imm << 1); @@ -23809,7 +23809,7 @@ static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx) break; case OPC_MOVCI: check_insn(ctx, ISA_MIPS4 | ISA_MIPS32); - if (env->CP0_Config1 & (1 << CP0C1_FP)) { + if (ctx->CP0_Config1 & (1 << CP0C1_FP)) { check_cp1_enabled(ctx); gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7, (ctx->opcode >> 16) & 1);
The DisasContext is already initialized from the CPUMIPSState in mips_tr_init_disas_context(). Suggested-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> --- target/mips/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)