From patchwork Sat Nov 10 21:02:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= X-Patchwork-Id: 996002 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rere.qmqm.pl Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=rere.qmqm.pl header.i=@rere.qmqm.pl header.b="AnhvO/nT"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42sqSd6X5lz9sC7 for ; Sun, 11 Nov 2018 08:11:13 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725815AbeKKG5d (ORCPT ); Sun, 11 Nov 2018 01:57:33 -0500 Received: from rere.qmqm.pl ([91.227.64.183]:21183 "EHLO rere.qmqm.pl" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725772AbeKKG5d (ORCPT ); Sun, 11 Nov 2018 01:57:33 -0500 X-Greylist: delayed 528 seconds by postgrey-1.27 at vger.kernel.org; Sun, 11 Nov 2018 01:57:30 EST Received: from remote.user (localhost [127.0.0.1]) by rere.qmqm.pl (Postfix) with ESMTPSA id 42sqFH0pGMzSL; Sat, 10 Nov 2018 22:01:23 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=rere.qmqm.pl; s=1; t=1541883683; bh=0EVKyGgqyMdhKmcjfkXV4TTARorA61c/lj+NDszHBqc=; h=Date:In-Reply-To:References:From:Subject:To:Cc:From; b=AnhvO/nT9Zkc95KHULdvrHD6ryd4/zPEnJsiSLAIVJhuNCFBtYrgaZJD+LWyYhFeo INeBlPnBpKfIVNi44AuiG+xuek4gWMqy8Lv0AK+t155m2ddg9bdmZEwTor8DsT59oQ hJn3llf9+tRkdSUXX6Dj4YD5jru8VXmdIiwwZ45OsYmrjGd6YC8S6XMRs0011lJKIY 2PbuluPSqh+57BQ/IGXY1qzP+nYc2bAlQZ1XAuAgJhHl7hArAnHADut+xM7fq4owor oXPymteBOzPK5VHI8P6yf5qZ04IHMPR1dIa5Hv5gVEK/NHRAlrNLJ/Q+E2qP0uqjn2 5cnVxmbjvu7qQ== X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.100.2 at mail Date: Sat, 10 Nov 2018 22:02:22 +0100 Message-Id: In-Reply-To: References: From: =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= Subject: [PATCH 1/3] ARM: cache-l2x0: share l2x0_base with PMU code MIME-Version: 1.0 To: linux-arm-kernel@lists.infradead.org Cc: Dmitry Osipenko , linux-tegra@vger.kernel.org, Mark Rutland , Russell King Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Avoid l2x0_base duplication with PMU driver by sharing it and using l2x0_name as the 'enabled' flag instead. Since l2x0_name is not used for anything else, mark it as __initdata. This will also be needed for cache maintenance with Trusted Foundations firmware. Signed-off-by: Michał Mirosław --- arch/arm/include/asm/hardware/cache-l2x0.h | 6 ++++-- arch/arm/mm/cache-l2x0-pmu.c | 9 +++------ arch/arm/mm/cache-l2x0.c | 6 +++--- 3 files changed, 10 insertions(+), 11 deletions(-) diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h index 736292b42fca..665eb0758417 100644 --- a/arch/arm/include/asm/hardware/cache-l2x0.h +++ b/arch/arm/include/asm/hardware/cache-l2x0.h @@ -167,11 +167,11 @@ static inline int l2x0_of_init(u32 aux_val, u32 aux_mask) #endif #ifdef CONFIG_CACHE_L2X0_PMU -void l2x0_pmu_register(void __iomem *base, u32 part); +void l2x0_pmu_register(u32 part); void l2x0_pmu_suspend(void); void l2x0_pmu_resume(void); #else -static inline void l2x0_pmu_register(void __iomem *base, u32 part) {} +static inline void l2x0_pmu_register(u32 part) {} static inline void l2x0_pmu_suspend(void) {} static inline void l2x0_pmu_resume(void) {} #endif @@ -193,6 +193,8 @@ struct l2x0_regs { unsigned long aux2_ctrl; }; +extern void __iomem *l2x0_base; +extern u32 l2x0_way_mask; /* Bitmask of active ways */ extern struct l2x0_regs l2x0_saved_regs; #endif /* __ASSEMBLY__ */ diff --git a/arch/arm/mm/cache-l2x0-pmu.c b/arch/arm/mm/cache-l2x0-pmu.c index afe5b4c7b164..6be335ae4e2f 100644 --- a/arch/arm/mm/cache-l2x0-pmu.c +++ b/arch/arm/mm/cache-l2x0-pmu.c @@ -29,11 +29,10 @@ #define PMU_NR_COUNTERS 2 -static void __iomem *l2x0_base; static struct pmu *l2x0_pmu; static cpumask_t pmu_cpu; -static const char *l2x0_name; +static const char *__initdata l2x0_name = NULL; static ktime_t l2x0_pmu_poll_period; static struct hrtimer l2x0_pmu_hrtimer; @@ -491,7 +490,7 @@ void l2x0_pmu_resume(void) l2x0_pmu_enable(l2x0_pmu); } -void __init l2x0_pmu_register(void __iomem *base, u32 part) +void __init l2x0_pmu_register(u32 part) { /* * Determine whether we support the PMU, and choose the name for sysfs. @@ -516,15 +515,13 @@ void __init l2x0_pmu_register(void __iomem *base, u32 part) default: return; } - - l2x0_base = base; } static __init int l2x0_pmu_init(void) { int ret; - if (!l2x0_base) + if (!l2x0_name) return 0; l2x0_pmu = kzalloc(sizeof(*l2x0_pmu), GFP_KERNEL); diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index ea1e70ff4568..2b6a023fea3f 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -48,13 +48,13 @@ struct l2c_init_data { #define CACHE_LINE_SIZE 32 -static void __iomem *l2x0_base; static const struct l2c_init_data *l2x0_data; static DEFINE_RAW_SPINLOCK(l2x0_lock); -static u32 l2x0_way_mask; /* Bitmask of active ways */ static u32 l2x0_size; static unsigned long sync_reg_offset = L2X0_CACHE_SYNC; +void __iomem *l2x0_base; +u32 l2x0_way_mask; /* Bitmask of active ways */ struct l2x0_regs l2x0_saved_regs; static bool l2x0_bresp_disable; @@ -900,7 +900,7 @@ static int __init __l2c_init(const struct l2c_init_data *data, pr_info("%s: CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n", data->type, cache_id, aux); - l2x0_pmu_register(l2x0_base, cache_id); + l2x0_pmu_register(cache_id); return 0; }