From patchwork Fri Nov 9 15:33:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudakshina Das X-Patchwork-Id: 995616 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-489533-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="ueNXVVdG"; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=armh.onmicrosoft.com header.i=@armh.onmicrosoft.com header.b="TGMfdo+Y"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42s41m0yvnz9s3x for ; Sat, 10 Nov 2018 02:33:47 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:content-type:mime-version; q=dns; s=default; b=LZgrTNtHJXaFzgZV+0hoo58TskRMPX9TWSgwdOFW5wbPM+NdJW CP+gMV/3sKVsn9d+k0A6kVtI+HBuxXExYM5T9E5MQrRyPAily3RltN5/1748n5PH Y4AN3+GDYO6UOe3qzdKVx901Iuh1kCeLiYp/eIzmd98+TiCEPmrQ7bi60= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:content-type:mime-version; s= default; bh=2cPf83Xa4UrXT39Da5MFD5adBB0=; b=ueNXVVdGY3vAX1RqwWrG pWJsD4FhXO5wICtLZyFETmyCb8NqQ/rC4DNL0uQqKJJuqzMHKrrHOhb13r2L/3R3 sXFC1grREJ6hm+dGp+R99B13L8suuGZql9lXlc0pmA9y91ukdOtrYYKaKu4tlEYM qEsVaJ/qCGHq1QUCVSHvbds= Received: (qmail 49322 invoked by alias); 9 Nov 2018 15:33:34 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 49211 invoked by uid 89); 9 Nov 2018 15:33:34 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_LOTSOFHASH, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS, SPF_PASS autolearn=ham version=3.3.2 spammy=rel, 85 X-HELO: EUR01-DB5-obe.outbound.protection.outlook.com Received: from mail-db5eur01on0077.outbound.protection.outlook.com (HELO EUR01-DB5-obe.outbound.protection.outlook.com) (104.47.2.77) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 09 Nov 2018 15:33:30 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector1-arm-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=kDDT5MFHiuB3or4qMl1+R4R4bRFDFFj6C+iYI2Tu7IY=; b=TGMfdo+Y8HBKkov5akElFtpmWqUHyy0OdExTGLmdrcbV12yN6RZrAo2xB6kTGriQjQc6GpLhj3sqCdsZm1dQVFpbgU4nQlPtljvGbA11p2sqN8vJs0m8p9o/wJFiQM6tmPQZl+VXiDNDhTHX0GBGjUfCrEkBPwVEM1YCNfthkTA= Received: from HE1PR0801MB1722.eurprd08.prod.outlook.com (10.168.149.146) by HE1PR0801MB1292.eurprd08.prod.outlook.com (10.167.247.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1294.28; Fri, 9 Nov 2018 15:33:26 +0000 Received: from HE1PR0801MB1722.eurprd08.prod.outlook.com ([fe80::6545:cf2:3660:1941]) by HE1PR0801MB1722.eurprd08.prod.outlook.com ([fe80::6545:cf2:3660:1941%5]) with mapi id 15.20.1294.034; Fri, 9 Nov 2018 15:33:26 +0000 From: Sudakshina Das To: "gcc-patches@gcc.gnu.org" CC: nd , Ramana Radhakrishnan , Kyrill Tkachov , Richard Earnshaw Subject: [PATCH, GCC, ARM] Enable armv8.5-a and add +sb and +predres for previous ARMv8-a in ARM Date: Fri, 9 Nov 2018 15:33:25 +0000 Message-ID: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Sudi.Das@arm.com; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) MIME-Version: 1.0 X-IsSubscribed: yes Hi This patch adds -march=armv8.5-a to the Arm backend. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools) Armv8.5-A also adds two new security features: - Speculation Barrier instruction - Execution and Data Prediction Restriction Instructions These are made optional to all older Armv8-A versions. Thus we are adding two new options "+sb" and "+predres" to all older Armv8-A. These are passed on to the assembler and have no code generation effects and have already gone in the trunk of binutils. Bootstrapped and regression tested with arm-none-linux-gnueabihf. Is this ok for trunk? Sudi *** gcc/ChangeLog *** 2018-xx-xx Sudakshina Das * config/arm/arm-cpus.in (armv8_5, sb, predres): New features. (ARMv8_5a): New fgroup. (armv8.5-a): New arch. (armv8-a, armv8.1-a, armv8.2-a, armv8.3-a, armv8.4-a): New options sb and predres. * config/arm/arm-tables.opt: Regenerate. * config/arm/t-aprofile: Add matching rules for -march=armv8.5-a * config/arm/t-arm-elf (all_v8_archs): Add armv8.5-a. * config/arm/t-multilib (v8_5_a_simd_variants): New variable. Add matching rules for -march=armv8.5-a and extensions. * doc/invoke.texi (ARM options): Document -march=armv8.5-a. Add sb and predres to all armv8-a except armv8.5-a. *** gcc/testsuite/ChangeLog *** 2018-xx-xx Sudakshina Das * gcc.target/arm/multilib.exp: Add some -march=armv8.5-a combination tests. diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index d82e95a226659948e59b317f07e0fd386ed674a2..e6bcc3c720b64f4c80d9bff101e756de82d760e6 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -114,6 +114,9 @@ define feature armv8_3 # Architecture rel 8.4. define feature armv8_4 +# Architecture rel 8.5. +define feature armv8_5 + # M-Profile security extensions. define feature cmse @@ -174,6 +177,14 @@ define feature quirk_cm3_ldrd # (Very) slow multiply operations. Should probably be a tuning bit. define feature smallmul +# Speculation Barrier Instruction for v8-A architectures, added by +# default to v8.5-A +define feature sb + +# Execution and Data Prediction Restriction Instruction for +# v8-A architectures, added by default from v8.5-A +define feature predres + # Feature groups. Conventionally all (or mostly) upper case. # ALL_FPU lists all the feature bits associated with the floating-point # unit; these will all be removed if the floating-point unit is disabled @@ -235,6 +246,7 @@ define fgroup ARMv8_1a ARMv8a crc32 armv8_1 define fgroup ARMv8_2a ARMv8_1a armv8_2 define fgroup ARMv8_3a ARMv8_2a armv8_3 define fgroup ARMv8_4a ARMv8_3a armv8_4 +define fgroup ARMv8_5a ARMv8_4a armv8_5 sb predres define fgroup ARMv8m_base ARMv6m armv8 cmse tdiv define fgroup ARMv8m_main ARMv7m armv8 cmse define fgroup ARMv8r ARMv8a @@ -505,6 +517,8 @@ begin arch armv8-a option crypto add FP_ARMv8 CRYPTO option nocrypto remove ALL_CRYPTO option nofp remove ALL_FP + option sb add sb + option predres add predres end arch armv8-a begin arch armv8.1-a @@ -517,6 +531,8 @@ begin arch armv8.1-a option crypto add FP_ARMv8 CRYPTO option nocrypto remove ALL_CRYPTO option nofp remove ALL_FP + option sb add sb + option predres add predres end arch armv8.1-a begin arch armv8.2-a @@ -532,6 +548,8 @@ begin arch armv8.2-a option nocrypto remove ALL_CRYPTO option nofp remove ALL_FP option dotprod add FP_ARMv8 DOTPROD + option sb add sb + option predres add predres end arch armv8.2-a begin arch armv8.3-a @@ -547,6 +565,8 @@ begin arch armv8.3-a option nocrypto remove ALL_CRYPTO option nofp remove ALL_FP option dotprod add FP_ARMv8 DOTPROD + option sb add sb + option predres add predres end arch armv8.3-a begin arch armv8.4-a @@ -560,8 +580,23 @@ begin arch armv8.4-a option crypto add FP_ARMv8 CRYPTO DOTPROD option nocrypto remove ALL_CRYPTO option nofp remove ALL_FP + option sb add sb + option predres add predres end arch armv8.4-a +begin arch armv8.5-a + tune for cortex-a53 + tune flags CO_PROC + base 8A + profile A + isa ARMv8_5a + option simd add FP_ARMv8 DOTPROD + option fp16 add fp16 fp16fml FP_ARMv8 DOTPROD + option crypto add FP_ARMv8 CRYPTO DOTPROD + option nocrypto remove ALL_CRYPTO + option nofp remove ALL_FP +end arch armv8.5-a + begin arch armv8-m.base tune for cortex-m23 base 8M_BASE diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt index eacee746a39912d04aa03c636f9a95e0e72ce43b..dde6e137db5598d92df6a1e69a63140146bf7372 100644 --- a/gcc/config/arm/arm-tables.opt +++ b/gcc/config/arm/arm-tables.opt @@ -377,19 +377,22 @@ EnumValue Enum(arm_arch) String(armv8.4-a) Value(24) EnumValue -Enum(arm_arch) String(armv8-m.base) Value(25) +Enum(arm_arch) String(armv8.5-a) Value(25) EnumValue -Enum(arm_arch) String(armv8-m.main) Value(26) +Enum(arm_arch) String(armv8-m.base) Value(26) EnumValue -Enum(arm_arch) String(armv8-r) Value(27) +Enum(arm_arch) String(armv8-m.main) Value(27) EnumValue -Enum(arm_arch) String(iwmmxt) Value(28) +Enum(arm_arch) String(armv8-r) Value(28) EnumValue -Enum(arm_arch) String(iwmmxt2) Value(29) +Enum(arm_arch) String(iwmmxt) Value(29) + +EnumValue +Enum(arm_arch) String(iwmmxt2) Value(30) Enum Name(arm_fpu) Type(enum fpu_type) diff --git a/gcc/config/arm/t-aprofile b/gcc/config/arm/t-aprofile index 7b55599d42947fea880483bf0a7a62f33bb1a1fb..945a938b4fed1283290224e836782fbb3069e9d9 100644 --- a/gcc/config/arm/t-aprofile +++ b/gcc/config/arm/t-aprofile @@ -103,6 +103,13 @@ MULTILIB_MATCHES += march?armv8-a=march?armv8.4-a MULTILIB_MATCHES += $(foreach ARCH, $(v8_4_a_simd_variants), \ march?armv8-a+simd=march?armv8.4-a$(ARCH)) +# Baseline v8.5-a: map down to baseline v8-a +MULTILIB_MATCHES += march?armv8-a=march?armv8.5-a + +# Map all v8.5-a SIMD variants to v8-a+simd +MULTILIB_MATCHES += $(foreach ARCH, $(v8_5_a_simd_variants), \ + march?armv8-a+simd=march?armv8.5-a$(ARCH)) + # Use Thumb libraries for everything. MULTILIB_REUSE += mthumb/march.armv7-a/mfloat-abi.soft=marm/march.armv7-a/mfloat-abi.soft diff --git a/gcc/config/arm/t-arm-elf b/gcc/config/arm/t-arm-elf index 3506b16e929fa30af90e0a1bf20653ed6a098eaa..d8853aa8f5afcccb0e4f4187c44de01a23b89402 100644 --- a/gcc/config/arm/t-arm-elf +++ b/gcc/config/arm/t-arm-elf @@ -46,7 +46,8 @@ all_early_arch := armv5tej armv6 armv6j armv6k armv6z armv6kz \ all_v7_a_r := armv7-a armv7ve armv7-r -all_v8_archs := armv8-a armv8-a+crc armv8.1-a armv8.2-a armv8.3-a armv8.4-a +all_v8_archs := armv8-a armv8-a+crc armv8.1-a armv8.2-a armv8.3-a armv8.4-a \ + armv8.5-a # No floating point variants, require thumb1 softfp all_nofp_t := armv6-m armv6s-m armv8-m.base diff --git a/gcc/config/arm/t-multilib b/gcc/config/arm/t-multilib index 25788ad09851daf41038b1578307bf23b7f34a94..eba038f9d20bc54bef7bdb7fa1c0e7028d954ed7 100644 --- a/gcc/config/arm/t-multilib +++ b/gcc/config/arm/t-multilib @@ -70,7 +70,8 @@ v8_a_simd_variants := $(call all_feat_combs, simd crypto) v8_1_a_simd_variants := $(call all_feat_combs, simd crypto) v8_2_a_simd_variants := $(call all_feat_combs, simd fp16 fp16fml crypto dotprod) v8_4_a_simd_variants := $(call all_feat_combs, simd fp16 crypto) -v8_r_nosimd_variants := +crc +v8_5_a_simd_variants := $(call all_feat_combs, simd fp16 crypto) +v8_r_nosimd_variants := +cr5 ifneq (,$(HAS_APROFILE)) include $(srcdir)/config/arm/t-aprofile @@ -163,6 +164,13 @@ MULTILIB_MATCHES += march?armv7=march?armv8.4-a MULTILIB_MATCHES += $(foreach ARCH, $(v8_4_a_simd_variants), \ march?armv7+fp=march?armv8.4-a$(ARCH)) +# Baseline v8.5-a: map down to baseline v8-a +MULTILIB_MATCHES += march?armv7=march?armv8.5-a + +# Map all v8.5-a SIMD variants +MULTILIB_MATCHES += $(foreach ARCH, $(v8_5_a_simd_variants), \ + march?armv7+fp=march?armv8.5-a$(ARCH)) + # Use Thumb libraries for everything. MULTILIB_REUSE += mthumb/march.armv7/mfloat-abi.soft=marm/march.armv7/mfloat-abi.soft @@ -176,4 +184,4 @@ MULTILIB_REUSE += $(foreach MODE, arm thumb, \ $(foreach ARCH, armv7, \ mthumb/march.$(ARCH)/mfloat-abi.soft=m$(MODE)/march.$(ARCH)/mfloat-abi.softfp)) -endif # Not APROFILE. \ No newline at end of file +endif # Not APROFILE. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 9e322b79a9f3405bac6b3a3c4b6cb15a61bef7a3..df9f00e054db795bc5478a2ac9ebbdc4bf82b73a 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -16388,6 +16388,7 @@ Permissible names are: @samp{armv7}, @samp{armv7-a}, @samp{armv7ve}, @samp{armv8-a}, @samp{armv8.1-a}, @samp{armv8.2-a}, @samp{armv8.3-a}, @samp{armv8.4-a}, +@samp{armv8.5-a}, @samp{armv7-r}, @samp{armv8-r}, @samp{armv6-m}, @samp{armv6s-m}, @@ -16564,6 +16565,10 @@ The cryptographic instructions. Disable the cryptographic instructions. @item +nofp Disable the floating-point, Advanced SIMD and cryptographic instructions. +@item +sb +Speculation Barrier Instruction. +@item +predres +Execution and Data Prediction Restriction Instructions. @end table @item armv8.1-a @@ -16580,6 +16585,12 @@ Disable the cryptographic instructions. @item +nofp Disable the floating-point, Advanced SIMD and cryptographic instructions. + +@item +sb +Speculation Barrier Instruction. + +@item +predres +Execution and Data Prediction Restriction Instructions. @end table @item armv8.2-a @@ -16609,6 +16620,12 @@ Disable the cryptographic extension. @item +nofp Disable the floating-point, Advanced SIMD and cryptographic instructions. + +@item +sb +Speculation Barrier Instruction. + +@item +predres +Execution and Data Prediction Restriction Instructions. @end table @item armv8.4-a @@ -16632,6 +16649,35 @@ Disable the cryptographic extension. @item +nofp Disable the floating-point, Advanced SIMD and cryptographic instructions. + +@item +sb +Speculation Barrier Instruction. + +@item +predres +Execution and Data Prediction Restriction Instructions. +@end table + +@item armv8.5-a +@table @samp +@item +fp16 +The half-precision floating-point data processing instructions. +This also enables the Advanced SIMD and floating-point instructions as well +as the Dot Product extension and the half-precision floating-point fmla +extension. + +@item +simd +The ARMv8.3-A Advanced SIMD and floating-point instructions as well as the +Dot Product extension. + +@item +crypto +The cryptographic instructions. This also enables the Advanced SIMD and +floating-point instructions as well as the Dot Product extension. + +@item +nocrypto +Disable the cryptographic extension. + +@item +nofp +Disable the floating-point, Advanced SIMD and cryptographic instructions. @end table @item armv7-r diff --git a/gcc/testsuite/gcc.target/arm/multilib.exp b/gcc/testsuite/gcc.target/arm/multilib.exp index 04da2b0a20eda299c5749e8702ac1c5a8c937900..cdd06f8265f9b1ac76d4aae9be003c519682eee6 100644 --- a/gcc/testsuite/gcc.target/arm/multilib.exp +++ b/gcc/testsuite/gcc.target/arm/multilib.exp @@ -108,6 +108,14 @@ if {[multilib_config "aprofile"] } { {-march=armv8.4-a+simd+fp16 -mfloat-abi=softfp} "thumb/v8-a+simd/softfp" {-march=armv8.4-a+simd+fp16+nofp -mfloat-abi=softfp} "thumb/v8-a/nofp" {-march=armv8.4-a+simd+nofp+fp16 -mfloat-abi=softfp} "thumb/v8-a+simd/softfp" + {-march=armv8.5-a+crypto -mfloat-abi=soft} "thumb/v8-a/nofp" + {-march=armv8.5-a+simd+crypto -mfloat-abi=softfp} "thumb/v8-a+simd/softfp" + {-march=armv8.5-a+simd+crypto+nofp -mfloat-abi=softfp} "thumb/v8-a/nofp" + {-march=armv8.5-a+simd+nofp+crypto -mfloat-abi=softfp} "thumb/v8-a+simd/softfp" + {-march=armv8.5-a+fp16 -mfloat-abi=soft} "thumb/v8-a/nofp" + {-march=armv8.5-a+simd+fp16 -mfloat-abi=softfp} "thumb/v8-a+simd/softfp" + {-march=armv8.5-a+simd+fp16+nofp -mfloat-abi=softfp} "thumb/v8-a/nofp" + {-march=armv8.5-a+simd+nofp+fp16 -mfloat-abi=softfp} "thumb/v8-a+simd/softfp" {-mcpu=cortex-a53+crypto -mfloat-abi=hard} "thumb/v8-a+simd/hard" {-mcpu=cortex-a53+nofp -mfloat-abi=softfp} "thumb/v8-a/nofp" {-march=armv8-a+crc -mfloat-abi=hard -mfpu=vfp} "thumb/v8-a+simd/hard"