From patchwork Wed Jun 8 18:55:19 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 99546 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 89E53B6FDD for ; Thu, 9 Jun 2011 05:41:04 +1000 (EST) Received: from localhost ([::1]:41136 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QUOce-0002Wd-Nj for incoming@patchwork.ozlabs.org; Wed, 08 Jun 2011 15:41:01 -0400 Received: from eggs.gnu.org ([140.186.70.92]:42071) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QUNui-0006OB-7W for qemu-devel@nongnu.org; Wed, 08 Jun 2011 14:55:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QUNuf-0006BS-Pg for qemu-devel@nongnu.org; Wed, 08 Jun 2011 14:55:36 -0400 Received: from fmmailgate02.web.de ([217.72.192.227]:32859) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QUNue-0006Ay-II for qemu-devel@nongnu.org; Wed, 08 Jun 2011 14:55:33 -0400 Received: from smtp01.web.de ( [172.20.0.243]) by fmmailgate02.web.de (Postfix) with ESMTP id 7013D1A2C3CCB; Wed, 8 Jun 2011 20:55:28 +0200 (CEST) Received: from [87.173.123.15] (helo=af.local) by smtp01.web.de with asmtp (WEB.DE 4.110 #2) id 1QUNuZ-0002zl-01; Wed, 08 Jun 2011 20:55:27 +0200 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: qemu-devel@nongnu.org Date: Wed, 8 Jun 2011 20:55:19 +0200 Message-Id: <1307559319-16183-13-git-send-email-andreas.faerber@web.de> X-Mailer: git-send-email 1.7.5.3 In-Reply-To: <1307559319-16183-12-git-send-email-andreas.faerber@web.de> References: <4DEF2F25.5070104@redhat.com> <1307559319-16183-1-git-send-email-andreas.faerber@web.de> <1307559319-16183-2-git-send-email-andreas.faerber@web.de> <1307559319-16183-3-git-send-email-andreas.faerber@web.de> <1307559319-16183-4-git-send-email-andreas.faerber@web.de> <1307559319-16183-5-git-send-email-andreas.faerber@web.de> <1307559319-16183-6-git-send-email-andreas.faerber@web.de> <1307559319-16183-7-git-send-email-andreas.faerber@web.de> <1307559319-16183-8-git-send-email-andreas.faerber@web.de> <1307559319-16183-9-git-send-email-andreas.faerber@web.de> <1307559319-16183-10-git-send-email-andreas.faerber@web.de> <1307559319-16183-11-git-send-email-andreas.faerber@web.de> <1307559319-16183-12-git-send-email-andreas.faerber@web.de> MIME-Version: 1.0 X-Sender: Andreas.Faerber@web.de X-Provags-ID: V01U2FsdGVkX199BydNGB+jtIebNpnJLOw/4mSmepyvJrwmXAiL BceGvmw7CkIH7xoXglIbUP0tzIgzdTffqwCl6IEbmj7WeFpQCE eTCj6uqlPKhzbidFyWPA== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 X-Received-From: 217.72.192.227 Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= , hpoussin@reactos.org, kraxel@redhat.com Subject: [Qemu-devel] [RFC v4 12/12] prep: Add pc87312 Super I/O emulation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Hervé Poussineau Create all devices ahead of time and enable/disable instead. Check the qdev properties for whether a change is necessary. Signed-off-by: Andreas Färber --- Makefile.objs | 1 + default-configs/ppc-softmmu.mak | 2 + hw/pc87312.c | 470 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 473 insertions(+), 0 deletions(-) create mode 100644 hw/pc87312.c diff --git a/Makefile.objs b/Makefile.objs index 66ffad4..3d9fc7a 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -206,6 +206,7 @@ hw-obj-$(CONFIG_SMARTCARD_NSS) += ccid-card-emulated.o # PPC devices hw-obj-$(CONFIG_OPENPIC) += openpic.o hw-obj-$(CONFIG_PREP_PCI) += prep_pci.o +hw-obj-$(CONFIG_PC87312) += pc87312.o # Mac shared devices hw-obj-$(CONFIG_MACIO) += macio.o hw-obj-$(CONFIG_CUDA) += cuda.o diff --git a/default-configs/ppc-softmmu.mak b/default-configs/ppc-softmmu.mak index 4563742..4b3ebec 100644 --- a/default-configs/ppc-softmmu.mak +++ b/default-configs/ppc-softmmu.mak @@ -7,12 +7,14 @@ CONFIG_ESCC=y CONFIG_M48T59=y CONFIG_VGA_PCI=y CONFIG_SERIAL=y +CONFIG_PARALLEL=y CONFIG_I8254=y CONFIG_PCKBD=y CONFIG_FDC=y CONFIG_DMA=y CONFIG_OPENPIC=y CONFIG_PREP_PCI=y +CONFIG_PC87312=y CONFIG_MACIO=y CONFIG_CUDA=y CONFIG_ADB=y diff --git a/hw/pc87312.c b/hw/pc87312.c new file mode 100644 index 0000000..71295ec --- /dev/null +++ b/hw/pc87312.c @@ -0,0 +1,470 @@ +/* + * QEMU National Semiconductor PC87312 (Super I/O) + * + * Copyright (c) 2010 Herve Poussineau + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "isa.h" +#include "fdc.h" +#include "ide.h" + +//#define DEBUG_PC87312 + +#ifdef DEBUG_PC87312 +#define DPRINTF(fmt, ...) \ +do { fprintf(stderr, "pc87312: " fmt , ## __VA_ARGS__); } while (0) +#else +#define DPRINTF(fmt, ...) \ +do {} while (0) +#endif + +#define BADF(fmt, ...) \ +do { fprintf(stderr, "pc87312 ERROR: " fmt , ## __VA_ARGS__); } while (0) + +#define REG_FER 0 +#define REG_FAR 1 +#define REG_PTR 2 + +#define FER regs[REG_FER] +#define FAR regs[REG_FAR] +#define PTR regs[REG_PTR] + +#define FER_PARALLEL_EN 0x01 +#define FER_UART1_EN 0x02 +#define FER_UART2_EN 0x04 +#define FER_FDC_EN 0x08 +#define FER_FDC_4 0x10 +#define FER_FDC_ADDR 0x20 +#define FER_IDE_EN 0x40 +#define FER_IDE_ADDR 0x80 + +#define FAR_PARALLEL_ADDR 0x03 +#define FAR_UART1_ADDR 0x0C +#define FAR_UART2_ADDR 0x30 +#define FAR_UART_3_4 0xC0 + +#define PTR_POWER_DOWN 0x01 +#define PTR_CLOCK_DOWN 0x02 +#define PTR_PWDN 0x04 +#define PTR_IRQ_5_7 0x08 +#define PTR_UART1_TEST 0x10 +#define PTR_UART2_TEST 0x20 +#define PTR_LOCK_CONF 0x40 +#define PTR_EPP_MODE 0x80 + +typedef struct PC87312State { + uint8_t config; /* initial configuration */ + + struct { + DeviceState *dev; + CharDriverState *chr; + } parallel; + + struct { + DeviceState *dev; + CharDriverState *chr; + } uart[2]; + + struct { + DeviceState *dev; + BlockDriverState *drive[2]; + uint32_t base; + } fdc; + + struct { + DeviceState *dev; + uint32_t base; + } ide; + + uint8_t read_id_step; + uint8_t selected_index; + + uint8_t regs[3]; +} PC87312State; + + +/* Parallel port */ + +static inline bool is_parallel_enabled(PC87312State *s) +{ + return s->FER & FER_PARALLEL_EN; +} + +static const uint32_t parallel_base[] = { 0x378, 0x3bc, 0x278, 0x00 }; + +static inline uint32_t get_parallel_iobase(PC87312State *s) +{ + return parallel_base[s->FAR & FAR_PARALLEL_ADDR]; +} + +static const uint32_t parallel_irq[] = { 5, 7, 5, 0 }; + +static inline uint32_t get_parallel_irq(PC87312State *s) +{ + int idx; + idx = (s->FAR & FAR_PARALLEL_ADDR); + if (idx == 0) { + return (s->PTR & PTR_IRQ_5_7) ? 7 : 5; + } else { + return parallel_irq[idx]; + } +} + +static inline bool is_parallel_epp(PC87312State *s) +{ + return (s->PTR & PTR_EPP_MODE); +} + +static void update_parallel(PC87312State *s) +{ + ISADevice *isa; + uint32_t base, isairq; + bool enabled; + + if (s->parallel.dev != NULL) { + isa = DO_UPCAST(ISADevice, qdev, s->parallel.dev); + base = get_parallel_iobase(s); + isairq = get_parallel_irq(s); + enabled = is_parallel_enabled(s); + if (qdev_prop_get_bool(&isa->qdev, "enabled") != enabled || + qdev_prop_get_uint32(&isa->qdev, "iobase") != base || + qdev_prop_get_uint32(&isa->qdev, "irq") != isairq) { + isa_set_state(isa, false); + qdev_prop_set_uint32(&isa->qdev, "iobase", base); + qdev_prop_set_uint32(&isa->qdev, "irq", isairq); + if (enabled) { + isa_set_state(isa, true); + } + } + } +} + + +/* UARTs */ + +static const uint32_t uart_base[2][4] = { + { 0x3e8, 0x338, 0x2e8, 0x220 }, + { 0x2e8, 0x238, 0x2e0, 0x228 } +}; + +static inline uint32_t get_uart_iobase(PC87312State *s, int i) +{ + int idx; + idx = (s->FAR >> (2 * i + 2)) & 0x3; + if (idx == 0) { + return 0x3f8; + } else if (idx == 1) { + return 0x2f8; + } else { + return uart_base[idx & 1][(s->FAR & FAR_UART_3_4) >> 6]; + } +} + +static inline uint32_t get_uart_irq(PC87312State *s, int i) +{ + int idx; + idx = (s->FAR >> (2 * i + 2)) & 0x3; + return (idx & 1) ? 3 : 4; +} + +static inline bool is_uart_enabled(PC87312State *s, int i) +{ + return s->FER & (FER_UART1_EN << i); +} + +static void update_uarts(PC87312State *s) +{ + ISADevice *isa; + uint32_t base, isairq; + bool enabled; + int i; + + for (i = 0; i < 2; i++) { + if (s->uart[i].dev != NULL) { + isa = DO_UPCAST(ISADevice, qdev, s->parallel.dev); + base = get_uart_iobase(s, i); + isairq = get_uart_irq(s, i); + enabled = is_uart_enabled(s, i); + if (qdev_prop_get_bool(&isa->qdev, "enabled") != enabled || + qdev_prop_get_uint32(&isa->qdev, "iobase") != base || + qdev_prop_get_uint32(&isa->qdev, "irq") != isairq) { + isa_set_state(isa, false); + qdev_prop_set_uint32(&isa->qdev, "iobase", base); + qdev_prop_set_uint32(&isa->qdev, "irq", isairq); + if (enabled) { + isa_set_state(isa, true); + } + } + } + } +} + + +/* Floppy controller */ + +static inline bool is_fdc_enabled(PC87312State *s) +{ + return (s->FER & FER_FDC_EN); +} + +static inline uint32_t get_fdc_iobase(PC87312State *s) +{ + return (s->FER & FER_FDC_ADDR) ? 0x370 : 0x3f0; +} + +static void update_fdc(PC87312State *s) +{ + ISADevice *isa = DO_UPCAST(ISADevice, qdev, s->fdc.dev); + uint32_t base; + bool enabled; + + base = get_fdc_iobase(s); + enabled = is_fdc_enabled(s); + if (qdev_prop_get_bool(&isa->qdev, "enabled") != enabled || + qdev_prop_get_uint32(&isa->qdev, "iobase") != base) { + isa_set_state(isa, false); + qdev_prop_set_uint32(&isa->qdev, "iobase", base); + if (enabled) { + isa_set_state(isa, true); + } + } +} + + +/* IDE controller */ + +static inline bool is_ide_enabled(PC87312State *s) +{ + return (s->FER & FER_IDE_EN); +} + +static inline uint32_t get_ide_iobase(PC87312State *s) +{ + return (s->FER & FER_IDE_ADDR) ? 0x170 : 0x1f0; +} + +static void update_ide(PC87312State *s) +{ + ISADevice *isa = DO_UPCAST(ISADevice, qdev, s->ide.dev); + uint32_t base; + bool enabled; + + base = get_ide_iobase(s); + enabled = is_ide_enabled(s); + if (qdev_prop_get_bool(&isa->qdev, "enabled") != enabled || + qdev_prop_get_uint32(&isa->qdev, "iobase") != base) { + isa_set_state(isa, false); + qdev_prop_set_uint32(&isa->qdev, "iobase", base); + qdev_prop_set_uint32(&isa->qdev, "iobase2", base + 0x206); + if (enabled) { + isa_set_state(isa, true); + } + } +} + + +static void update_mappings(PC87312State *s) +{ + update_parallel(s); + update_uarts(s); + update_fdc(s); + update_ide(s); +} + +static void pc87312_soft_reset(PC87312State *s) +{ + static const uint8_t fer_init[] = { + 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4b, 0x4b, + 0x4b, 0x4b, 0x4b, 0x4b, 0x0f, 0x0f, 0x0f, 0x0f, + 0x49, 0x49, 0x49, 0x49, 0x07, 0x07, 0x07, 0x07, + 0x47, 0x47, 0x47, 0x47, 0x47, 0x47, 0x08, 0x00, + }; + static const uint8_t far_init[] = { + 0x10, 0x11, 0x11, 0x39, 0x24, 0x38, 0x00, 0x01, + 0x01, 0x09, 0x08, 0x08, 0x10, 0x11, 0x39, 0x24, + 0x00, 0x01, 0x01, 0x00, 0x10, 0x11, 0x39, 0x24, + 0x10, 0x11, 0x11, 0x39, 0x24, 0x38, 0x10, 0x10, + }; + static const uint8_t ptr_init[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, + }; + + s->read_id_step = 0; + s->selected_index = REG_FER; + + s->FER = fer_init[s->config & 0x1f]; + s->FAR = far_init[s->config & 0x1f]; + s->PTR = ptr_init[s->config & 0x1f]; +} + +static void pc87312_hard_reset(PC87312State *s) +{ + pc87312_soft_reset(s); +} + +static void pc87312_ioport_write(void *opaque, uint32_t addr, uint32_t val) +{ + PC87312State *s = opaque; + + DPRINTF("%s: write %x at %x\n", __func__, val, addr); + + if ((addr & 1) == 0) { + /* Index register */ + s->read_id_step = 2; + s->selected_index = val; + } else { + /* Data register */ + if (s->selected_index < 3) { + s->regs[s->selected_index] = val; + update_mappings(s); + } + } +} + +static uint32_t pc87312_ioport_read(void *opaque, uint32_t addr) +{ + PC87312State *s = opaque; + uint32_t val; + + if ((addr & 1) == 0) { + /* Index register */ + if (s->read_id_step++ == 0) { + val = 0x88; + } else if (s->read_id_step++ == 1) { + val = 0; + } else { + val = s->selected_index; + } + } else { + /* Data register */ + if (s->selected_index < 3) { + val = s->regs[s->selected_index]; + } else { + /* Invalid selected index */ + val = 0; + } + } + + DPRINTF("%s: read %x at %x\n", __func__, val, addr); + return val; +} + +static void pc87312_init_core(PC87312State *s) +{ + ISADevice *isa; + int i; + + pc87312_hard_reset(s); + + if (s->parallel.chr != NULL) { + isa = isa_create("isa-parallel"); + qdev_prop_set_uint32(&isa->qdev, "index", 0); + qdev_prop_set_uint32(&isa->qdev, "iobase", get_parallel_iobase(s)); + qdev_prop_set_uint32(&isa->qdev, "irq", get_parallel_irq(s)); + qdev_prop_set_chr(&isa->qdev, "chardev", s->parallel.chr); + qdev_init_nofail(&isa->qdev); + s->parallel.dev = &isa->qdev; + } + + for (i = 0; i < 2; i++) { + if (s->uart[i].chr != NULL) { + isa = isa_create("isa-serial"); + qdev_prop_set_uint32(&isa->qdev, "index", i); + qdev_prop_set_uint32(&isa->qdev, "iobase", get_uart_iobase(s, i)); + qdev_prop_set_uint32(&isa->qdev, "irq", get_uart_irq(s, i)); + qdev_prop_set_chr(&isa->qdev, "chardev", s->uart[i].chr); + qdev_init_nofail(&isa->qdev); + s->uart[i].dev = &isa->qdev; + } + } + + isa = isa_create("isa-fdc"); + qdev_prop_set_uint32(&isa->qdev, "iobase", get_fdc_iobase(s)); + qdev_prop_set_uint32(&isa->qdev, "irq", 6); + if (s->fdc.drive[0] != NULL) { + qdev_prop_set_drive_nofail(&isa->qdev, "driveA", s->fdc.drive[0]); + } + if (s->fdc.drive[1] != NULL) { + qdev_prop_set_drive_nofail(&isa->qdev, "driveB", s->fdc.drive[1]); + } + qdev_init_nofail(&isa->qdev); + s->fdc.dev = &isa->qdev; + + isa = isa_create("isa-ide"); + qdev_prop_set_uint32(&isa->qdev, "iobase", get_ide_iobase(s)); + qdev_prop_set_uint32(&isa->qdev, "iobase2", get_ide_iobase(s) + 0x206); + qdev_prop_set_uint32(&isa->qdev, "irq", 14); + qdev_init_nofail(&isa->qdev); + s->ide.dev = &isa->qdev; + + update_mappings(s); +} + +typedef struct ISAPC87312State { + ISADevice dev; + uint32_t iobase; + PC87312State state; +} ISAPC87312State; + +static void isa_pc87312_reset(DeviceState *d) +{ + PC87312State *s = &container_of(d, ISAPC87312State, dev.qdev)->state; + pc87312_soft_reset(s); +} + +static int isa_pc87312_init(ISADevice *dev) +{ + ISAPC87312State *isa = DO_UPCAST(ISAPC87312State, dev, dev); + PC87312State *s = &isa->state; + + pc87312_init_core(s); + + register_ioport_write(isa->iobase, 2, 1, pc87312_ioport_write, s); + register_ioport_read(isa->iobase, 2, 1, pc87312_ioport_read, s); + return 0; +} + +static ISADeviceInfo pc87312_isa_info = { + .qdev.name = "isa-pc87312", + .qdev.size = sizeof(ISAPC87312State), + .qdev.reset = isa_pc87312_reset, + .init = isa_pc87312_init, + .qdev.props = (Property[]) { + DEFINE_PROP_HEX32("iobase", ISAPC87312State, iobase, 0x398), + DEFINE_PROP_UINT8("config", ISAPC87312State, state.config, 1), + DEFINE_PROP_CHR("parallel", ISAPC87312State, state.parallel.chr), + DEFINE_PROP_CHR("uart1", ISAPC87312State, state.uart[0].chr), + DEFINE_PROP_CHR("uart2", ISAPC87312State, state.uart[1].chr), + DEFINE_PROP_DRIVE("floppyA", ISAPC87312State, state.fdc.drive[0]), + DEFINE_PROP_DRIVE("floppyB", ISAPC87312State, state.fdc.drive[1]), + DEFINE_PROP_END_OF_LIST() + }, +}; + +static void pc87312_register_devices(void) +{ + isa_qdev_register(&pc87312_isa_info); +} + +device_init(pc87312_register_devices)