arm - use the new CPU alias option to simplify the list of CPUs.

Message ID 021bf007-7bef-064b-1529-c139e67d0de2@arm.com
State New
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  • arm - use the new CPU alias option to simplify the list of CPUs.
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Commit Message

Richard Earnshaw (lists) Nov. 9, 2018, 11 a.m.
This patch simplifies the table of CPUs supported in GCC by making
use of the new alias feature.  Most of the changes are fairly
straight-forward:
- arm7tdmi and arm7tdmi-s are the same thing.
- arm710t, arm720t and arm740t differ only in features external to the core
- arm920 and arm920t are the same thing; arm922t and arm940t differ from
  arm920t only in features external to the core; ep9312 is an
arm920t-derived
  core that we continue to recognize for legacy reasons.
- arm10tdmi and arm1020t differ only in features external to the core.
- arm9e, arm946te-s, arm966e-s and arm968e-s differ only in features
external
  to the core.
- arm10e, arm1020e and arm1022e differ only in features external to the
core.

The arm10e/arm1020e/arm1022e change is the only one which changes
behaviour of the compiler slightly.  Previously, and for no reason
that I can remember, the scheduler for arm1020e/arm1022e was not used
for arm10e: this was probably an oversight.  The unification means
that the same scheduler is now used for all three cores.

	* config/arm/arm-cpus.in (arm7tdmi): Add an alias for arm7tdmi-s.
	(arm7tdmi-s): Delete CPU.
	(arm710t): Add aliases for arm720t and arm740t.
	(arm720t, arm740t): Delete CPUs.
	(arm920t): Add aliases for arm920, arm922t and arm940t.
	(arm920, arm922t, arm940t): Delete CPUs.
	(arm10tdmi): Add alias for arm1020t.
	(arm1020t): Delete CPU.
	(arm9e): Add aliases for arm946e-s, arm966e-s and arm968e-s.
	(arm946e-s, arm966e-s, arm968e-s): Delete CPUs.
	(arm10e): Add aliases for arm1020e and arm1022e.
	(arm1020e, arm1022e): Delete CPU.
	* config/arm/arm.md (generic_sched): Remove entries that are now
	handled by aliases.
	(generic_vfp): Likewise.
	* config/arm/arm1020e.md: Simplify tuning selection based on alias
	changes.
	* config/arm/arm-tune.md: Regenerated.
	* config/arm/arm-tables.opt: Regenerated.

Applied to trunk.

Patch

diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
index 1def1cace68..7189fc9210d 100644
--- a/gcc/config/arm/arm-cpus.in
+++ b/gcc/config/arm/arm-cpus.in
@@ -683,36 +683,19 @@  end cpu fa626
 
 # V4T Architecture Processors
 begin cpu arm7tdmi
+ alias arm7tdmi-s
  tune flags CO_PROC
  architecture armv4t
  costs fastmul
 end cpu arm7tdmi
 
-begin cpu arm7tdmi-s
- cname arm7tdmis
- tune flags CO_PROC
- architecture armv4t
- costs fastmul
-end cpu arm7tdmi-s
-
 begin cpu arm710t
+ alias arm720t arm740t
  tune flags WBUF
  architecture armv4t
  costs fastmul
 end cpu arm710t
 
-begin cpu arm720t
- tune flags WBUF
- architecture armv4t
- costs fastmul
-end cpu arm720t
-
-begin cpu arm740t
- tune flags WBUF
- architecture armv4t
- costs fastmul
-end cpu arm740t
-
 begin cpu arm9
  tune flags LDSCHED
  architecture armv4t
@@ -725,105 +708,41 @@  begin cpu arm9tdmi
  costs fastmul
 end cpu arm9tdmi
 
-begin cpu arm920
- tune flags LDSCHED
- architecture armv4t
- costs fastmul
-end cpu arm920
-
 begin cpu arm920t
+ alias arm920 arm922t arm940t ep9312
  tune flags LDSCHED
  architecture armv4t
  costs fastmul
 end cpu arm920t
 
-begin cpu arm922t
- tune flags LDSCHED
- architecture armv4t
- costs fastmul
-end cpu arm922t
-
-begin cpu arm940t
- tune flags LDSCHED
- architecture armv4t
- costs fastmul
-end cpu arm940t
-
-begin cpu ep9312
- tune flags LDSCHED
- architecture armv4t
- costs fastmul
-end cpu ep9312
-
 
 # V5T Architecture Processors
 # These used VFPv1 which isn't supported by GCC
 begin cpu arm10tdmi
+ alias arm1020t
  tune flags LDSCHED
  architecture armv5t
  costs fastmul
 end cpu arm10tdmi
 
-begin cpu arm1020t
- tune flags LDSCHED
- architecture armv5t
- costs fastmul
-end cpu arm1020t
-
 
 # V5TE Architecture Processors
 begin cpu arm9e
+ alias arm946e-s arm966e-s arm968e-s
  tune flags LDSCHED
  architecture armv5te+fp
  option nofp remove ALL_FP
  costs 9e
 end cpu arm9e
 
-begin cpu arm946e-s
- cname arm946es
- tune flags LDSCHED
- architecture armv5te+fp
- option nofp remove ALL_FP
- costs 9e
-end cpu arm946e-s
-
-begin cpu arm966e-s
- cname arm966es
- tune flags LDSCHED
- architecture armv5te+fp
- option nofp remove ALL_FP
- costs 9e
-end cpu arm966e-s
-
-begin cpu arm968e-s
- cname arm968es
- tune flags LDSCHED
- architecture armv5te+fp
- option nofp remove ALL_FP
- costs 9e
-end cpu arm968e-s
-
 begin cpu arm10e
+ alias arm1020e arm1022e
  tune flags LDSCHED
  architecture armv5te+fp
  option nofp remove ALL_FP
  costs fastmul
 end cpu arm10e
 
-begin cpu arm1020e
- tune flags LDSCHED
- architecture armv5te+fp
- option nofp remove ALL_FP
- costs fastmul
-end cpu arm1020e
-
-begin cpu arm1022e
- tune flags LDSCHED
- architecture armv5te+fp
- option nofp remove ALL_FP
- costs fastmul
-end cpu arm1022e
-
 begin cpu xscale
  tune flags LDSCHED XSCALE
  architecture armv5te
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index cd496366cec..b314ec30ede 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -42,66 +42,27 @@  Enum(processor_type) String(fa626) Value( TARGET_CPU_fa626)
 EnumValue
 Enum(processor_type) String(arm7tdmi) Value( TARGET_CPU_arm7tdmi)
 
-EnumValue
-Enum(processor_type) String(arm7tdmi-s) Value( TARGET_CPU_arm7tdmis)
-
 EnumValue
 Enum(processor_type) String(arm710t) Value( TARGET_CPU_arm710t)
 
-EnumValue
-Enum(processor_type) String(arm720t) Value( TARGET_CPU_arm720t)
-
-EnumValue
-Enum(processor_type) String(arm740t) Value( TARGET_CPU_arm740t)
-
 EnumValue
 Enum(processor_type) String(arm9) Value( TARGET_CPU_arm9)
 
 EnumValue
 Enum(processor_type) String(arm9tdmi) Value( TARGET_CPU_arm9tdmi)
 
-EnumValue
-Enum(processor_type) String(arm920) Value( TARGET_CPU_arm920)
-
 EnumValue
 Enum(processor_type) String(arm920t) Value( TARGET_CPU_arm920t)
 
-EnumValue
-Enum(processor_type) String(arm922t) Value( TARGET_CPU_arm922t)
-
-EnumValue
-Enum(processor_type) String(arm940t) Value( TARGET_CPU_arm940t)
-
-EnumValue
-Enum(processor_type) String(ep9312) Value( TARGET_CPU_ep9312)
-
 EnumValue
 Enum(processor_type) String(arm10tdmi) Value( TARGET_CPU_arm10tdmi)
 
-EnumValue
-Enum(processor_type) String(arm1020t) Value( TARGET_CPU_arm1020t)
-
 EnumValue
 Enum(processor_type) String(arm9e) Value( TARGET_CPU_arm9e)
 
-EnumValue
-Enum(processor_type) String(arm946e-s) Value( TARGET_CPU_arm946es)
-
-EnumValue
-Enum(processor_type) String(arm966e-s) Value( TARGET_CPU_arm966es)
-
-EnumValue
-Enum(processor_type) String(arm968e-s) Value( TARGET_CPU_arm968es)
-
 EnumValue
 Enum(processor_type) String(arm10e) Value( TARGET_CPU_arm10e)
 
-EnumValue
-Enum(processor_type) String(arm1020e) Value( TARGET_CPU_arm1020e)
-
-EnumValue
-Enum(processor_type) String(arm1022e) Value( TARGET_CPU_arm1022e)
-
 EnumValue
 Enum(processor_type) String(xscale) Value( TARGET_CPU_xscale)
 
diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md
index bbe09cf466c..b9bcfa71e7b 100644
--- a/gcc/config/arm/arm-tune.md
+++ b/gcc/config/arm/arm-tune.md
@@ -23,32 +23,28 @@ 
 (define_attr "tune"
 	"arm8,arm810,strongarm,
 	fa526,fa626,arm7tdmi,
-	arm7tdmis,arm710t,arm720t,
-	arm740t,arm9,arm9tdmi,
-	arm920,arm920t,arm922t,
-	arm940t,ep9312,arm10tdmi,
-	arm1020t,arm9e,arm946es,
-	arm966es,arm968es,arm10e,
-	arm1020e,arm1022e,xscale,
-	iwmmxt,iwmmxt2,fa606te,
-	fa626te,fmp626,fa726te,
-	arm926ejs,arm1026ejs,arm1136js,
-	arm1136jfs,arm1176jzs,arm1176jzfs,
-	mpcorenovfp,mpcore,arm1156t2s,
-	arm1156t2fs,cortexm1,cortexm0,
-	cortexm0plus,cortexm1smallmultiply,cortexm0smallmultiply,
-	cortexm0plussmallmultiply,genericv7a,cortexa5,
-	cortexa7,cortexa8,cortexa9,
-	cortexa12,cortexa15,cortexa17,
-	cortexr4,cortexr4f,cortexr5,
-	cortexr7,cortexr8,cortexm7,
-	cortexm4,cortexm3,marvell_pj4,
-	cortexa15cortexa7,cortexa17cortexa7,cortexa32,
-	cortexa35,cortexa53,cortexa57,
-	cortexa72,cortexa73,exynosm1,
-	xgene1,cortexa57cortexa53,cortexa72cortexa53,
-	cortexa73cortexa35,cortexa73cortexa53,cortexa55,
-	cortexa75,cortexa76,ares,
-	cortexa75cortexa55,cortexa76cortexa55,cortexm23,
-	cortexm33,cortexr52"
+	arm710t,arm9,arm9tdmi,
+	arm920t,arm10tdmi,arm9e,
+	arm10e,xscale,iwmmxt,
+	iwmmxt2,fa606te,fa626te,
+	fmp626,fa726te,arm926ejs,
+	arm1026ejs,arm1136js,arm1136jfs,
+	arm1176jzs,arm1176jzfs,mpcorenovfp,
+	mpcore,arm1156t2s,arm1156t2fs,
+	cortexm1,cortexm0,cortexm0plus,
+	cortexm1smallmultiply,cortexm0smallmultiply,cortexm0plussmallmultiply,
+	genericv7a,cortexa5,cortexa7,
+	cortexa8,cortexa9,cortexa12,
+	cortexa15,cortexa17,cortexr4,
+	cortexr4f,cortexr5,cortexr7,
+	cortexr8,cortexm7,cortexm4,
+	cortexm3,marvell_pj4,cortexa15cortexa7,
+	cortexa17cortexa7,cortexa32,cortexa35,
+	cortexa53,cortexa57,cortexa72,
+	cortexa73,exynosm1,xgene1,
+	cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,
+	cortexa73cortexa53,cortexa55,cortexa75,
+	cortexa76,ares,cortexa75cortexa55,
+	cortexa76cortexa55,cortexm23,cortexm33,
+	cortexr52"
 	(const (symbol_ref "((enum attr_tune) arm_tune)")))
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index a773518cefa..c8dc9474b1b 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -384,7 +384,7 @@  (define_attr "tune_cortexr4" "yes,no"
 (define_attr "generic_sched" "yes,no"
   (const (if_then_else
           (ior (eq_attr "tune" "fa526,fa626,fa606te,fa626te,fmp626,fa726te,\
-                                arm926ejs,arm1020e,arm1026ejs,arm1136js,\
+                                arm926ejs,arm10e,arm1026ejs,arm1136js,\
                                 arm1136jfs,cortexa5,cortexa7,cortexa8,\
                                 cortexa9,cortexa12,cortexa15,cortexa17,\
                                 cortexa53,cortexa57,cortexm4,cortexm7,\
@@ -396,7 +396,7 @@  (define_attr "generic_sched" "yes,no"
 (define_attr "generic_vfp" "yes,no"
   (const (if_then_else
 	  (and (eq_attr "fpu" "vfp")
-	       (eq_attr "tune" "!arm1020e,arm1022e,cortexa5,cortexa7,\
+	       (eq_attr "tune" "!arm10e,cortexa5,cortexa7,\
                                 cortexa8,cortexa9,cortexa53,cortexm4,\
                                 cortexm7,marvell_pj4,xgene1")
 	       (eq_attr "tune_cortexr4" "no"))
diff --git a/gcc/config/arm/arm1020e.md b/gcc/config/arm/arm1020e.md
index 3a00104420c..9b800f87e8c 100644
--- a/gcc/config/arm/arm1020e.md
+++ b/gcc/config/arm/arm1020e.md
@@ -65,7 +65,7 @@  (define_cpu_unit "1020l_e,1020l_m,1020l_w" "arm1020e")
 
 ;; ALU operations with no shifted operand
 (define_insn_reservation "1020alu_op" 1 
- (and (eq_attr "tune" "arm1020e,arm1022e")
+ (and (eq_attr "tune" "arm10e")
       (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
                        alu_sreg,alus_sreg,logic_reg,logics_reg,\
                        adc_imm,adcs_imm,adc_reg,adcs_reg,\
@@ -77,7 +77,7 @@  (define_insn_reservation "1020alu_op" 1
 
 ;; ALU operations with a shift-by-constant operand
 (define_insn_reservation "1020alu_shift_op" 1 
- (and (eq_attr "tune" "arm1020e,arm1022e")
+ (and (eq_attr "tune" "arm10e")
       (eq_attr "type" "alu_shift_imm,alus_shift_imm,\
                        logic_shift_imm,logics_shift_imm,\
                        extend,mov_shift,mvn_shift"))
@@ -88,7 +88,7 @@  (define_insn_reservation "1020alu_shift_op" 1
 ;; the shift value in a second cycle. Pretend we take two cycles in
 ;; the execute stage.
 (define_insn_reservation "1020alu_shift_reg_op" 2 
- (and (eq_attr "tune" "arm1020e,arm1022e")
+ (and (eq_attr "tune" "arm10e")
       (eq_attr "type" "alu_shift_reg,alus_shift_reg,\
                        logic_shift_reg,logics_shift_reg,\
                        mov_shift_reg,mvn_shift_reg"))
@@ -105,7 +105,7 @@  (define_insn_reservation "1020alu_shift_reg_op" 2
 ;; The result of the "smul" and "smulw" instructions is not available
 ;; until after the memory stage.
 (define_insn_reservation "1020mult1" 2
- (and (eq_attr "tune" "arm1020e,arm1022e")
+ (and (eq_attr "tune" "arm10e")
       (eq_attr "type" "smulxy,smulwy"))
  "1020a_e,1020a_m,1020a_w")
 
@@ -113,7 +113,7 @@  (define_insn_reservation "1020mult1" 2
 ;; the execute stage; the result is available immediately following
 ;; the execute stage.
 (define_insn_reservation "1020mult2" 2
- (and (eq_attr "tune" "arm1020e,arm1022e")
+ (and (eq_attr "tune" "arm10e")
       (eq_attr "type" "smlaxy,smlalxy,smlawx"))
  "1020a_e*2,1020a_m,1020a_w")
 
@@ -121,7 +121,7 @@  (define_insn_reservation "1020mult2" 2
 ;; through the execute stage; the result is not available until after
 ;; the memory stage.
 (define_insn_reservation "1020mult3" 3
- (and (eq_attr "tune" "arm1020e,arm1022e")
+ (and (eq_attr "tune" "arm10e")
       (eq_attr "type" "smlalxy,mul,mla"))
  "1020a_e*2,1020a_m,1020a_w")
 
@@ -129,7 +129,7 @@  (define_insn_reservation "1020mult3" 3
 ;; four iterations in order to set the flags.  The value result is
 ;; available after three iterations.
 (define_insn_reservation "1020mult4" 3
- (and (eq_attr "tune" "arm1020e,arm1022e")
+ (and (eq_attr "tune" "arm10e")
       (eq_attr "type" "muls,mlas"))
  "1020a_e*4,1020a_m,1020a_w")
 
@@ -144,7 +144,7 @@  (define_insn_reservation "1020mult4" 3
 ;; three iterations through the execute cycle, and make their results
 ;; available after the memory cycle.
 (define_insn_reservation "1020mult5" 4
- (and (eq_attr "tune" "arm1020e,arm1022e")
+ (and (eq_attr "tune" "arm10e")
       (eq_attr "type" "umull,umlal,smull,smlal"))
  "1020a_e*3,1020a_m,1020a_w")
 
@@ -152,7 +152,7 @@  (define_insn_reservation "1020mult5" 4
 ;; the execute stage for five iterations in order to set the flags.
 ;; The value result is available after four iterations.
 (define_insn_reservation "1020mult6" 4
- (and (eq_attr "tune" "arm1020e,arm1022e")
+ (and (eq_attr "tune" "arm10e")
       (eq_attr "type" "umulls,umlals,smulls,smlals"))
  "1020a_e*5,1020a_m,1020a_w")
 
@@ -175,12 +175,12 @@  (define_insn_reservation "1020mult6" 4
 ;; For 4byte loads there is a bypass from the load stage
 
 (define_insn_reservation "1020load1_op" 2
- (and (eq_attr "tune" "arm1020e,arm1022e")
+ (and (eq_attr "tune" "arm10e")
       (eq_attr "type" "load_byte,load_4"))
  "1020a_e+1020l_e,1020l_m,1020l_w")
 
 (define_insn_reservation "1020store1_op" 0
- (and (eq_attr "tune" "arm1020e,arm1022e")
+ (and (eq_attr "tune" "arm10e")
       (eq_attr "type" "store_4"))
  "1020a_e+1020l_e,1020l_m,1020l_w")
 
@@ -210,22 +210,22 @@  (define_bypass 1 "1020load1_op" "1020store1_op" "arm_no_early_store_addr_dep")
 ;; PC, there are additional stalls; that is not modeled.
 
 (define_insn_reservation "1020load2_op" 2
- (and (eq_attr "tune" "arm1020e,arm1022e")
+ (and (eq_attr "tune" "arm10e")
       (eq_attr "type" "load_8"))
  "1020a_e+1020l_e,1020l_m,1020l_w")
 
 (define_insn_reservation "1020store2_op" 0
- (and (eq_attr "tune" "arm1020e,arm1022e")
+ (and (eq_attr "tune" "arm10e")
       (eq_attr "type" "store_8"))
  "1020a_e+1020l_e,1020l_m,1020l_w")
 
 (define_insn_reservation "1020load34_op" 3
- (and (eq_attr "tune" "arm1020e,arm1022e")
+ (and (eq_attr "tune" "arm10e")
       (eq_attr "type" "load_12,load_16"))
  "1020a_e+1020l_e,1020l_e+1020l_m,1020l_m,1020l_w")
 
 (define_insn_reservation "1020store34_op" 0
- (and (eq_attr "tune" "arm1020e,arm1022e")
+ (and (eq_attr "tune" "arm10e")
       (eq_attr "type" "store_12,store_16"))
  "1020a_e+1020l_e,1020l_e+1020l_m,1020l_m,1020l_w")
 
@@ -242,7 +242,7 @@  (define_insn_reservation "1020store34_op" 0
 ;; therefore the minimum value.
 
 (define_insn_reservation "1020branch_op" 0
- (and (eq_attr "tune" "arm1020e,arm1022e")
+ (and (eq_attr "tune" "arm10e")
       (eq_attr "type" "branch"))
  "1020a_e")
 
@@ -251,7 +251,7 @@  (define_insn_reservation "1020branch_op" 0
 ;; than that.
 
 (define_insn_reservation "1020call_op" 32
- (and (eq_attr "tune" "arm1020e,arm1022e")
+ (and (eq_attr "tune" "arm10e")
       (eq_attr "type" "call"))
  "1020a_e*4")
 
@@ -272,7 +272,7 @@  (define_cpu_unit "v10_ls1,v10_ls2,v10_ls3" "arm1020e")
 (exclusion_set "v10_fmac,v10_ds" "v10_fmstat")
 
 (define_attr "vfp10" "yes,no" 
-  (const (if_then_else (and (eq_attr "tune" "arm1020e,arm1022e")
+  (const (if_then_else (and (eq_attr "tune" "arm10e")
 			    (eq_attr "fpu" "vfp"))
 		       (const_string "yes") (const_string "no"))))