From patchwork Wed Jun 8 14:19:24 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramana Radhakrishnan X-Patchwork-Id: 99437 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 10673B6F87 for ; Thu, 9 Jun 2011 00:19:47 +1000 (EST) Received: (qmail 16751 invoked by alias); 8 Jun 2011 14:19:41 -0000 Received: (qmail 16732 invoked by uid 22791); 8 Jun 2011 14:19:40 -0000 X-SWARE-Spam-Status: No, hits=-2.5 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, TW_MV, TW_QE, TW_XF X-Spam-Check-By: sourceware.org Received: from mail-qw0-f47.google.com (HELO mail-qw0-f47.google.com) (209.85.216.47) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 08 Jun 2011 14:19:25 +0000 Received: by qwh5 with SMTP id 5so267826qwh.20 for ; Wed, 08 Jun 2011 07:19:24 -0700 (PDT) MIME-Version: 1.0 Received: by 10.224.187.17 with SMTP id cu17mr4046580qab.215.1307542764352; Wed, 08 Jun 2011 07:19:24 -0700 (PDT) Received: by 10.224.73.204 with HTTP; Wed, 8 Jun 2011 07:19:24 -0700 (PDT) Date: Wed, 8 Jun 2011 15:19:24 +0100 Message-ID: Subject: [Patch ARM] Unify movdi patterns and fix case for mvn in const_ok_for_op. From: Ramana Radhakrishnan To: gcc-patches Cc: Patch Tracking X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hi, This fixes a testsuite failure with 20041011-1.c where we are generating out of range adr instructions because a splitter goes awry because we didn't consider the mvn case in const_ok_for_op. So we ended up splitting this movdi reg:r1 0xffffffff to (insn 370 21 371 (set (reg:SI 2 r2) (const_int -2147483648 [0xffffffff80000000])) /home/ramrad01/sources/fsf/trunk/gcc/testsuite/gcc.c-torture/execute/20041011-1.c:56 624 {*arm_movsi_vfp} (nil)) (insn 371 370 372 (set (reg:SI 2 r2) (ashiftrt:SI (reg:SI 2 r2) (const_int 31 [0x1f]))) /home/ramrad01/sources/fsf/trunk/gcc/testsuite/gcc.c-torture/execute/20041011-1.c:56 119 {*arm_shiftsi3} (nil)) (insn 372 371 23 (set (reg:SI 3 r3 [+4 ]) (const_int 0 [0])) /home/ramrad01/sources/fsf/trunk/gcc/testsuite/gcc.c-torture/execute/20041011-1.c:56 624 {*arm_movsi_vfp} (nil)) After this patch we now split this to a mvn 0 followed by a mov 0 which is much better. I've also taken the opportunity to rejig the *movdi patterns to make them simpler - unified them with thumb2 movdi patterns and taken out the check for TARGET_VFP_SINGLE from the cortex-a8 version . Tested with cross on armv7-a for qemu in both ARM and Thumb2 state using arm-linux-gnueabi. I will commit this in 24 hours if there are no objections. cheers Ramana 2011-06-03 Ramana Radhakrishnan Richard Earnshaw * config/arm/arm.c (const_ok_for_op): Check to see if mvn can be used. * config/arm/vfp.md (*arm_movdi_vfp): Delete. (*thumb2_movdi_vfp): Delete. (*arm_movdi_vfp_cortexa8): Delete. (*movdi_vfp): Consolidate from *arm_movdi_vfp and *thumb2_movdi_vfp. (*movdi_vfp_cortexa8): Likewise. diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 57c5238..c2d69c8 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -2210,7 +2210,8 @@ const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code) if (arm_arch_thumb2 && (i & 0xffff0000) == 0) return 1; else - return 0; + /* Otherwise, try mvn. */ + return const_ok_for_arm (ARM_SIGN_EXTEND (~i)); case PLUS: case COMPARE: diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index d257cb8..42be2ff 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -133,127 +133,92 @@ ;; DImode moves -(define_insn "*arm_movdi_vfp" - [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, m,w,r,w,w, Uv") - (match_operand:DI 1 "di_operand" "rIK,mi,r,r,w,w,Uvi,w"))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP && arm_tune != cortexa8 +(define_insn "*movdi_vfp" + [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,r,r,r,r,m,w,r,w,w, Uv") + (match_operand:DI 1 "di_operand" "r,rDa,Db,Dc,mi,mi,r,r,w,w,Uvi,w"))] + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && arm_tune != cortexa8 && ( register_operand (operands[0], DImode) || register_operand (operands[1], DImode))" "* switch (which_alternative) { case 0: - return \"#\"; case 1: case 2: - return output_move_double (operands); case 3: - return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\"; + return \"#\"; case 4: - return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\"; case 5: + case 6: + return output_move_double (operands); + case 7: + return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\"; + case 8: + return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\"; + case 9: if (TARGET_VFP_SINGLE) return \"fcpys%?\\t%0, %1\\t%@ int\;fcpys%?\\t%p0, %p1\\t%@ int\"; else return \"fcpyd%?\\t%P0, %P1\\t%@ int\"; - case 6: case 7: + case 10: case 11: return output_move_vfp (operands); default: gcc_unreachable (); } " - [(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarithd,f_loadd,f_stored") - (set_attr "neon_type" "*,*,*,neon_mcr_2_mcrr,neon_mrrc,neon_vmov,*,*") - (set (attr "length") (cond [(eq_attr "alternative" "0,1,2") (const_int 8) - (eq_attr "alternative" "5") - (if_then_else - (eq (symbol_ref "TARGET_VFP_SINGLE") (const_int 1)) - (const_int 8) - (const_int 4))] - (const_int 4))) - (set_attr "pool_range" "*,1020,*,*,*,*,1020,*") - (set_attr "neg_pool_range" "*,1008,*,*,*,*,1008,*")] + [(set_attr "type" "*,*,*,*,load2,load2,store2,r_2_f,f_2_r,ffarithd,f_loadd,f_stored") + (set_attr "neon_type" "*,*,*,*,*,*,*,neon_mcr_2_mcrr,neon_mrrc,neon_vmov,*,*") + (set (attr "length") (cond [(eq_attr "alternative" "1,4,5,6") (const_int 8) + (eq_attr "alternative" "2") (const_int 12) + (eq_attr "alternative" "3") (const_int 16) + (eq_attr "alternative" "9") + (if_then_else + (eq (symbol_ref "TARGET_VFP_SINGLE") (const_int 1)) + (const_int 8) + (const_int 4))] + (const_int 4))) + (set_attr "pool_range" "*,*,*,*,1020,4096,*,*,*,*,1020,*") + (set_attr "neg_pool_range" "*,*,*,*,1008,0,*,*,*,*,1008,*") + (set_attr "arch" "t2,any,any,any,a,t2,any,any,any,any,any,any")] ) -(define_insn "*arm_movdi_vfp_cortexa8" - [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r,m,w,!r,w,w, Uv") - (match_operand:DI 1 "di_operand" "rIK,mi,r,r,w,w,Uvi,w"))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP && arm_tune == cortexa8 - && ( register_operand (operands[0], DImode) - || register_operand (operands[1], DImode))" +(define_insn "*movdi_vfp_cortexa8" + [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,r,r,r,r,m,w,!r,w,w, Uv") + (match_operand:DI 1 "di_operand" "r,rDa,Db,Dc,mi,mi,r,r,w,w,Uvi,w"))] + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && arm_tune == cortexa8 + && ( register_operand (operands[0], DImode) + || register_operand (operands[1], DImode))" "* switch (which_alternative) { case 0: - return \"#\"; case 1: case 2: - return output_move_double (operands); case 3: - return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\"; + return \"#\"; case 4: - return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\"; case 5: - if (TARGET_VFP_SINGLE) - return \"fcpys%?\\t%0, %1\\t%@ int\;fcpys%?\\t%p0, %p1\\t%@ int\"; - else - return \"fcpyd%?\\t%P0, %P1\\t%@ int\"; - case 6: case 7: - return output_move_vfp (operands); - default: - gcc_unreachable (); - } - " - [(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarithd,f_loadd,f_stored") - (set (attr "length") (cond [(eq_attr "alternative" "0,1,2") (const_int 8) - (eq_attr "alternative" "5") - (if_then_else - (eq (symbol_ref "TARGET_VFP_SINGLE") - (const_int 1)) - (const_int 8) - (const_int 4))] - (const_int 4))) - (set_attr "predicable" "yes") - (set_attr "pool_range" "*,1020,*,*,*,*,1020,*") - (set_attr "neg_pool_range" "*,1008,*,*,*,*,1008,*")] -) - -(define_insn "*thumb2_movdi_vfp" - [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r,m,w,r,w,w, Uv") - (match_operand:DI 1 "di_operand" "rIK,mi,r,r,w,w,Uvi,w"))] - "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP" - "* - switch (which_alternative) - { - case 0: case 1: case 2: - return (output_move_double (operands)); - case 3: + case 6: + return output_move_double (operands); + case 7: return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\"; - case 4: + case 8: return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\"; - case 5: - if (TARGET_VFP_SINGLE) - return \"fcpys%?\\t%0, %1\\t%@ int\;fcpys%?\\t%p0, %p1\\t%@ int\"; - else - return \"fcpyd%?\\t%P0, %P1\\t%@ int\"; - case 6: case 7: + case 9: + return \"fcpyd%?\\t%P0, %P1\\t%@ int\"; + case 10: case 11: return output_move_vfp (operands); default: - abort (); + gcc_unreachable (); } " - [(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarithd,f_loadd,f_stored") - (set (attr "length") (cond [(eq_attr "alternative" "0,1,2") (const_int 8) - (eq_attr "alternative" "5") - (if_then_else - (eq (symbol_ref "TARGET_VFP_SINGLE") - (const_int 1)) - (const_int 8) - (const_int 4))] - (const_int 4))) - (set_attr "pool_range" "*,4096,*,*,*,*,1020,*") - (set_attr "neg_pool_range" "*, 0,*,*,*,*,1008,*")] -) + [(set_attr "type" "*,*,*,*,load2,load2,store2,r_2_f,f_2_r,ffarithd,f_loadd,f_stored") + (set_attr "length" "4,8,12,16,8,8,8,4,4,4,4,4") + (set_attr "predicable" "yes") + (set_attr "pool_range" "*,*,*,*,1020,4096,*,*,*,*,1020,*") + (set_attr "neg_pool_range" "*,*,*,*,1008,0,*,*,*,*,1008,*") + (set_attr "arch" "t2,any,any,any,a,t2,any,any,any,any,any,any")] + ) ;; HFmode moves (define_insn "*movhf_vfp_neon"