From patchwork Wed Nov 7 09:47:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kyrill Tkachov X-Patchwork-Id: 994163 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-489229-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=foss.arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="bE8aV13H"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42qhRQ6DPLz9s8T for ; Wed, 7 Nov 2018 20:47:46 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:content-type; q= dns; s=default; b=aDIcVsShg7H3aCRdbGQUlj4KIyQ43LOWTNp4a1wrQjWcW1 1DpHMvSgBxsc2qEO3gYcahlx4LZxh91UnB6L0jDlJyBPVHkGCMG1otxZr0vK/W33 t9GkuL+O1E81pv6qg2hrnQJw6Ly+b6yxNWujaw+0R243hhpHd1tJgqmOBUOoM= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:content-type; s= default; bh=yz470E05IoVuu124Da0wkLSXri8=; b=bE8aV13HTMDg7Aeihd+q dOeWaAiBVEA34no7DyhalhQY3Hz4LcpSUrEi0a+ArrOc/DiSb/eaV18mzyU3z0ta 7S/zj2AHkrLmG79fsfN6nzLzYi4b2IjhU/UAs27KiZAXAb4W8SuyKiaEvleiv0VF CMPFv2j/yhMiA/XnkIbjy2I= Received: (qmail 5381 invoked by alias); 7 Nov 2018 09:47:27 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 5271 invoked by uid 89); 7 Nov 2018 09:47:26 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-25.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_LAZY_DOMAIN_SECURITY, KAM_LOTSOFHASH autolearn=ham version=3.3.2 spammy= X-HELO: foss.arm.com Received: from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 07 Nov 2018 09:47:25 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7CE441596 for ; Wed, 7 Nov 2018 01:47:23 -0800 (PST) Received: from [10.2.207.77] (e100706-lin.cambridge.arm.com [10.2.207.77]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 282B33F718 for ; Wed, 7 Nov 2018 01:47:23 -0800 (PST) Message-ID: <5BE2B4A9.2000705@foss.arm.com> Date: Wed, 07 Nov 2018 09:47:21 +0000 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" Subject: [PATCH][arm] Add support for Arm Ares Hi all, This adds support for the Arm Ares CPU for in the arm port. It implements the Armv8.2-A architecture with the optional features of statistical profiling, dot product and FP16 on by default. Note: Ares is a codename to enable early adopters and in time we will add the final product name once it's announced. Bootstrapped and tested on arm-none-linux-gnueabihf. Will commit to trunk with the aarch64 patch once that is approved. Thanks, Kyrill 2018-11-07 Kyrylo Tkachov * config/arm/arm-cpus.in (ares): New entry. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm-tune.md: Likewise. * doc/invoke.texi (ARM Options): Document ares. diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index d82e95a226659948e59b317f07e0fd386ed674a2..b3163a90260c66a8df18d00282443434dee96e15 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -1376,6 +1376,17 @@ begin cpu cortex-a76 part d0b end cpu cortex-a76 +begin cpu ares + cname ares + tune for cortex-a57 + tune flags LDSCHED + architecture armv8.2-a+fp16+dotprod+simd + option crypto add FP_ARMv8 CRYPTO + costs cortex_a57 + vendor 41 + part d0c +end cpu ares + # ARMv8.2 A-profile ARM DynamIQ big.LITTLE implementations begin cpu cortex-a75.cortex-a55 cname cortexa75cortexa55 diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt index eacee746a39912d04aa03c636f9a95e0e72ce43b..ceac4b4be419c9bd27db281e9880948ff5c40d76 100644 --- a/gcc/config/arm/arm-tables.opt +++ b/gcc/config/arm/arm-tables.opt @@ -282,6 +282,9 @@ Enum(processor_type) String(cortex-a75) Value( TARGET_CPU_cortexa75) EnumValue Enum(processor_type) String(cortex-a76) Value( TARGET_CPU_cortexa76) +EnumValue +Enum(processor_type) String(ares) Value( TARGET_CPU_ares) + EnumValue Enum(processor_type) String(cortex-a75.cortex-a55) Value( TARGET_CPU_cortexa75cortexa55) diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md index f64c1ef176de6c31659cce35326de8393e9cd886..2bd7e8741166af43f606cee1eb2cc3a0c712af29 100644 --- a/gcc/config/arm/arm-tune.md +++ b/gcc/config/arm/arm-tune.md @@ -49,7 +49,7 @@ (define_attr "tune" cortexa72,cortexa73,exynosm1, xgene1,cortexa57cortexa53,cortexa72cortexa53, cortexa73cortexa35,cortexa73cortexa53,cortexa55, - cortexa75,cortexa76,cortexa75cortexa55, - cortexa76cortexa55,cortexm23,cortexm33, - cortexr52" + cortexa75,cortexa76,ares, + cortexa75cortexa55,cortexa76cortexa55,cortexm23, + cortexm33,cortexr52" (const (symbol_ref "((enum attr_tune) arm_tune)"))) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 5f051ed1acca32a6bd0bb673691a55b72b239c96..81c6232283b0607703f1f3381f1135ebdda36bfe 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -16693,8 +16693,8 @@ Permissible names are: @samp{arm2}, @samp{arm250}, @samp{cortex-a9}, @samp{cortex-a12}, @samp{cortex-a15}, @samp{cortex-a17}, @samp{cortex-a32}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a55}, @samp{cortex-a57}, @samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-a75}, -@samp{cortex-a76}, @samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-r5}, -@samp{cortex-r7}, @samp{cortex-r8}, @samp{cortex-r52}, +@samp{cortex-a76}, @samp{ares}, @samp{cortex-r4}, @samp{cortex-r4f}, +@samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8}, @samp{cortex-r52}, @samp{cortex-m33}, @samp{cortex-m23}, @samp{cortex-m7},