From patchwork Wed Nov 7 09:16:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Hua X-Patchwork-Id: 994154 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-489221-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="yO8aPYzh"; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="HDpJ+jVH"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42qgmC14HVz9sCX for ; Wed, 7 Nov 2018 20:17:14 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:references:in-reply-to:from:date:message-id :subject:to:cc:content-type; q=dns; s=default; b=QHqLzbE6JK/zjpV VAuObP0NrTFa5Z6onxtIR1YbjQKNthUzx2Uhnsg83gfovus5lAPJgfvGZrMBP0XP KMIKTsp0/rKO61dSmLmo3A9sNchkffvgZyNyZsGEJWQ+ddMZBaNmWj/Bc6V6zVQc UzBJYO45lYj6NgLAPgQoKbjs7+20= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:references:in-reply-to:from:date:message-id :subject:to:cc:content-type; s=default; bh=5aGaowsJZh06iV523wNx8 AhlxuA=; b=yO8aPYzh3c3qfyyw3wS2sByMfH3vpuhdAoDzCThXCbJ7m1CKg8+sS eczmYHuNB9fXAS9pedvJH3jXEFJnm0mSbOtJ95bDstho8tLgefcqmv65pm2GnnVZ HQj2i8XcM1Janjp38QTOAUHsmxpWZj2OEz3C+d7DoOhC8hUp9YKVEc= Received: (qmail 35619 invoked by alias); 7 Nov 2018 09:17:07 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 35602 invoked by uid 89); 7 Nov 2018 09:17:06 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-25.6 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=1647 X-HELO: mail-ot1-f44.google.com Received: from mail-ot1-f44.google.com (HELO mail-ot1-f44.google.com) (209.85.210.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 07 Nov 2018 09:17:03 +0000 Received: by mail-ot1-f44.google.com with SMTP id 81so14192317otj.2 for ; Wed, 07 Nov 2018 01:17:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=noHMl1/LNjEZum3kaPyv0n5Jlm9ifb5HdJZBU3wQtx8=; b=HDpJ+jVHZPQzJK3B9RAhqvIZm1UWYk2oHaOWt7Jm1QL50TL6w2GNAaQ3QUB9avJuos v/01aIbvyOTcKUlfEyoVHnb/97PWIsmtPOOR+oWhkmEqr5PZJQdFzvl9RnfVSMXPQp2F z/3md66DZUpgiGXkBh2y70w6Y+tIdTSVrVyhOf2iX9+zxkx92JqQr+xdIQXAWKxc1QYe gjewYheugFZf1YkrfATWuuyN286tX1oYGpkRDrfI8SxFmtu8zgP4avuNJsU255XtZfoC Ew3aZKJaf/3Zp/+zCWicIxNuR455DAqSLPaSd9xDc25HfsZquibkje2mZfKptV2/5WNz yw7A== MIME-Version: 1.0 References: In-Reply-To: From: Paul Hua Date: Wed, 7 Nov 2018 17:16:50 +0800 Message-ID: Subject: [PATCH v4 5/6, Committed] [MIPS] Add Loongson 3A2000/3A3000 processor support To: gcc-patches Cc: Matthew Fortune X-IsSubscribed: yes On Tue, Oct 16, 2018 at 10:50 AM Paul Hua wrote: > > From 51c914e8c2b2e4c7cc93718e563a8f55f0161ff9 Mon Sep 17 00:00:00 2001 From: Chenghua Xu Date: Wed, 7 Nov 2018 09:27:05 +0800 Subject: [PATCH 5/6] Add support for Loongson 3A2000/3A3000 processor. gcc/ * config/mips/gs464e.md: New. * config/mips/mips-cpus.def: Define gs464e. * config/mips/mips-tables.opt: Regenerate. * config/mips/mips.c (mips_rtx_cost_data): Add DEFAULT_COSTS for gs464e. (mips_issue_rate): Add support for gs464e. (mips_multipass_dfa_lookahead): Likewise. (mips_option_override): Enable MMI, EXT and EXT2 for gs464e. * config/mips/mips.h: Define TARGET_GS464E and TUNE_GS464E. (MIPS_ISA_LEVEL_SPEC): Infer mips64r2 from gs464e. (ISA_HAS_FUSED_MADD4): Enable for TARGET_GS464E. (ISA_HAS_UNFUSED_MADD4): Exclude TARGET_GS464E. * config/mips/mips.md: Include gs464e.md. (processor): Add gs464e. * doc/invoke.texi: Add gs464e to supported architectures. --- gcc/config/mips/gs464e.md | 137 ++++++++++++++++++++++++++++++++ gcc/config/mips/mips-cpus.def | 1 + gcc/config/mips/mips-tables.opt | 19 +++-- gcc/config/mips/mips.c | 6 +- gcc/config/mips/mips.h | 13 ++- gcc/config/mips/mips.md | 2 + gcc/doc/invoke.texi | 1 + 7 files changed, 166 insertions(+), 13 deletions(-) create mode 100644 gcc/config/mips/gs464e.md diff --git a/gcc/config/mips/gs464e.md b/gcc/config/mips/gs464e.md new file mode 100644 index 00000000000..60e0e6b0463 --- /dev/null +++ b/gcc/config/mips/gs464e.md @@ -0,0 +1,137 @@ +;; Pipeline model for Loongson gs464e cores. + +;; Copyright (C) 2018 Free Software Foundation, Inc. +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published +;; by the Free Software Foundation; either version 3, or (at your +;; option) any later version. +;; +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +;; License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +;; Uncomment the following line to output automata for debugging. +;; (automata_option "v") + +;; Automaton for integer instructions. +(define_automaton "gs464e_a_alu") + +;; Automaton for floating-point instructions. +(define_automaton "gs464e_a_falu") + +;; Automaton for memory operations. +(define_automaton "gs464e_a_mem") + +;; Describe the resources. + +(define_cpu_unit "gs464e_alu1" "gs464e_a_alu") +(define_cpu_unit "gs464e_alu2" "gs464e_a_alu") +(define_cpu_unit "gs464e_mem1" "gs464e_a_mem") +(define_cpu_unit "gs464e_mem2" "gs464e_a_mem") +(define_cpu_unit "gs464e_falu1" "gs464e_a_falu") +(define_cpu_unit "gs464e_falu2" "gs464e_a_falu") + +;; Describe instruction reservations. + +(define_insn_reservation "gs464e_arith" 1 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "arith,clz,const,logical, + move,nop,shift,signext,slt")) + "gs464e_alu1 | gs464e_alu2") + +(define_insn_reservation "gs464e_branch" 1 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "branch,jump,call,condmove,trap")) + "gs464e_alu1 | gs464e_alu2") + +(define_insn_reservation "gs464e_mfhilo" 1 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "mfhi,mflo,mthi,mtlo")) + "gs464e_alu1 | gs464e_alu2") + +;; Operation imul3nc is fully pipelined. +(define_insn_reservation "gs464e_imul3nc" 5 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "imul3nc")) + "gs464e_alu1 | gs464e_alu2") + +(define_insn_reservation "gs464e_imul" 7 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "imul,imadd")) + "gs464e_alu1 | gs464e_alu2") + +(define_insn_reservation "gs464e_idiv_si" 12 + (and (eq_attr "cpu" "gs464e") + (and (eq_attr "type" "idiv") + (eq_attr "mode" "SI"))) + "gs464e_alu1 | gs464e_alu2") + +(define_insn_reservation "gs464e_idiv_di" 25 + (and (eq_attr "cpu" "gs464e") + (and (eq_attr "type" "idiv") + (eq_attr "mode" "DI"))) + "gs464e_alu1 | gs464e_alu2") + +(define_insn_reservation "gs464e_load" 4 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "load")) + "gs464e_mem1 | gs464e_mem2") + +(define_insn_reservation "gs464e_fpload" 5 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "load,mfc,mtc")) + "gs464e_mem1 | gs464e_mem2") + +(define_insn_reservation "gs464e_prefetch" 0 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "prefetch,prefetchx")) + "gs464e_mem1 | gs464e_mem2") + +(define_insn_reservation "gs464e_store" 0 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "store,fpstore,fpidxstore")) + "gs464e_mem1 | gs464e_mem2") + +(define_insn_reservation "gs464e_fadd" 4 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "fadd,fmul,fmadd")) + "gs464e_falu1 | gs464e_falu2") + +(define_insn_reservation "gs464e_fcmp" 2 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "fabs,fcmp,fmove,fneg")) + "gs464e_falu1 | gs464e_falu2") + +(define_insn_reservation "gs464e_fcvt" 4 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "fcvt")) + "gs464e_falu1 | gs464e_falu2") + +(define_insn_reservation "gs464e_fdiv_sf" 12 + (and (eq_attr "cpu" "gs464e") + (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt") + (eq_attr "mode" "SF"))) + "gs464e_falu1 | gs464e_falu2") + +(define_insn_reservation "gs464e_fdiv_df" 19 + (and (eq_attr "cpu" "gs464e") + (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt") + (eq_attr "mode" "DF"))) + "gs464e_falu1 | gs464e_falu2") + +;; Force single-dispatch for unknown or multi. +(define_insn_reservation "gs464e_unknown" 1 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "unknown,multi,atomic,syncloop")) + "gs464e_alu1 + gs464e_alu2 + gs464e_falu1 + + gs464e_falu2 + gs464e_mem1 + gs464e_mem2") + +;; End of DFA-based pipeline description for gs464e diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def index eabe045cf39..b05b455c3c5 100644 --- a/gcc/config/mips/mips-cpus.def +++ b/gcc/config/mips/mips-cpus.def @@ -164,6 +164,7 @@ MIPS_CPU ("xlr", PROCESSOR_XLR, 64, PTF_AVOID_BRANCHLIKELY_SPEED) /* MIPS64 Release 2 processors. */ MIPS_CPU ("loongson3a", PROCESSOR_GS464, 65, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("gs464", PROCESSOR_GS464, 65, PTF_AVOID_BRANCHLIKELY_SPEED) +MIPS_CPU ("gs464e", PROCESSOR_GS464E, 65, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("octeon+", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("octeon2", PROCESSOR_OCTEON2, 65, PTF_AVOID_BRANCHLIKELY_SPEED) diff --git a/gcc/config/mips/mips-tables.opt b/gcc/config/mips/mips-tables.opt index 3114fce7c70..539266aec89 100644 --- a/gcc/config/mips/mips-tables.opt +++ b/gcc/config/mips/mips-tables.opt @@ -682,26 +682,29 @@ EnumValue Enum(mips_arch_opt_value) String(gs464) Value(97) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon) Value(98) Canonical +Enum(mips_arch_opt_value) String(gs464e) Value(98) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon+) Value(99) Canonical +Enum(mips_arch_opt_value) String(octeon) Value(99) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon2) Value(100) Canonical +Enum(mips_arch_opt_value) String(octeon+) Value(100) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon3) Value(101) Canonical +Enum(mips_arch_opt_value) String(octeon2) Value(101) Canonical EnumValue -Enum(mips_arch_opt_value) String(xlp) Value(102) Canonical +Enum(mips_arch_opt_value) String(octeon3) Value(102) Canonical EnumValue -Enum(mips_arch_opt_value) String(i6400) Value(103) Canonical +Enum(mips_arch_opt_value) String(xlp) Value(103) Canonical EnumValue -Enum(mips_arch_opt_value) String(i6500) Value(104) Canonical +Enum(mips_arch_opt_value) String(i6400) Value(104) Canonical EnumValue -Enum(mips_arch_opt_value) String(p6600) Value(105) Canonical +Enum(mips_arch_opt_value) String(i6500) Value(105) Canonical + +EnumValue +Enum(mips_arch_opt_value) String(p6600) Value(106) Canonical diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index e6dd3795694..74f6f8dfdae 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -839,6 +839,9 @@ static const struct mips_rtx_cost_data { /* Loongson gs464. */ DEFAULT_COSTS }, + { /* Loongson gs464e. */ + DEFAULT_COSTS + }, { /* M4k */ DEFAULT_COSTS }, @@ -14615,6 +14618,7 @@ mips_issue_rate (void) case PROCESSOR_LOONGSON_2E: case PROCESSOR_LOONGSON_2F: case PROCESSOR_GS464: + case PROCESSOR_GS464E: case PROCESSOR_P5600: case PROCESSOR_P6600: return 4; @@ -14746,7 +14750,7 @@ mips_multipass_dfa_lookahead (void) if (TUNE_SB1) return 4; - if (TUNE_LOONGSON_2EF || TUNE_GS464) + if (TUNE_LOONGSON_2EF || TUNE_GS464 || TUNE_GS464E) return 4; if (TUNE_OCTEON) diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 9666107077e..193d399d0b8 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -267,6 +267,7 @@ struct mips_cpu_info { #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F) #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F) #define TARGET_GS464 (mips_arch == PROCESSOR_GS464) +#define TARGET_GS464E (mips_arch == PROCESSOR_GS464E) #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900) #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000) #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120) @@ -299,6 +300,7 @@ struct mips_cpu_info { #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \ || mips_tune == PROCESSOR_LOONGSON_2F) #define TUNE_GS464 (mips_tune == PROCESSOR_GS464) +#define TUNE_GS464E (mips_tune == PROCESSOR_GS464E) #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000) #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900) #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000) @@ -792,7 +794,7 @@ struct mips_cpu_info { %{march=mips32r6: -mips32r6} \ %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \ |march=xlr: -mips64} \ - %{march=mips64r2|march=loongson3a|march=gs464|march=octeon \ + %{march=mips64r2|march=loongson3a|march=gs464|march=gs464e|march=octeon \ |march=xlp: -mips64r2} \ %{march=mips64r3: -mips64r3} \ %{march=mips64r5: -mips64r5} \ @@ -910,7 +912,8 @@ struct mips_cpu_info { #define MIPS_ASE_LOONGSON_EXT_SPEC \ "%{!mno-loongson-ext: \ - %{march=loongson3a|march=gs464: -mloongson-ext}}" + %{march=loongson3a|march=gs464: -mloongson-ext} \ + {march=gs464e: %{!mno-loongson-ext2: -mloongson-ext2 -mloongson-ext}}}" #define DRIVER_SELF_SPECS \ MIPS_ISA_LEVEL_SPEC, \ @@ -1099,14 +1102,16 @@ struct mips_cpu_info { 'd = [+-] (a * b [+-] c)'. */ #define ISA_HAS_FUSED_MADD4 (mips_madd4 \ && (TARGET_MIPS8000 \ - || TARGET_GS464)) + || TARGET_GS464 \ + || TARGET_GS464E)) /* ISA has 4 operand unfused madd instructions of the form 'd = [+-] (a * b [+-] c)'. */ #define ISA_HAS_UNFUSED_MADD4 (mips_madd4 \ && ISA_HAS_FP4 \ && !TARGET_MIPS8000 \ - && !TARGET_GS464) + && !TARGET_GS464 \ + && !TARGET_GS464E) /* ISA has 3 operand r6 fused madd instructions of the form 'c = c [+-] (a * b)'. */ diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index d347a253ff1..acf572ab0d3 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -38,6 +38,7 @@ loongson_2e loongson_2f gs464 + gs464e m4k octeon octeon2 @@ -1174,6 +1175,7 @@ (include "10000.md") (include "loongson2ef.md") (include "gs464.md") +(include "gs464e.md") (include "octeon.md") (include "sb1.md") (include "sr71k.md") diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 9780cb8f255..32929915622 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -20800,6 +20800,7 @@ The processor names are: @samp{i6400}, @samp{i6500}, @samp{interaptiv}, @samp{loongson2e}, @samp{loongson2f}, @samp{loongson3a}, @samp{gs464}, +@samp{gs464e}, @samp{m4k}, @samp{m14k}, @samp{m14kc}, @samp{m14ke}, @samp{m14kec}, @samp{m5100}, @samp{m5101}, -- 2.18.0