[v4,3/6,Committed,MIPS] Add Loongson EXTensions R2 (EXT2) instructions support
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Message ID CAKjxQH=O-=1DRP+dQXXDanbh46eVaUhazMXqFveaLpYs8XdsLA@mail.gmail.com
State New
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Series
  • Untitled series #74440
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Commit Message

Paul Hua Nov. 7, 2018, 9:14 a.m. UTC
On Tue, Oct 16, 2018 at 10:50 AM Paul Hua <paul.hua.gm@gmail.com> wrote:
>
>

Comments

Paul Hua Nov. 7, 2018, 10:33 a.m. UTC | #1
sorry, i commits a wrong version patch. Fix the typo and bad logical
by commits attached patch.
On Wed, Nov 7, 2018 at 5:14 PM Paul Hua <paul.hua.gm@gmail.com> wrote:
>
> On Tue, Oct 16, 2018 at 10:50 AM Paul Hua <paul.hua.gm@gmail.com> wrote:
> >
> >
From 16a357d8f844e4bdc45bf385e98b8dc6c0723720 Mon Sep 17 00:00:00 2001
From: Chenghua Xu <paul.hua.gm@gmail.com>
Date: Wed, 7 Nov 2018 18:15:03 +0800
Subject: [PATCH] Fix some typo and brain twister logical.

gcc/
	* config/mips/mips.c: Fix typo in documentation of
	mips_loongson_ext2_prefetch_cookie.
	(mips_option_override): fix brain twister logical.
	* config/mips/mips.h: Fix typo in documentation of
	ISA_HAS_CTZ_CTO and define pattern.
	* config/mips/mips.md (prefetch): Hoist EXT2 above
	the 2EF/EXT block.
	(prefetch_indexed): Hoist EXT2 above the EXT block.

gcc/testsuite/
	* gcc.target/mips/loongson-ctz.c: Fix typo.
	* gcc.target/mips/loongson-dctz.c: Fix typo.
---
 gcc/config/mips/mips.c                        |  4 +--
 gcc/config/mips/mips.h                        |  2 +-
 gcc/config/mips/mips.md                       | 34 +++++++++----------
 gcc/testsuite/gcc.target/mips/loongson-ctz.c  |  2 +-
 gcc/testsuite/gcc.target/mips/loongson-dctz.c |  2 +-
 5 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 2b83e4ec679..d78e2056ec2 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -15151,7 +15151,7 @@ mips_prefetch_cookie (rtx write, rtx locality)
   return GEN_INT (INTVAL (write) + 6);
 }
 
-/* Loongson EXT2 only implements perf hint=0 (prefetch for load) and hint=1
+/* Loongson EXT2 only implements pref hint=0 (prefetch for load) and hint=1
    (prefetch for store), other hint just scale to hint = 0 and hint = 1.  */
 
 rtx
@@ -20202,7 +20202,7 @@ mips_option_override (void)
 	 is true.  If a user explicitly says -mloongson-ext2 -mno-loongson-ext
 	 then that is an error.  */
       if (!TARGET_LOONGSON_EXT
-	  && !((target_flags_explicit & MASK_LOONGSON_EXT) == 0))
+	  && (target_flags_explicit & MASK_LOONGSON_EXT) != 0)
 	error ("%<-mloongson-ext2%> must be used with %<-mloongson-ext%>");
       target_flags |= MASK_LOONGSON_EXT;
     }
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 0a92cf6788a..11ca364d752 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -1158,7 +1158,7 @@ struct mips_cpu_info {
 /* ISA has count leading zeroes/ones instruction (not implemented).  */
 #define ISA_HAS_CLZ_CLO		(mips_isa_rev >= 1 && !TARGET_MIPS16)
 
-/* ISA has count tailing zeroes/ones instruction.  */
+/* ISA has count trailing zeroes/ones instruction.  */
 #define ISA_HAS_CTZ_CTO		(TARGET_LOONGSON_EXT2)
 
 /* ISA has three operand multiply instructions that put
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 9e222dc0df0..0cb0cb80bcd 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -3153,7 +3153,7 @@
 ;;
 ;;  ...................
 ;;
-;;  Count tailing zeroes.
+;;  Count trailing zeroes.
 ;;
 ;;  ...................
 ;;
@@ -7157,21 +7157,21 @@
 	     (match_operand 2 "const_int_operand" "n"))]
   "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
 {
-  if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || TARGET_LOONGSON_EXT2)
+  if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT)
     {
-      /* Loongson ext2 implementation pref insnstructions.  */
-      if (TARGET_LOONGSON_EXT2)
-	{
-  	  operands[1] = mips_loongson_ext2_prefetch_cookie (operands[1],
-							    operands[2]);
-	  return "pref\t%1, %a0";
-	}
       /* Loongson 2[ef] and Loongson ext use load to $0 for prefetching.  */
       if (TARGET_64BIT)
 	return "ld\t$0,%a0";
       else
 	return "lw\t$0,%a0";
     }
+  /* Loongson ext2 implementation pref instructions.  */
+  if (TARGET_LOONGSON_EXT2)
+    {
+      operands[1] = mips_loongson_ext2_prefetch_cookie (operands[1],
+							operands[2]);
+      return "pref\t%1, %a0";
+    }
   operands[1] = mips_prefetch_cookie (operands[1], operands[2]);
   return "pref\t%1,%a0";
 }
@@ -7184,21 +7184,21 @@
 	     (match_operand 3 "const_int_operand" "n"))]
   "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
 {
-  if (TARGET_LOONGSON_EXT || TARGET_LOONGSON_EXT2)
+  if (TARGET_LOONGSON_EXT)
     {
-      /* Loongson ext2 implementation pref insnstructions.  */
-      if (TARGET_LOONGSON_EXT2)
-	{
-  	  operands[2] = mips_loongson_ext2_prefetch_cookie (operands[2],
-							    operands[3]);
-	  return "prefx\t%2,%1(%0)";
-	}
       /* Loongson Loongson ext use index load to $0 for prefetching.  */
       if (TARGET_64BIT)
 	return "gsldx\t$0,0(%0,%1)";
       else
 	return "gslwx\t$0,0(%0,%1)";
     }
+  /* Loongson ext2 implementation pref instructions.  */
+  if (TARGET_LOONGSON_EXT2)
+    {
+      operands[2] = mips_loongson_ext2_prefetch_cookie (operands[2],
+							operands[3]);
+      return "prefx\t%2,%1(%0)";
+    }
   operands[2] = mips_prefetch_cookie (operands[2], operands[3]);
   return "prefx\t%2,%1(%0)";
 }
diff --git a/gcc/testsuite/gcc.target/mips/loongson-ctz.c b/gcc/testsuite/gcc.target/mips/loongson-ctz.c
index 8df66a00dc1..7238fe2f281 100644
--- a/gcc/testsuite/gcc.target/mips/loongson-ctz.c
+++ b/gcc/testsuite/gcc.target/mips/loongson-ctz.c
@@ -1,4 +1,4 @@
-/* Test cases for Loongson EXT2 instrutions.  */
+/* Test cases for Loongson EXT2 instructions.  */
 
 /* { dg-do compile } */
 /* { dg-options "-mloongson-ext2" } */
diff --git a/gcc/testsuite/gcc.target/mips/loongson-dctz.c b/gcc/testsuite/gcc.target/mips/loongson-dctz.c
index 8c47433459f..f0c42f8a069 100644
--- a/gcc/testsuite/gcc.target/mips/loongson-dctz.c
+++ b/gcc/testsuite/gcc.target/mips/loongson-dctz.c
@@ -1,4 +1,4 @@
-/* Test cases for Loongson EXT2 instrutions.  */
+/* Test cases for Loongson EXT2 instructions.  */
 
 /* { dg-do compile } */
 /* { dg-options "-mloongson-ext2" } */

Patch
diff mbox series

From 73a4aac5034307cf7369bb70fa407709502fffbf Mon Sep 17 00:00:00 2001
From: Chenghua Xu <paul.hua.gm@gmail.com>
Date: Fri, 31 Aug 2018 11:55:48 +0800
Subject: [PATCH 3/6] Add support for Loongson EXT2 instructions.

gcc/
	* config/mips/mips-protos.h
	(mips_loongson_ext2_prefetch_cookie): New prototype.
	* config/mips/mips.c (mips_loongson_ext2_prefetch_cookie): New.
	(mips_option_override): Enable TARGET_LOONGSON_EXT when
	TARGET_LOONGSON_EXT2 is true.
	* config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): Define
	__mips_loongson_ext2, __mips_loongson_ext_rev=2.
	(ISA_HAS_CTZ_CTO): New, true if TARGET_LOONGSON_EXT2.
	(ISA_HAS_PREFETCH): Include TARGET_LOONGSON_EXT and
	TARGET_LOONGSON_EXT2.
	(ASM_SPEC): Add mloongson-ext2 and mno-loongson-ext2.
	(define_insn "ctz<mode>2"): New insn pattern.
	(define_insn "prefetch"): Include TARGET_LOONGSON_EXT2.
	(define_insn "prefetch_indexed_<mode>"): Include
	TARGET_LOONGSON_EXT and TARGET_LOONGSON_EXT2.
	* config/mips/mips.opt (-mloongson-ext2): Add option.
	* gcc/doc/invoke.texi (-mloongson-ext2): Document.

gcc/testsuite/
	* gcc.target/mips/loongson-ctz.c: New test.
	* gcc.target/mips/loongson-dctz.c: Likewise.
	* gcc.target/mips/mips.exp (mips_option_groups): Add
	-mloongson-ext2 option.
---
 gcc/config/mips/mips-protos.h                 |  1 +
 gcc/config/mips/mips.c                        | 28 +++++++++++
 gcc/config/mips/mips.h                        | 15 +++++-
 gcc/config/mips/mips.md                       | 47 +++++++++++++++++--
 gcc/config/mips/mips.opt                      |  4 ++
 gcc/doc/invoke.texi                           |  7 +++
 gcc/testsuite/gcc.target/mips/loongson-ctz.c  | 11 +++++
 gcc/testsuite/gcc.target/mips/loongson-dctz.c | 11 +++++
 gcc/testsuite/gcc.target/mips/mips.exp        |  1 +
 9 files changed, 120 insertions(+), 5 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/mips/loongson-ctz.c
 create mode 100644 gcc/testsuite/gcc.target/mips/loongson-dctz.c

diff --git a/gcc/config/mips/mips-protos.h b/gcc/config/mips/mips-protos.h
index 099120db7b4..7cde2424016 100644
--- a/gcc/config/mips/mips-protos.h
+++ b/gcc/config/mips/mips-protos.h
@@ -323,6 +323,7 @@  extern bool mips_linked_madd_p (rtx_insn *, rtx_insn *);
 extern bool mips_store_data_bypass_p (rtx_insn *, rtx_insn *);
 extern int mips_dspalu_bypass_p (rtx, rtx);
 extern rtx mips_prefetch_cookie (rtx, rtx);
+extern rtx mips_loongson_ext2_prefetch_cookie (rtx, rtx);
 
 extern const char *current_section_name (void);
 extern unsigned int current_section_flags (void);
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index b579c3c3a2a..1c2075044d0 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -15142,6 +15142,22 @@  mips_prefetch_cookie (rtx write, rtx locality)
   /* store_retained / load_retained.  */
   return GEN_INT (INTVAL (write) + 6);
 }
+
+/* Loongson EXT2 only implements perf hint=0 (prefetch for load) and hint=1
+   (prefetch for store), other hint just scale to hint = 0 and hint = 1.  */
+
+rtx
+mips_loongson_ext2_prefetch_cookie (rtx write, rtx locality)
+{
+  /* store.  */
+  if (INTVAL (write) == 1)
+    return GEN_INT (INTVAL (write));
+
+  /* load.  */
+  if (INTVAL (write) == 0)
+    return GEN_INT (INTVAL (write));
+}
+
 
 /* Flags that indicate when a built-in function is available.
 
@@ -20171,6 +20187,18 @@  mips_option_override (void)
   if (TARGET_LOONGSON_MMI &&  !TARGET_HARD_FLOAT_ABI)
     error ("%<-mloongson-mmi%> must be used with %<-mhard-float%>");
 
+  /* If TARGET_LOONGSON_EXT2, enable TARGET_LOONGSON_EXT.  */
+  if (TARGET_LOONGSON_EXT2)
+    {
+      /* Make sure that when TARGET_LOONGSON_EXT2 is true, TARGET_LOONGSON_EXT
+	 is true.  If a user explicitly says -mloongson-ext2 -mno-loongson-ext
+	 then that is an error.  */
+      if (!TARGET_LOONGSON_EXT
+	  && !((target_flags_explicit & MASK_LOONGSON_EXT) == 0))
+	error ("%<-mloongson-ext2%> must be used with %<-mloongson-ext%>");
+      target_flags |= MASK_LOONGSON_EXT;
+    }
+
   /* .eh_frame addresses should be the same width as a C pointer.
      Most MIPS ABIs support only one pointer size, so the assembler
      will usually know exactly how big an .eh_frame address is.
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 7237c8da8ac..beeb4bcf20d 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -600,6 +600,13 @@  struct mips_cpu_info {
       if (TARGET_LOONGSON_EXT)						\
 	{								\
 	  builtin_define ("__mips_loongson_ext");			\
+	  if (TARGET_LOONGSON_EXT2)					\
+	    {								\
+	      builtin_define ("__mips_loongson_ext2");			\
+	      builtin_define ("__mips_loongson_ext_rev=2");		\
+	    }								\
+	  else								\
+	      builtin_define ("__mips_loongson_ext_rev=1");		\
 	}								\
 									\
       /* Historical Octeon macro.  */					\
@@ -1134,6 +1141,9 @@  struct mips_cpu_info {
 /* ISA has count leading zeroes/ones instruction (not implemented).  */
 #define ISA_HAS_CLZ_CLO		(mips_isa_rev >= 1 && !TARGET_MIPS16)
 
+/* ISA has count tailing zeroes/ones instruction.  */
+#define ISA_HAS_CTZ_CTO		(TARGET_LOONGSON_EXT2)
+
 /* ISA has three operand multiply instructions that put
    the high part in an accumulator: mulhi or mulhiu.  */
 #define ISA_HAS_MULHI		((TARGET_MIPS5400			 \
@@ -1195,7 +1205,9 @@  struct mips_cpu_info {
    'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
    (prefx is a cop1x instruction, so can only be used if FP is
    enabled.)  */
-#define ISA_HAS_PREFETCHX	ISA_HAS_FP4
+#define ISA_HAS_PREFETCHX	(ISA_HAS_FP4				\
+				 || TARGET_LOONGSON_EXT			\
+				 || TARGET_LOONGSON_EXT2)
 
 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
    instructions.  Both require TARGET_HARD_FLOAT, and trunc.w.d
@@ -1379,6 +1391,7 @@  struct mips_cpu_info {
 %{mmsa} %{mno-msa} \
 %{mloongson-mmi} %{mno-loongson-mmi} \
 %{mloongson-ext} %{mno-loongson-ext} \
+%{mloongson-ext2} %{mno-loongson-ext2} \
 %{msmartmips} %{mno-smartmips} \
 %{mmt} %{mno-mt} \
 %{mfix-rm7000} %{mno-fix-rm7000} \
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 4b7a627b7a6..8358218d8ac 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -3146,6 +3146,23 @@ 
   [(set_attr "type" "clz")
    (set_attr "mode" "<MODE>")])
 
+;;
+;;  ...................
+;;
+;;  Count tailing zeroes.
+;;
+;;  ...................
+;;
+
+(define_insn "ctz<mode>2"
+  [(set (match_operand:GPR 0 "register_operand" "=d")
+	(ctz:GPR (match_operand:GPR 1 "register_operand" "d")))]
+  "ISA_HAS_CTZ_CTO"
+  "<d>ctz\t%0,%1"
+  [(set_attr "type" "clz")
+   (set_attr "mode" "<MODE>")])
+
+
 ;;
 ;;  ...................
 ;;
@@ -7136,13 +7153,20 @@ 
 	     (match_operand 2 "const_int_operand" "n"))]
   "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
 {
-  if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT)
+  if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || TARGET_LOONGSON_EXT2)
     {
-      /* Loongson 2[ef] and Loongson 3a use load to $0 for prefetching.  */
+      /* Loongson ext2 implementation pref insnstructions.  */
+      if (TARGET_LOONGSON_EXT2)
+	{
+  	  operands[1] = mips_loongson_ext2_prefetch_cookie (operands[1],
+							    operands[2]);
+	  return "pref\t%1, %a0";
+	}
+      /* Loongson 2[ef] and Loongson ext use load to $0 for prefetching.  */
       if (TARGET_64BIT)
-        return "ld\t$0,%a0";
+	return "ld\t$0,%a0";
       else
-        return "lw\t$0,%a0";
+	return "lw\t$0,%a0";
     }
   operands[1] = mips_prefetch_cookie (operands[1], operands[2]);
   return "pref\t%1,%a0";
@@ -7156,6 +7180,21 @@ 
 	     (match_operand 3 "const_int_operand" "n"))]
   "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
 {
+  if (TARGET_LOONGSON_EXT || TARGET_LOONGSON_EXT2)
+    {
+      /* Loongson ext2 implementation pref insnstructions.  */
+      if (TARGET_LOONGSON_EXT2)
+	{
+  	  operands[2] = mips_loongson_ext2_prefetch_cookie (operands[2],
+							    operands[3]);
+	  return "prefx\t%2,%1(%0)";
+	}
+      /* Loongson Loongson ext use index load to $0 for prefetching.  */
+      if (TARGET_64BIT)
+	return "gsldx\t$0,0(%0,%1)";
+      else
+	return "gslwx\t$0,0(%0,%1)";
+    }
   operands[2] = mips_prefetch_cookie (operands[2], operands[3]);
   return "prefx\t%2,%1(%0)";
 }
diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt
index a8fe8db3c66..c0c8005b025 100644
--- a/gcc/config/mips/mips.opt
+++ b/gcc/config/mips/mips.opt
@@ -467,3 +467,7 @@  Use Loongson MultiMedia extensions Instructions (MMI) instructions.
 mloongson-ext
 Target Report Mask(LOONGSON_EXT)
 Use Loongson EXTension (EXT) instructions.
+
+mloongson-ext2
+Target Report Mask(LOONGSON_EXT2)
+Use Loongson EXTension R2 (EXT2) instructions.
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index ae92323eb06..d36a15a34ef 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -922,6 +922,7 @@  Objective-C and Objective-C++ Dialects}.
 -mmsa  -mno-msa @gol
 -mloongson-mmi  -mno-loongson-mmi @gol
 -mloongson-ext  -mno-loongson-ext @gol
+-mloongson-ext2  -mno-loongson-ext2 @gol
 -mfpu=@var{fpu-type} @gol
 -msmartmips  -mno-smartmips @gol
 -mpaired-single  -mno-paired-single  -mdmx  -mno-mdmx @gol
@@ -21301,6 +21302,12 @@  Use (do not use) the MIPS Loongson MultiMedia extensions Instructions (MMI).
 @opindex mno-loongson-ext
 Use (do not use) the MIPS Loongson EXTensions (EXT) instructions.
 
+@item -mloongson-ext2
+@itemx -mno-loongson-ext2
+@opindex mloongson-ext2
+@opindex mno-loongson-ext2
+Use (do not use) the MIPS Loongson EXTensions r2 (EXT2) instructions.
+
 @item -mlong64
 @opindex mlong64
 Force @code{long} types to be 64 bits wide.  See @option{-mlong32} for
diff --git a/gcc/testsuite/gcc.target/mips/loongson-ctz.c b/gcc/testsuite/gcc.target/mips/loongson-ctz.c
new file mode 100644
index 00000000000..8df66a00dc1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/loongson-ctz.c
@@ -0,0 +1,11 @@ 
+/* Test cases for Loongson EXT2 instrutions.  */
+
+/* { dg-do compile } */
+/* { dg-options "-mloongson-ext2" } */
+
+unsigned int foo(unsigned int x)
+{
+  return __builtin_ctz (x);
+}
+
+/* { dg-final { scan-assembler "ctz\t" } } */
diff --git a/gcc/testsuite/gcc.target/mips/loongson-dctz.c b/gcc/testsuite/gcc.target/mips/loongson-dctz.c
new file mode 100644
index 00000000000..8c47433459f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/loongson-dctz.c
@@ -0,0 +1,11 @@ 
+/* Test cases for Loongson EXT2 instrutions.  */
+
+/* { dg-do compile } */
+/* { dg-options "-mloongson-ext2" } */
+
+unsigned long long foo(unsigned long long x)
+{
+  return __builtin_ctzl (x);
+}
+
+/* { dg-final { scan-assembler "dctz\t" } } */
diff --git a/gcc/testsuite/gcc.target/mips/mips.exp b/gcc/testsuite/gcc.target/mips/mips.exp
index ceb86cc0276..e70d416d0dd 100644
--- a/gcc/testsuite/gcc.target/mips/mips.exp
+++ b/gcc/testsuite/gcc.target/mips/mips.exp
@@ -298,6 +298,7 @@  foreach option {
     msa
     loongson-mmi
     loongson-ext
+    loongson-ext2
 } {
     lappend mips_option_groups $option "-m(no-|)$option"
 }
-- 
2.18.0