[Disco,SRU,Cosmic,SRU,Bionic] net: hns3: Set tx ring' tc info when netdev is up

Message ID 20181107012538.GA17236@xps13.dannf
State New
Headers show
Series
  • [Disco,SRU,Cosmic,SRU,Bionic] net: hns3: Set tx ring' tc info when netdev is up
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Commit Message

dann frazier Nov. 7, 2018, 1:25 a.m.
From: Yunsheng Lin <linyunsheng@huawei.com>

BugLink: https://bugs.launchpad.net/bugs/1802023

The HNS3_RING_TX_RING_TC_REG register is used to map tx ring to
specific tc, the tx queue to tc mapping is needed by the hardware
to do the correct tx schedule.

Signed-off-by: Yunsheng Lin <linyunsheng@huawei.com>
Signed-off-by: Peng Li <lipeng321@huawei.com>
Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(backported from commit 1c77215480bcfa0852575180f997bd156f2aef17)
[ dannf: Trivial offset fix in hns3_enet.h ]
Signed-off-by: dann frazier <dann.frazier@canonical.com>
---
 .../net/ethernet/hisilicon/hns3/hns3_enet.c   | 24 +++++++++++++++++++
 .../net/ethernet/hisilicon/hns3/hns3_enet.h   |  1 +
 2 files changed, 25 insertions(+)

Comments

Kleber Souza Nov. 7, 2018, 9:05 a.m. | #1
On 11/07/18 02:25, dann frazier wrote:
> From: Yunsheng Lin <linyunsheng@huawei.com>
>
> BugLink: https://bugs.launchpad.net/bugs/1802023
>
> The HNS3_RING_TX_RING_TC_REG register is used to map tx ring to
> specific tc, the tx queue to tc mapping is needed by the hardware
> to do the correct tx schedule.
>
> Signed-off-by: Yunsheng Lin <linyunsheng@huawei.com>
> Signed-off-by: Peng Li <lipeng321@huawei.com>
> Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
> Signed-off-by: David S. Miller <davem@davemloft.net>
> (backported from commit 1c77215480bcfa0852575180f997bd156f2aef17)
> [ dannf: Trivial offset fix in hns3_enet.h ]
> Signed-off-by: dann frazier <dann.frazier@canonical.com>

Acked-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>

> ---
>  .../net/ethernet/hisilicon/hns3/hns3_enet.c   | 24 +++++++++++++++++++
>  .../net/ethernet/hisilicon/hns3/hns3_enet.h   |  1 +
>  2 files changed, 25 insertions(+)
>
> diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
> index 18c93eb9c045e..f6ca760ea65c8 100644
> --- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
> +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
> @@ -2998,6 +2998,28 @@ static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
>  	}
>  }
>  
> +static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
> +{
> +	struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
> +	int i;
> +
> +	for (i = 0; i < HNAE3_MAX_TC; i++) {
> +		struct hnae3_tc_info *tc_info = &kinfo->tc_info[i];
> +		int j;
> +
> +		if (!tc_info->enable)
> +			continue;
> +
> +		for (j = 0; j < tc_info->tqp_count; j++) {
> +			struct hnae3_queue *q;
> +
> +			q = priv->ring_data[tc_info->tqp_offset + j].ring->tqp;
> +			hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG,
> +				       tc_info->tc);
> +		}
> +	}
> +}
> +
>  int hns3_init_all_ring(struct hns3_nic_priv *priv)
>  {
>  	struct hnae3_handle *h = priv->ae_handle;
> @@ -3409,6 +3431,8 @@ int hns3_nic_reset_all_ring(struct hnae3_handle *h)
>  		rx_ring->next_to_use = 0;
>  	}
>  
> +	hns3_init_tx_ring_tc(priv);
> +
>  	return 0;
>  }
>  
> diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
> index e4b4a8f2ceaab..902b751206608 100644
> --- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
> +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
> @@ -38,6 +38,7 @@ enum hns3_nic_state {
>  #define HNS3_RING_TX_RING_BASEADDR_H_REG	0x00044
>  #define HNS3_RING_TX_RING_BD_NUM_REG		0x00048
>  #define HNS3_RING_TX_RING_BD_LEN_REG		0x0004C
> +#define HNS3_RING_TX_RING_TC_REG		0x00050
>  #define HNS3_RING_TX_RING_TAIL_REG		0x00058
>  #define HNS3_RING_TX_RING_HEAD_REG		0x0005C
>  #define HNS3_RING_TX_RING_FBDNUM_REG		0x00060
Stefan Bader Nov. 7, 2018, 12:55 p.m. | #2
On 07.11.18 02:25, dann frazier wrote:
> From: Yunsheng Lin <linyunsheng@huawei.com>
> 
> BugLink: https://bugs.launchpad.net/bugs/1802023
> 
> The HNS3_RING_TX_RING_TC_REG register is used to map tx ring to
> specific tc, the tx queue to tc mapping is needed by the hardware
> to do the correct tx schedule.
> 
> Signed-off-by: Yunsheng Lin <linyunsheng@huawei.com>
> Signed-off-by: Peng Li <lipeng321@huawei.com>
> Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
> Signed-off-by: David S. Miller <davem@davemloft.net>
> (backported from commit 1c77215480bcfa0852575180f997bd156f2aef17)
> [ dannf: Trivial offset fix in hns3_enet.h ]
> Signed-off-by: dann frazier <dann.frazier@canonical.com>
Acked-by: Stefan Bader <stefan.bader@canonical.com>
> ---
>  .../net/ethernet/hisilicon/hns3/hns3_enet.c   | 24 +++++++++++++++++++
>  .../net/ethernet/hisilicon/hns3/hns3_enet.h   |  1 +
>  2 files changed, 25 insertions(+)
> 
> diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
> index 18c93eb9c045e..f6ca760ea65c8 100644
> --- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
> +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
> @@ -2998,6 +2998,28 @@ static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
>  	}
>  }
>  
> +static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
> +{
> +	struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
> +	int i;
> +
> +	for (i = 0; i < HNAE3_MAX_TC; i++) {
> +		struct hnae3_tc_info *tc_info = &kinfo->tc_info[i];
> +		int j;
> +
> +		if (!tc_info->enable)
> +			continue;
> +
> +		for (j = 0; j < tc_info->tqp_count; j++) {
> +			struct hnae3_queue *q;
> +
> +			q = priv->ring_data[tc_info->tqp_offset + j].ring->tqp;
> +			hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG,
> +				       tc_info->tc);
> +		}
> +	}
> +}
> +
>  int hns3_init_all_ring(struct hns3_nic_priv *priv)
>  {
>  	struct hnae3_handle *h = priv->ae_handle;
> @@ -3409,6 +3431,8 @@ int hns3_nic_reset_all_ring(struct hnae3_handle *h)
>  		rx_ring->next_to_use = 0;
>  	}
>  
> +	hns3_init_tx_ring_tc(priv);
> +
>  	return 0;
>  }
>  
> diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
> index e4b4a8f2ceaab..902b751206608 100644
> --- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
> +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
> @@ -38,6 +38,7 @@ enum hns3_nic_state {
>  #define HNS3_RING_TX_RING_BASEADDR_H_REG	0x00044
>  #define HNS3_RING_TX_RING_BD_NUM_REG		0x00048
>  #define HNS3_RING_TX_RING_BD_LEN_REG		0x0004C
> +#define HNS3_RING_TX_RING_TC_REG		0x00050
>  #define HNS3_RING_TX_RING_TAIL_REG		0x00058
>  #define HNS3_RING_TX_RING_HEAD_REG		0x0005C
>  #define HNS3_RING_TX_RING_FBDNUM_REG		0x00060
>
Khaled Elmously Nov. 8, 2018, 4:06 a.m. | #3
On 2018-11-06 18:25:38 , dann frazier wrote:
> From: Yunsheng Lin <linyunsheng@huawei.com>
> 
> BugLink: https://bugs.launchpad.net/bugs/1802023
> 
> The HNS3_RING_TX_RING_TC_REG register is used to map tx ring to
> specific tc, the tx queue to tc mapping is needed by the hardware
> to do the correct tx schedule.
> 
> Signed-off-by: Yunsheng Lin <linyunsheng@huawei.com>
> Signed-off-by: Peng Li <lipeng321@huawei.com>
> Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
> Signed-off-by: David S. Miller <davem@davemloft.net>
> (backported from commit 1c77215480bcfa0852575180f997bd156f2aef17)
> [ dannf: Trivial offset fix in hns3_enet.h ]
> Signed-off-by: dann frazier <dann.frazier@canonical.com>
> ---
>  .../net/ethernet/hisilicon/hns3/hns3_enet.c   | 24 +++++++++++++++++++
>  .../net/ethernet/hisilicon/hns3/hns3_enet.h   |  1 +
>  2 files changed, 25 insertions(+)
> 
> diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
> index 18c93eb9c045e..f6ca760ea65c8 100644
> --- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
> +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
> @@ -2998,6 +2998,28 @@ static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
>  	}
>  }
>  
> +static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
> +{
> +	struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
> +	int i;
> +
> +	for (i = 0; i < HNAE3_MAX_TC; i++) {
> +		struct hnae3_tc_info *tc_info = &kinfo->tc_info[i];
> +		int j;
> +
> +		if (!tc_info->enable)
> +			continue;
> +
> +		for (j = 0; j < tc_info->tqp_count; j++) {
> +			struct hnae3_queue *q;
> +
> +			q = priv->ring_data[tc_info->tqp_offset + j].ring->tqp;
> +			hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG,
> +				       tc_info->tc);
> +		}
> +	}
> +}
> +
>  int hns3_init_all_ring(struct hns3_nic_priv *priv)
>  {
>  	struct hnae3_handle *h = priv->ae_handle;
> @@ -3409,6 +3431,8 @@ int hns3_nic_reset_all_ring(struct hnae3_handle *h)
>  		rx_ring->next_to_use = 0;
>  	}
>  
> +	hns3_init_tx_ring_tc(priv);
> +
>  	return 0;
>  }
>  
> diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
> index e4b4a8f2ceaab..902b751206608 100644
> --- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
> +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
> @@ -38,6 +38,7 @@ enum hns3_nic_state {
>  #define HNS3_RING_TX_RING_BASEADDR_H_REG	0x00044
>  #define HNS3_RING_TX_RING_BD_NUM_REG		0x00048
>  #define HNS3_RING_TX_RING_BD_LEN_REG		0x0004C
> +#define HNS3_RING_TX_RING_TC_REG		0x00050
>  #define HNS3_RING_TX_RING_TAIL_REG		0x00058
>  #define HNS3_RING_TX_RING_HEAD_REG		0x0005C
>  #define HNS3_RING_TX_RING_FBDNUM_REG		0x00060
> -- 
> 2.19.1
> 
> 
> -- 
> kernel-team mailing list
> kernel-team@lists.ubuntu.com
> https://lists.ubuntu.com/mailman/listinfo/kernel-team
Khaled Elmously Nov. 8, 2018, 4:11 a.m. | #4
On 2018-11-06 18:25:38 , dann frazier wrote:
> From: Yunsheng Lin <linyunsheng@huawei.com>
> 
> BugLink: https://bugs.launchpad.net/bugs/1802023
> 
> The HNS3_RING_TX_RING_TC_REG register is used to map tx ring to
> specific tc, the tx queue to tc mapping is needed by the hardware
> to do the correct tx schedule.
> 
> Signed-off-by: Yunsheng Lin <linyunsheng@huawei.com>
> Signed-off-by: Peng Li <lipeng321@huawei.com>
> Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
> Signed-off-by: David S. Miller <davem@davemloft.net>
> (backported from commit 1c77215480bcfa0852575180f997bd156f2aef17)
> [ dannf: Trivial offset fix in hns3_enet.h ]
> Signed-off-by: dann frazier <dann.frazier@canonical.com>
> ---
>  .../net/ethernet/hisilicon/hns3/hns3_enet.c   | 24 +++++++++++++++++++
>  .../net/ethernet/hisilicon/hns3/hns3_enet.h   |  1 +
>  2 files changed, 25 insertions(+)
> 
> diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
> index 18c93eb9c045e..f6ca760ea65c8 100644
> --- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
> +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
> @@ -2998,6 +2998,28 @@ static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
>  	}
>  }
>  
> +static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
> +{
> +	struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
> +	int i;
> +
> +	for (i = 0; i < HNAE3_MAX_TC; i++) {
> +		struct hnae3_tc_info *tc_info = &kinfo->tc_info[i];
> +		int j;
> +
> +		if (!tc_info->enable)
> +			continue;
> +
> +		for (j = 0; j < tc_info->tqp_count; j++) {
> +			struct hnae3_queue *q;
> +
> +			q = priv->ring_data[tc_info->tqp_offset + j].ring->tqp;
> +			hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG,
> +				       tc_info->tc);
> +		}
> +	}
> +}
> +
>  int hns3_init_all_ring(struct hns3_nic_priv *priv)
>  {
>  	struct hnae3_handle *h = priv->ae_handle;
> @@ -3409,6 +3431,8 @@ int hns3_nic_reset_all_ring(struct hnae3_handle *h)
>  		rx_ring->next_to_use = 0;
>  	}
>  
> +	hns3_init_tx_ring_tc(priv);
> +
>  	return 0;
>  }
>  
> diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
> index e4b4a8f2ceaab..902b751206608 100644
> --- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
> +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
> @@ -38,6 +38,7 @@ enum hns3_nic_state {
>  #define HNS3_RING_TX_RING_BASEADDR_H_REG	0x00044
>  #define HNS3_RING_TX_RING_BD_NUM_REG		0x00048
>  #define HNS3_RING_TX_RING_BD_LEN_REG		0x0004C
> +#define HNS3_RING_TX_RING_TC_REG		0x00050
>  #define HNS3_RING_TX_RING_TAIL_REG		0x00058
>  #define HNS3_RING_TX_RING_HEAD_REG		0x0005C
>  #define HNS3_RING_TX_RING_FBDNUM_REG		0x00060
> -- 
> 2.19.1
> 
> 
> -- 
> kernel-team mailing list
> kernel-team@lists.ubuntu.com
> https://lists.ubuntu.com/mailman/listinfo/kernel-team
Thadeu Lima de Souza Cascardo Nov. 8, 2018, 12:06 p.m. | #5
This is already in unstable/master, as it is upstream as of 4.19.

Cascardo.

Patch

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
index 18c93eb9c045e..f6ca760ea65c8 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
@@ -2998,6 +2998,28 @@  static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
 	}
 }
 
+static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
+{
+	struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
+	int i;
+
+	for (i = 0; i < HNAE3_MAX_TC; i++) {
+		struct hnae3_tc_info *tc_info = &kinfo->tc_info[i];
+		int j;
+
+		if (!tc_info->enable)
+			continue;
+
+		for (j = 0; j < tc_info->tqp_count; j++) {
+			struct hnae3_queue *q;
+
+			q = priv->ring_data[tc_info->tqp_offset + j].ring->tqp;
+			hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG,
+				       tc_info->tc);
+		}
+	}
+}
+
 int hns3_init_all_ring(struct hns3_nic_priv *priv)
 {
 	struct hnae3_handle *h = priv->ae_handle;
@@ -3409,6 +3431,8 @@  int hns3_nic_reset_all_ring(struct hnae3_handle *h)
 		rx_ring->next_to_use = 0;
 	}
 
+	hns3_init_tx_ring_tc(priv);
+
 	return 0;
 }
 
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
index e4b4a8f2ceaab..902b751206608 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
@@ -38,6 +38,7 @@  enum hns3_nic_state {
 #define HNS3_RING_TX_RING_BASEADDR_H_REG	0x00044
 #define HNS3_RING_TX_RING_BD_NUM_REG		0x00048
 #define HNS3_RING_TX_RING_BD_LEN_REG		0x0004C
+#define HNS3_RING_TX_RING_TC_REG		0x00050
 #define HNS3_RING_TX_RING_TAIL_REG		0x00058
 #define HNS3_RING_TX_RING_HEAD_REG		0x0005C
 #define HNS3_RING_TX_RING_FBDNUM_REG		0x00060